JP6490305B2 - 半導体装置および電力変換装置 - Google Patents
半導体装置および電力変換装置 Download PDFInfo
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- JP6490305B2 JP6490305B2 JP2018514108A JP2018514108A JP6490305B2 JP 6490305 B2 JP6490305 B2 JP 6490305B2 JP 2018514108 A JP2018514108 A JP 2018514108A JP 2018514108 A JP2018514108 A JP 2018514108A JP 6490305 B2 JP6490305 B2 JP 6490305B2
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Description
以下、本発明に係る実施の形態について説明する。なお、本発明は以下の記述に限定されるものではなく、本発明の要旨を逸脱しない範囲において適宜変更可能である。また、以下に示す図面においては、理解の容易のため、各部材の縮尺が実際とは異なる場合がある。これは各図面間においても同様である。
<装置構成>
図1はSiC基板上に形成されたMOS構造を有する電界効果トランジスタ(SiC−MOSFET)100の部分構成を模式的に示す断面図である。なお、図1では「セル」と呼称されるMOSの最小単位構造を破線で囲んで示しており、実際のSiC−MOSFET100は、複数のセルによって構成されている。
次に、製造工程を順に示す断面図である図6〜図13を用いて、SiC−MOSFET100の製造方法を説明する。なお、以下の説明で例として挙げる材料は同等の機能を有する材料に適宜変更可能である。
次に、図22を用いて、実施の形態1の変形例1に係るSiC−MOSFET100Aの構成を説明する。なお、図22においては、図1を用いて説明したSiC−MOSFET100と同一の構成については同一の符号を付し、重複する説明は省略する。
図23は、実施の形態1の変形例2に係るSiC−MOSFET100Bの構成を示す断面図である。なお、図23においては、図1を用いて説明したSiC−MOSFET100と同一の構成については同一の符号を付し、重複する説明は省略する。
図24は、実施の形態1の変形例3に係るSiC−MOSFET100Cの構成を示す断面図である。なお、図24においては、図1を用いて説明したSiC−MOSFET100と同一の構成については同一の符号を付し、重複する説明は省略する。
図25は、実施の形態1の変形例4に係るSiC−MOSFET100Dの構成を示す断面図である。なお、図25においては、図1を用いて説明したSiC−MOSFET100と同一の構成については同一の符号を付し、重複する説明は省略する。
図26はSiC基板上に形成されたSiC−MOSFET200の部分構成を模式的に示す断面図である。なお、図26においては、図1を用いて説明したSiC−MOSFET100と同一の構成については同一の符号を付し、重複する説明は省略する。
図31はSiC基板上に形成されたSiC−MOSFET300の部分構成を模式的に示す断面図である。なお、図30においては、図1を用いて説明したSiC−MOSFET100と同一の構成については同一の符号を付し、重複する説明は省略する。
次に、図32を用いて、実施の形態3の変形例に係るSiC−MOSFET300Aの構成を説明する。図32は、SiC−MOSFET300Aのセルの平面パターンを示す図であり、トレンチ6がストライプ状となった平面パターンにおいて、空乏化抑制層8がトレンチ6に沿ってストライプ状に配置された構成を例示している。そして、平面視形状がトレンチ6でストライプ状に規定される複数のボディ領域5のうち、1つのボディ領域5が途中でトレンチ60で分断された構成となっており、そこが図18を用いて説明した電位固定部17と同様の構成となっている。
以上説明した実施の形態1〜3においては、本発明をドリフト層2とSiC基板1(バッファ層含む)とが同じ導電型を有するMOSFETに適用した例を示したが、本発明はドリフト層2とSiC基板1とが異なる導電型を有するIGBTに対しても適用可能である。
本実施の形態は、上述した実施の形態1〜3に係る半導体装置を電力変換装置に適用したものである。本発明は特定の電力変換装置に限定されるものではないが、以下、実施の形態4として、三相のインバータに本発明を適用した場合について説明する。
Claims (11)
- 半導体基板と、
前記半導体基板の第1の主面上に配設された第1導電型の半導体層と、
前記半導体層の上層部に選択的に設けられた第1導電型の第1の半導体領域と、
前記半導体層の上層部に前記第1の半導体領域に接して設けられた第2導電型の第2の半導体領域と、
前記第1および第2の半導体領域の底面に接して設けられた第2導電型の第3の半導体領域と、
前記第1および第3の半導体領域を厚さ方向に貫通して複数設けられた、前記半導体層内に達するトレンチと、
前記トレンチの内面を覆うゲート絶縁膜と、
前記ゲート絶縁膜で覆われた前記トレンチ内に埋め込まれたゲート電極と、
前記トレンチの底部に接するように設けられた第2導電型のトレンチ底部保護層と、
隣り合う前記トレンチ底部保護層間に設けられた第1導電型の空乏化抑制層と、
前記トレンチおよびその周囲の前記第1の半導体領域の上方を覆い、前記第1および第2の半導体領域の上方にコンタクトホールを有する層間絶縁膜と、
前記層間絶縁膜上を覆うと共に、前記コンタクトホール内に埋め込まれた第1の主電極と、
前記半導体基板の第2の主面上に配設された第2の主電極と、を備え、
前記空乏化抑制層は、
隣り合う前記トレンチ底部保護層までの水平方向の距離が等しい中間点を含み、前記第3の半導体領域、前記トレンチおよび前記トレンチ底部保護層の何れとも接しない大きさに形成され、前記トレンチ底部保護層と同じ深さに位置し、同じ厚さを有し、その不純物濃度は前記半導体層よりも高く設定される半導体装置。 - 半導体基板と、
前記半導体基板の第1の主面上に配設された第1導電型の半導体層と、
前記半導体層の上層部に選択的に設けられた第1導電型の第1の半導体領域と、
前記半導体層の上層部に前記第1の半導体領域に接して設けられた第2導電型の第2の半導体領域と、
前記第1および第2の半導体領域の底面に接して設けられた第2導電型の第3の半導体領域と、
前記第3の半導体領域の底面に接するように設けられた第1導電型の不純物領域と、
前記第1および第3の半導体領域を厚さ方向に貫通して複数設けられた、前記半導体層内に達するトレンチと、
前記トレンチの内面を覆うゲート絶縁膜と、
前記ゲート絶縁膜で覆われた前記トレンチ内に埋め込まれたゲート電極と、
前記トレンチの底部に接するように設けられた第2導電型のトレンチ底部保護層と、
隣り合う前記トレンチ底部保護層間に設けられた第1導電型の空乏化抑制層と、
前記トレンチおよびその周囲の前記第1の半導体領域の上方を覆い、前記第1および第2の半導体領域の上方にコンタクトホールを有する層間絶縁膜と、
前記層間絶縁膜上を覆うと共に、前記コンタクトホール内に埋め込まれた第1の主電極と、
前記半導体基板の第2の主面上に配設された第2の主電極と、を備え、
前記空乏化抑制層は、
隣り合う前記トレンチ底部保護層までの水平方向の距離が等しい中間点を含み、前記第3の半導体領域、前記トレンチおよび前記トレンチ底部保護層の何れとも接しない大きさに形成され、その不純物濃度は前記半導体層よりも高く設定され、前記不純物領域は、前記空乏化抑制層とは離れた位置に設けられる半導体装置。 - 前記不純物領域は、
前記トレンチ底部保護層間における前記第3の半導体領域の底面のうち、水平方向の中央部分を除く領域に設けられる、請求項2記載の半導体装置。 - 前記トレンチ底部保護層は、前記第1の主電極と電気的に接続される、請求項1から請求項3の何れか1項に記載の半導体装置。
- 半導体基板と、
前記半導体基板の第1の主面上に配設された第1導電型の半導体層と、
前記半導体層の上層部に選択的に設けられた第1導電型の第1の半導体領域と、
前記半導体層の上層部に前記第1の半導体領域に接して設けられた第2導電型の第2の半導体領域と、
前記第1および第2の半導体領域の底面に接して設けられた第2導電型の第3の半導体領域と、
前記第1および第3の半導体領域を厚さ方向に貫通して複数設けられた、前記半導体層内に達するトレンチと、
前記トレンチの内面を覆うゲート絶縁膜と、
前記ゲート絶縁膜で覆われた前記トレンチ内に埋め込まれたゲート電極と、
前記トレンチの底部に接するように設けられた第2導電型のトレンチ底部保護層と、
隣り合う前記トレンチ底部保護層間に設けられた第1導電型の空乏化抑制層と、
前記トレンチおよびその周囲の前記第1の半導体領域の上方を覆い、前記第1および第2の半導体領域の上方にコンタクトホールを有する層間絶縁膜と、
前記層間絶縁膜上を覆うと共に、前記コンタクトホール内に埋め込まれた第1の主電極と、
前記半導体基板の第2の主面上に配設された第2の主電極と、を備え、
前記空乏化抑制層は、
隣り合う前記トレンチ底部保護層までの水平方向の距離が等しい中間点を含み、前記第3の半導体領域、前記トレンチおよび前記トレンチ底部保護層の何れとも接しない大きさに形成され、
前記空乏化抑制層の水平方向の位置は、前記トレンチの側壁までの水平方向の距離が、前記トレンチの側壁の結晶面の面方位に合わせて異なるように設定され、その不純物濃度は前記半導体層よりも高く設定される半導体装置。 - 前記空乏化抑制層の位置は、
第1の電子移動度を有する結晶面で構成される第1の側壁までの水平方向の距離が、前記第1の電子移動度よりも低い第2の電子移動度を有する結晶面で構成される第2の側壁までの水平方向の距離よりも広くなるように設定される、請求項5記載の半導体装置。 - 前記空乏化抑制層は、
第2導電型の耐圧維持層を有する、請求項1から請求項6の何れか1項に記載の半導体装置。 - 前記耐圧維持層は、前記トレンチ底部保護層と接続される、請求項7記載の半導体装置。
- 前記耐圧維持層は、
前記空乏化抑制層の水平方向の中央部分に設けられる、請求項7または請求項8記載の半導体装置。 - 前記第1の主電極は、
前記コンタクトホールを介して前記第1および第2の半導体領域とオーミック接触するように設けられる、請求項1から請求項9の何れか1項に記載の半導体装置。 - 請求項1から請求項10の何れか1項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
前記半導体装置を駆動する駆動信号を前記半導体装置に出力する駆動回路と、
前記駆動回路を制御する制御信号を前記駆動回路に出力する制御回路と、を備えた電力変換装置。
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