JP6482454B2 - 電子部品の製造方法ならびに電子部品製造装置 - Google Patents

電子部品の製造方法ならびに電子部品製造装置 Download PDF

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Publication number
JP6482454B2
JP6482454B2 JP2015247561A JP2015247561A JP6482454B2 JP 6482454 B2 JP6482454 B2 JP 6482454B2 JP 2015247561 A JP2015247561 A JP 2015247561A JP 2015247561 A JP2015247561 A JP 2015247561A JP 6482454 B2 JP6482454 B2 JP 6482454B2
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JP
Japan
Prior art keywords
resin
electronic component
substrate
semiconductor chip
grinding
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Active
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JP2015247561A
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English (en)
Japanese (ja)
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JP2017112317A (ja
Inventor
勝則 傳藤
勝則 傳藤
山本　雅之
雅之 山本
幹司 石橋
幹司 石橋
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Towa Corp
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Towa Corp
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Publication date
Application filed by Towa Corp filed Critical Towa Corp
Priority to JP2015247561A priority Critical patent/JP6482454B2/ja
Priority to KR1020187017784A priority patent/KR102261309B1/ko
Priority to PCT/JP2016/073389 priority patent/WO2017104169A1/ja
Priority to CN201680072617.1A priority patent/CN108431933B/zh
Priority to TW105126044A priority patent/TW201724391A/zh
Publication of JP2017112317A publication Critical patent/JP2017112317A/ja
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Publication of JP6482454B2 publication Critical patent/JP6482454B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)
JP2015247561A 2015-12-18 2015-12-18 電子部品の製造方法ならびに電子部品製造装置 Active JP6482454B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2015247561A JP6482454B2 (ja) 2015-12-18 2015-12-18 電子部品の製造方法ならびに電子部品製造装置
KR1020187017784A KR102261309B1 (ko) 2015-12-18 2016-08-09 전자 부품 및 그 제조 방법 및 전자 부품 제조 장치
PCT/JP2016/073389 WO2017104169A1 (ja) 2015-12-18 2016-08-09 電子部品およびその製造方法ならびに電子部品製造装置
CN201680072617.1A CN108431933B (zh) 2015-12-18 2016-08-09 电子零件及其制造方法和电子零件制造装置
TW105126044A TW201724391A (zh) 2015-12-18 2016-08-16 電子元件以及其製造方法與電子元件製造裝置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015247561A JP6482454B2 (ja) 2015-12-18 2015-12-18 電子部品の製造方法ならびに電子部品製造装置

Publications (2)

Publication Number Publication Date
JP2017112317A JP2017112317A (ja) 2017-06-22
JP6482454B2 true JP6482454B2 (ja) 2019-03-13

Family

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JP2015247561A Active JP6482454B2 (ja) 2015-12-18 2015-12-18 電子部品の製造方法ならびに電子部品製造装置

Country Status (5)

Country Link
JP (1) JP6482454B2 (ko)
KR (1) KR102261309B1 (ko)
CN (1) CN108431933B (ko)
TW (1) TW201724391A (ko)
WO (1) WO2017104169A1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019012714A (ja) * 2017-06-29 2019-01-24 株式会社ディスコ 半導体パッケージの製造方法
JP6609674B1 (ja) * 2018-07-11 2019-11-20 浜松ホトニクス株式会社 光検出装置及び光検出装置の製造方法
JP6994279B1 (ja) * 2021-05-12 2022-01-14 ハイソル株式会社 研磨方法、及び研磨用半導体チップ保持構造

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS552112U (ko) * 1978-06-21 1980-01-09
JPH04297056A (ja) 1991-03-08 1992-10-21 Sony Corp 半導体装置の製造方法
JPH06120295A (ja) * 1992-10-02 1994-04-28 Mitsubishi Electric Corp 半導体装置
JP4803855B2 (ja) * 1999-02-09 2011-10-26 三洋電機株式会社 半導体装置の製造方法
JP3339838B2 (ja) * 1999-06-07 2002-10-28 ローム株式会社 半導体装置およびその製造方法
DE10106346B4 (de) * 2001-02-09 2007-03-01 Infineon Technologies Ag Elektronisches Bauteil
JP3854814B2 (ja) * 2001-04-06 2006-12-06 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2003152005A (ja) * 2001-11-19 2003-05-23 Towa Corp 半導体素子の樹脂封止成形装置
JP4859814B2 (ja) * 2007-11-06 2012-01-25 株式会社東京精密 ウェーハ処理装置
JP5192790B2 (ja) * 2007-11-28 2013-05-08 Ｔｏｗａ株式会社 基板の切断方法及び装置
JP3142888U (ja) * 2008-03-28 2008-07-03 幸三 松井 パタークラブ
JP2010073803A (ja) * 2008-09-17 2010-04-02 Nec Electronics Corp 半導体装置の製造方法
TW201032300A (en) * 2009-02-27 2010-09-01 Advanced Semiconductor Eng Chip scale package and method of fabricating the same
JP2011222706A (ja) * 2010-04-08 2011-11-04 Canon Inc 半導体パッケージ
US9318404B2 (en) * 2013-02-05 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package
JP2014165324A (ja) * 2013-02-25 2014-09-08 Disco Abrasive Syst Ltd パッケージ基板の加工方法
US9252092B2 (en) * 2013-07-24 2016-02-02 Stats Chippac, Ltd. Semiconductor device and method of forming through mold hole with alignment and dimension control
JP6235391B2 (ja) * 2014-03-27 2017-11-22 Ｔｏｗａ株式会社 検査用治具、切断装置及び切断方法

Also Published As

Publication number Publication date
CN108431933A (zh) 2018-08-21
KR102261309B1 (ko) 2021-06-07
CN108431933B (zh) 2021-07-13
TW201724391A (zh) 2017-07-01
WO2017104169A1 (ja) 2017-06-22
KR20180095829A (ko) 2018-08-28
JP2017112317A (ja) 2017-06-22

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