JP6469705B2 - エッチング後のインターフェースを安定化し、次の処理ステップ前のキュータイム問題を最小化する方法 - Google Patents
エッチング後のインターフェースを安定化し、次の処理ステップ前のキュータイム問題を最小化する方法 Download PDFInfo
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- JP6469705B2 JP6469705B2 JP2016541966A JP2016541966A JP6469705B2 JP 6469705 B2 JP6469705 B2 JP 6469705B2 JP 2016541966 A JP2016541966 A JP 2016541966A JP 2016541966 A JP2016541966 A JP 2016541966A JP 6469705 B2 JP6469705 B2 JP 6469705B2
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
- H01L2221/1063—Sacrificial or temporary thin dielectric films in openings in a dielectric
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Description
を含むフッ化アンモニウム(NH4F.HF)とのエッチャントが処理チャンバ100の処理領域141に導入され基板表面上に達すると、フッ化アンモニウム(NH4F)とHFを含むフッ化アンモニウム(NH4F.HF)とのエッチャントは、材料層404の酸化ケイ素などの誘電体材料と反応し得、大部分は固体の(NH4)2SiF6を形成する。フッ化アンモニウム(NH4F)とHFを含むフッ化アンモニウム(NH4F.HF)とのエッチャントは、処理された誘電体バリア層412と化学反応し、固体の(NH4)2SiF6を形成し、これが後に、ブロック308で更に後述する低温昇華処理を用いて基板表面から除去される。
Claims (15)
- 基板上に配置された誘電体バリア層をエッチングする方法であって、
誘電体バリア層が配置された基板を、エッチング処理チャンバ内へ移送すること、
前記誘電体バリア層に処理工程を実施すること、
前記基板上に配置された前記処理された誘電体バリア層をエッチングするために、前記エッチング処理チャンバ内に供給されるエッチング混合ガス中にプラズマを遠隔で発生させること、
前記誘電体バリア層を前記基板から除去するために、エッチングされた前記誘電体バリア層をプラズマアニーリングすること、及び
前記誘電体バリア層が前記基板から除去された後にインターフェース保護層を形成すること
を含む、方法。 - 前記エッチング混合ガス中に前記プラズマを遠隔で発生させることが、
前記エッチング混合ガス中に、アンモニウムガス及び三フッ化窒素を、約5:1から約30:1のモル比で供給すること
を更に含む、請求項1に記載の方法。 - 前記エッチング混合ガス中に前記プラズマを遠隔で発生させることが、
基板温度を摂氏約100度未満で維持することを更に含む、請求項1に記載の方法。 - エッチングされた前記誘電体バリア層をプラズマアニーリングすることが、
前記基板からエッチング副生成物を昇華させることを更に含む、請求項1に記載の方法。 - 前記誘電体バリア層が炭化ケイ素層である、請求項1に記載の方法。
- 前記エッチング混合ガス中に前記プラズマを遠隔で発生させることが、
前記エッチング混合ガスから前記プラズマを遠隔で発生させるために、RFソース電力を印加することを更に含む、請求項1に記載の方法。 - 前記RFソース電力が約80kHzの周波数を有する、請求項6に記載の方法。
- 前記インターフェース保護層を形成することが、
少なくとも一種のキャリアガスに随伴するポリマーガスを、前記エッチング処理チャンバ内に供給することを更に含む、請求項1に記載の方法。 - 前記キャリアガスが、アルゴンガス(Ar)、ヘリウムガス(He)、一酸化窒素(NO)、一酸化炭素(CO)、亜酸化窒素(N2O)、酸素ガス(O2)、又は窒素ガス(N2)のうちの少なくとも一種である、請求項8に記載の方法。
- 前記ポリマーガスが、フルオロアルキルポリオキシエチレン、ポリジメチルシロキサン、トリメチルシラン、テトラメチルシラン、オクタメチルシクロテトラシラン(OMCTS)、又はヘキサメチルジシリアン(HMDS)のうちの少なくとも一種である、請求項8に記載の方法。
- 前記インターフェース保護層が酸化ケイ素層である、請求項1に記載の方法。
- 前記基板上の前記誘電体バリア層を除去するために、エッチングされた前記誘電体バリア層を前記プラズマアニーリングすることが、
前記誘電体バリア層が除去された後に、前記基板中に配置された導電層を露出すること
を更に含む、請求項1に記載の方法。 - エッチングされた前記誘電体バリア層をプラズマアニーリングすることが、
前記基板をプラズマアニーリングするためのプラズマを発生させるために、300ワット未満のRFバイアス電力を印加すること
を更に含む、請求項1に記載の方法。 - エッチングされた前記誘電体バリア層をプラズマアニーリングすることが、
基板温度を摂氏約20度から摂氏約150度に維持すること
を更に含む、請求項1に記載の方法。 - 基板上に配置された誘電体バリア層をエッチングする方法であって、
基板上のデュアルダマシン構造中に誘電体バリア層が配置された基板を、エッチング処理チャンバ内に移送すること、
前記誘電体バリア層を処理するために、前記エッチング処理チャンバ内の処理混合ガス中に、第1の低いRFバイアス電力を印加すること、
エッチング混合ガス中に、前記エッチング処理チャンバから遠隔で、RFソース電力を印加することであって、前記エッチング混合ガスがアンモニウムガス及び三フッ化窒素を含む、印加すること、
エッチングされた前記誘電体バリア層をアニーリングして前記誘電体バリア層を前記基板から除去するために、前記エッチング処理チャンバ内のアニーリング混合ガス中に、第2の低いRFバイアス電力を印加すること、並びに
前記誘電体バリア層が前記基板から除去された後にインターフェース保護層を形成すること
を含む、方法。
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US14/029,771 US20150079799A1 (en) | 2013-09-17 | 2013-09-17 | Method for stabilizing an interface post etch to minimize queue time issues before next processing step |
US14/029,771 | 2013-09-17 | ||
PCT/US2014/048491 WO2015041746A1 (en) | 2013-09-17 | 2014-07-28 | Methods for stabilizing an interface post etch to minimize queue time issues before next processing step |
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US10373850B2 (en) * | 2015-03-11 | 2019-08-06 | Asm Ip Holding B.V. | Pre-clean chamber and process with substrate tray for changing substrate temperature |
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CN112204169A (zh) * | 2018-05-16 | 2021-01-08 | 应用材料公司 | 原子层自对准的基板处理和整合式成套工具 |
KR102554014B1 (ko) * | 2018-06-15 | 2023-07-11 | 삼성전자주식회사 | 저온 식각 방법 및 플라즈마 식각 장치 |
WO2020033405A1 (en) * | 2018-08-08 | 2020-02-13 | Tokyo Electron Limited | Method utilizing using post etch pattern encapsulation |
CN109559988A (zh) * | 2018-11-30 | 2019-04-02 | 德淮半导体有限公司 | 硅片的制备方法及装置 |
KR20210035449A (ko) * | 2019-09-24 | 2021-04-01 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US20230031381A1 (en) * | 2021-07-31 | 2023-02-02 | Applied Materials, Inc. | Apparatus for removing etch stop layers |
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- 2014-07-28 WO PCT/US2014/048491 patent/WO2015041746A1/en active Application Filing
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WO2015041746A1 (en) | 2015-03-26 |
KR20160055227A (ko) | 2016-05-17 |
CN105745740B (zh) | 2019-11-26 |
TWI640040B (zh) | 2018-11-01 |
JP2016530729A (ja) | 2016-09-29 |
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