CN108352317A - 具有多重类型腔室的积层蚀刻*** - Google Patents
具有多重类型腔室的积层蚀刻*** Download PDFInfo
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Abstract
本文所描述的实施方式一般涉及基板处理***,诸如蚀刻处理***。在一个实施方式中,本文公开了一种基板处理***。基板处理***包含移送腔室和耦接至移送腔室的多个处理腔室。多个处理腔室包含第一处理腔室、第二处理腔室和第三处理腔室。第一处理腔室经构造以定向修改形成在基板上的膜堆叠的表面。第二处理腔室经构造以将蚀刻剂沉积至膜堆叠的表面上。第三处理腔室经构造以将膜堆叠暴露至高温升华工艺。
Description
技术领域
本文所描述的实施方式涉及用于基板处理的蚀刻***,更特定而言,涉及具有多种类型腔室的集成层蚀刻***。
背景技术
可靠地生产亚半微米(sub-half micron)与更小的特征,是下一代超大型集成电路(VLSI)与特大型集成电路(ULSI)半导体装置的一个关键科技挑战。然而,随着电路技术的限制向前推进,VLSI与ULSI技术的不断缩小的尺寸对工艺能力产生了额外的要求。在基板上可靠地形成栅极结构,对于VLSI与ULSI的成功是重要的,对于提升个别基板与裸片的电路密度与品质的持续努力也是重要的。
随着下一代装置的电路密度提升,互连结构(诸如过孔、沟槽、触点、栅极结构和其它特征)的宽度和互连结构之间的介电材料的宽度,下降到45nm与32nm尺寸,而介电材料层的厚度维持大致恒定,而使得特征的深宽比提升。为了实现下一代装置与结构的制造,时常利用三维(3D)堆叠半导体芯片以提升晶体管的效能。通过设置三维晶体管来代替传统的二维晶体管,在集成电路(IC)中可将多个晶体管放置为非常靠近彼此。半导体芯片的三维(3D)堆叠减少了线长度,并使布线延迟低。在生产半导体芯片的三维(3D)堆叠过程中,时常利用梯形结构以允许在梯形结构上放置多个互连结构,从而形成高密度的垂直晶体管装置。
因此,需要改进的基板处理方法,以持续降低集成电路的生产成本、存储单元尺寸、和功率消耗。
发明内容
本文所描述的实施方式一般而言涉及基板处理***,诸如蚀刻处理***。在一个实施方式中,公开一种基板处理***,包含移送腔室和耦接至移送腔室的多个处理腔室。多个处理腔室包含第一处理腔室、第二处理腔室和第三处理腔室。第一处理腔室经构造以定向修改膜堆叠的表面,此膜堆叠形成于在第一处理腔室内处理的基板上。第二处理腔室经构造以将蚀刻剂沉积至膜堆叠的表面上。第三处理腔室经构造以将膜堆叠暴露至高温升华工艺。
在另一实施方式中,本文公开一种用于处理基板的方法。方法包含:定向修改沉积在基板的表面上的膜堆叠的暴露层;将蚀刻剂选择性地沉积至暴露层的经修改的表面上;和将基板暴露至高温升华工艺。
在另一实施方式中,本文公开了另一基板处理***。基板处理***包含移送腔室、耦接至移送腔室的多个处理腔室、和基板处理器(handler)。多个处理腔室包含第一处理腔室、第二处理腔室、第三处理腔室、和第四处理腔室。第一处理腔室经构造以定向修改膜堆叠的表面,此膜堆叠形成于在第一处理腔室内处理的基板上。第二处理腔室经构造以将蚀刻剂沉积至膜堆叠的表面上。第三处理腔室经构造以将膜堆叠暴露至高温升华工艺。第四处理腔室经构造以蚀刻膜堆叠。基板处理器设置在移送腔室中,且基板处理器经构造以在处理腔室之间移送基板。
附图说明
可参考多个实施方式来获得上文简要总结的本公开内容的更特定的说明,以更详细了解本公开内容的上述特征,附图图示了其中一些实施方式。然而应注意到,附图仅图示本公开内容的典型实施方式,且因此不应被视为限制本公开内容的保护范围,因为公开内容可允许其它等效的实施方式。
图1为根据一个实施方式的,适合用于硅材料移除工艺的说明性处理腔室的截面图。
图2为根据一个实施方式的,适合用于执行图案化工艺的处理腔室的一个示例的剖视图。
图3绘示了根据一个实施方式的半导体处理***的平面图。
图4绘示了根据另一实施方式的半导体处理***的平面图。
图5图示了根据一个实施方式的用于处理基板的方法的一个实施方式的流程图。
图6A至图6E图示了根据一个实施方式的,在图5的方法的不同阶段的基板截面图。
为了清楚说明,已尽可能使用相同的附图标记来标定图式之间共通的相同元件。此外,一个实施方式的元件可被有益地适用于本文描述的其它实施方式中。
具体实施方式
图1图示了根据一个示例的处理腔室100。处理腔室100可经构造以从设置在基板表面上的材料层移除材料。处理腔室100特别有用于执行等离子体辅助干式蚀刻工艺。
处理腔室100包含腔室主体112,腔室主体112界定处理区域141。盖组件123设置在腔室主体112的顶端,并限制处理区域141。支撑组件180设置在盖组件123下方,并至少部分位于腔室主体112内。
腔室主体112包含形成在腔室主体112侧壁中的狭缝阀开口114,以提供对处理腔室100的处理区域141的接取(access)。狭缝阀开口114通过闸(未图示)而被选择性地开启与关闭,以允许通过晶片处理机器人(也未图示)接取腔室主体112的处理区域141。
在一个或多个实施例中,腔室主体112包含形成于腔室主体112中的通道115,以用于使热传递流体流过其中。腔室主体112可进一步包含衬垫120,衬垫120围绕支撑组件180。衬垫120可被移除,以供服务与清洗。在一个或多个实施方式中,衬垫120包含形成于衬垫120中的一个或多个孔125与泵通道129,泵通道129与真空***流体连通。孔125提供流动路径以让气体流入泵通道129,为处理腔室100内的气体提供了出口。
真空***可包含真空泵130与节流阀132,以调节通过处理腔室100的气体流。真空泵130耦接至设置在腔室主体112中的真空端口131,真空端口131与形成在衬垫120内的泵通道129流体连通。
远程等离子体***110可处理含卤素的前驱物,例如含氟前驱物。含卤素前驱物接着行进通过气体入口组件111。两个不同的气体供应通道(第一通道109与第二通道113)存在于气体入口组件111内。在一个示例中,第一通道109携带通过远程等离子体***110(RPS)的气体,同时第二通道113绕过远程等离子体***110。盖组件123与具有多个贯孔156的喷淋头153由绝缘环124间隔开,绝缘环124允许相对于喷淋头153向盖组件123施加AC电位。盖组件123与喷淋头153之间的AC电位可足以激发界定在盖组件123与喷淋头153之间的腔室等离子体区域121中的等离子体。
支撑组件180可包含支撑构件185,支撑构件185经构造以支撑要在腔室主体112内处理的基板(未图示于图1)。支撑构件185可通过杆187耦接至升降机构183,杆187延伸通过形成在腔室主体112的底表面中的中央定位的开口116。可通过波纹管188将升降机构183弹性密封至腔室主体112,以防止真空从杆187周围泄漏。支撑组件180可进一步包含沿着支撑构件185设置的边缘环196。
支撑构件185可包含穿过支撑构件185而形成的穿孔192,以容纳升举销193,图1图示其中一个升举销。当升举销193被设置在腔室主体112内的可动环形升举环195移位时,升举销193在升举销193各自的穿孔192内是可移动的。
可由循环通过流体通道198的流体控制支撑组件180的温度,流体通道198嵌入支撑构件185的主体中。在一个或多个实施例中,流体通道198与热传递导管199流体连通,热传递导管199穿过支撑组件180的杆187而被设置。流体通道198沿着支撑构件185定位,以从热传递导管199提供均匀的热传递至支撑构件185的基板接收表面。根据需要,流体通道198与热传递导管199可流动热传递流体以加热或冷却支撑构件185。
控制器170耦接至处理腔室100,以控制处理腔室100的操作。控制器170包含中央处理单元(CPU)172、存储器174和支持电路176,用于控制工艺流程并调节来自气体面板178的气体流动。CPU 172可为可用于工业设定中的任何形式的通用计算机处理器。软件程序可被储存在存储器174中,诸如随机存取存储器、只读存储器、软盘、或硬盘驱动器、或其它形式的数字储存。支持电路176以传统方式耦接至CPU 172,并可包含高速缓存、时钟电路、输入/输出***、电源供应器、和类似者。通过多个信号缆线来处理控制器170与处理腔室100各种部件之间的双向通信。
图2根据一个示例图示处理腔室200。处理腔室200包含腔室主体202与盖204,腔室主体202与盖204围绕内部容积206。腔室主体202一般包含侧壁208与底部210。可在侧壁208中界定基板支撑基座接取端口(未图示),并由狭缝阀选择性密封,以促进基板201进入与离开处理腔室200。在腔室主体202中界定排气口226,且排气口226将内部容积206耦接至泵***228。
气体面板258耦接至处理腔室200,以向内部容积206提供处理气体及/或清洁气体。在图2绘示的示例中,入口端口232’、232”被提供于盖204中,以允许气体从气体面板258传递至处理腔室200的内部容积206。
喷淋头组件230被耦接至盖204的内部表面214。喷淋头组件230包含多个孔,这些孔允许气体以跨越在处理腔室200中正被处理的基板201的表面的预定分布从入口端口232’、232”流动通过喷淋头组件230至处理腔室200的内部容积206中。
远程等离子体源277可被可选地耦接至气体面板258,以在进入内部容积206用于处理之前促进从远程等离子体分离混合气体。RF电源243通过匹配网路241而被耦接至喷淋头组件230。
基板支撑台座组件248设置在处理腔室200的内部容积206中,并位于喷淋头组件230下方。基板支撑台座组件248在处理期间支撑基板201。基板支撑台座组件248一般包含穿过基板支撑台座组件248而设置的多个升举销(未图示),这些升举销经构造以从基板支撑台座组件248升举基板201,并促进以传统方式由机器人(未图示)交换基板201。
在一个实施例中,基板支撑台座组件248包含安装板262、基座264和静电吸盘266。安装板262耦接至腔室主体202的底部210,并包含用于将设施布线至基座264与静电吸盘266的通道。静电吸盘266包含至少一个夹持电极280,以将基板201保持在喷淋头组件230下方。静电吸盘266由吸附电源282驱动而产生静电力,此静电力将基板201保持至吸附表面,如通常所知。或者,可通过夹持、真空或重力而将基板201保持至基板支撑台座组件248。
基座264或静电吸盘266的至少一者,可包含至少一个可选的嵌入式加热器276、至少一个可选的嵌入式隔离器274和多个导管268、270,以控制基板支撑台座组件248的横向温度分布。导管268、270被流动耦接至流体源272,流体源272使温度调节流体循环通过导管268、270。由电源278调节加热器276。利用导管268、270与加热器276来控制基座264的温度,由此加热及/或冷却静电吸盘266。可使用多个温度传感器290、292监测静电吸盘266与基座264的温度。
在一个实施例中,基板支撑台座组件248被构造为阴极,且包含耦接至多个RF偏压电源284、286的电极280。通过匹配电路288将RF偏压电源284、286耦接至设置在基板支撑台座组件248中的电极280和另一电极。可将额外的偏压电源289耦接至电极280,以控制等离子体的特性。RF偏压电力激发并维持由设置在腔室主体202的处理区域中的气体形成的等离子体放电。
将控制器250耦接至处理腔室200以控制处理腔室200的操作。控制器250包含中央处理单元(CPU)252、存储器254和支持电路256,以控制工艺流程并调节来自气体面板258的气体流动。CPU 252可为可用于工业设定中的任何形式的通用计算机处理器。软件程序可被储存在存储器254中,诸如随机存取存储器、只读存储器、软盘、或硬盘驱动器、或其它类型的数字储存。支持电路256以传统方式耦接至CPU 252,并可包含高速缓存、时钟电路、输入/输出***、电源供应器和类似者。由多个信号缆线处理控制器250与处理腔室200的各种部件之间的双向通信。
图3图示半导体处理***300,本文所描述的方法可在半导体处理***300上实施。可适于从本发明受益的一种处理***为300mmProducerTM处理***(可从美国加州圣塔克拉拉市的应用材料公司商业购买)。处理***300可包含移送腔室302,和耦接至移送腔室302的多个处理腔室304a-304c。处理***可进一步包含前端平台306、前开式标准舱(frontopening unified pods;FOUPs)308、负载锁定腔室310和基板处理器312。
前端平台306支撑包含在FOUPs 308中的基板匣314。基板被装载进入负载锁定腔室310、容纳基板处理器312的移送腔室302、和一系列的处理腔室304a-304c(和从上述腔室卸载)。负载锁定腔室310可对引入处理***300的基板抽气(pump down)以维持真空密封。
可装配每个处理腔室304a-304c以执行数个基板操作。例如,处理腔室304a可为用于基板表面的定向修改的腔室(诸如适当调适的Sym3TM腔室);处理腔室304b可为用于沉积蚀刻剂的沉积腔室(诸如适当调适的FrontierTM腔室);且处理腔室304c可为用于升华的高温腔室。
控制器320可经构造以操作处理***300的所有方面,诸如下面连同图5讨论的方法。例如,控制器320可经构造以控制在基板上形成金属互连的方法。控制器320包含耦接至处理***的各种部件以促进控制基板处理的可编程中央处理单元(CPU)322(诸如电源供应器、时钟、高速缓存、输入/输出(I/O)电路、和衬垫),CPU 322可与存储器324及大容量储存装置、输入控制单元和显示单元(未图示)操作。控制器320也包含硬件以通过处理***300中的传感器监测基板处理,包含监测前驱物、处理气体和净化气体流的传感器。其它测量***参数(诸如基板温度、腔室气压及类似者)的传感器,也可向控制器320提供信息。
为了促进控制上文所描述的处理***300,CPU 322可为一种可用于工业设定中的任何形式的通用计算机处理器,诸如可编程逻辑控制器(PLC),以控制各种腔室与子处理器。存储器324耦接至CPU 322,且存储器324为非暂态的,并可为一种或多种可轻易取得的存储器,诸如位于本地或远程的随机存取存储器(RAM)、只读存储器(ROM)、软盘驱动器、硬盘、或的任何其它形式的数字储存。支持电路326耦接至CPU 322以传统方式支持处理器。带电物种生成(Charged species generation)、加热及其它工艺,通常作为软件程序而被一般地储存在存储器324。软件程序也可由第二CPU(未图示)储存及/或执行,第二CPU位于由CPU 322控制的硬件的远程处。
存储324的形式是计算机可读取储存媒体,计算机可读取储存媒体包含指令,当这些指令由CPU 322执行时促进处理***300的操作。存储器324中的指令的形式为程序产品,诸如实施本公开内容的方法的程序。程序代码可符合数种不同的程序语言的任一者。在一个示例中,本公开内容可被实施为储存在计算机可读取储存媒体上、与计算机***一起使用的程序产品。程序产品中的程序界定实施方式的功能(包含本文所说明的方法)。说明性的计算机可读取储存媒体包含(但不限于):(1)不可写入式储存媒体(例如计算机内的只读存储器装置(诸如由只读光盘驱动器读取的只读光盘)、闪存存储器、ROM芯片、或任何类型的固态非易失性半导体存储器),信息被永久性储存在这种不可写入式储存媒体上;和(2)可写入式储存媒体(例如软盘驱动器内的软片或硬盘驱动器或任何类型固态随机存取半导体存储器),可改变的信息被储存在这种可写入式储存媒体上。此种计算机可读取储存媒体在携带针对本文所述方法的功能的计算机可读取指令时,为本公开内容的实施方式。
图4图示说明根据一个实施方式的半导体处理***400。半导体处理***400类似于半导体处理***300。然而在半导体处理***400中,高温腔室304c被移动至负载锁定腔室的位置(在图3中)。半导体处理***400进一步包含耦接至移送腔室302的腔室404。在一个示例中,腔室404可为化学气相沉积(CVD)腔室。
图5为图示用于处理基板的方法500的一个实施方式的流程图。图6A至图6E图示图500的方法500的不同阶段的基板截面图。
图6A绘示基板600。基板600上沉积了膜堆叠601,膜堆叠601包含蚀刻终止层602、图案化结构604和间隔(spacer)层606。蚀刻终止层602被沉积在基板600表面上。图案化结构604被沉积在蚀刻终止层602上。在图案化结构604之间形成多个开口610。多个开口610暴露蚀刻终止层602的部分612。间隔层606被沉积在图案化结构604的侧壁614和暴露部分612上。间隔层606可为不同于被选为蚀刻终止层602的材料的介电材料。
方法500开始于方块502。在方块502,基板600的暴露层由活性化学基等离子体(active chemistry based plasma)定向修改,如图6B图示。例如,由非活性等离子体处理(non-active plasma treatment)616定向修改暴露层。在一个实施方式中,可在腔室304a中执行非活性等离子体处理。可使用***气体产生非活性等离子体处理616。
在方块504,蚀刻剂618被选择性沉积在暴露层的修改表面上,如图6C图示。蚀刻剂可由下游等离子体在低压低温环境下沉积,诸如在腔室304b中。
在方块506中,基板600被暴露至高温升华工艺,如图6D图示。可在高温处理腔室(诸如腔室304c)中执行高温升华工艺。高温升华工艺经构造以通过移除沉积在方块504中的蚀刻剂618,来暴露图案化结构604。可重复执行方块502-506,直到图案化结构604被暴露为止。
在一个实施方式中,方法500进一步包含方块508。在方块508,基板600经受蚀刻工艺以暴露开口610中的蚀刻终止层602,如图6E图示。例如,基板600可被移送至CVD腔室,诸如图4中的腔室404。在移送之后,通过蚀刻工艺暴露开口610中的蚀刻终止层602。
虽然前述内容关于特定实施方式,但在不脱离前述内容的基本范围的情况下,可设想其它与进一步的实施方式,且前述内容的范围由所附权利要求书所确定。
Claims (15)
1.一种用于处理基板的处理***,包括:
移送腔室;和
多个处理腔室,所述多个处理腔室耦接至所述移送腔室,所述多个处理腔室包括:
第一处理腔室,所述第一处理腔室经构造以定向修改沉积在所述基板上的膜堆叠的表面;
第二处理腔室,所述第二处理腔室经构造以将蚀刻剂沉积至所述膜堆叠的所述表面上;和
第三处理腔室,所述第三处理腔室经构造以将所述膜堆叠暴露至高温升华工艺。
2.根据权利要求1所述的处理***,其中所述多个处理腔室进一步包括:
第四处理腔室,所述第四处理腔室经构造以蚀刻所述基板。
3.一种用于处理基板的处理***,包含:
移送腔室;
多个处理腔室,所述多个处理腔室耦接至所述移送腔室,所述多个处理腔室包括:
第一处理腔室,所述第一处理腔室经构造以定向修改沉积在所述基板上的膜堆叠的表面;
第二处理腔室,所述第二处理腔室经构造以将蚀刻剂沉积至所述膜堆叠的所述表面上;
第三处理腔室,所述第三处理腔室经构造以将所述膜堆叠暴露至高温升华工艺;和
第四处理腔室,所述第四处理腔室经构造以蚀刻所述膜堆叠;和基板处理器,所述基板处理器设置在所述移送腔室中,且所述基板处理器经构造以在这些处理腔室之间移送所述基板。
4.根据权利要求1或3所述的处理***,其中所述第一处理腔室经构造以使用非反应性气体定向修改所述膜堆叠的所述表面。
5.根据权利要求4所述的处理***,其中第一处理腔室耦接至气体面板,所述气体面板经构造以氢气的形式提供所述非反应性气体。
6.根据权利要求1或3所述的处理***,其中所述第二处理腔室耦接至气体面板,所述气体面板经构造以提供氟。
7.根据权利要求1或3所述的处理***,其中所述第三处理腔室包括加热器,所述加热器能够***作以将所述第三处理腔室的温度维持在摄氏80度至摄氏100度之间。
8.根据权利要求7所述的处理***,其中所述第三处理腔室被提升至一定压力。
9.一种用于处理基板的方法,包括以下步骤:
定向修改沉积在所述基板的表面上的膜堆叠的暴露层;
将蚀刻剂选择性的沉积至所述暴露层的经修改的表面上;和
将所述基板暴露至高温升华工艺。
10.根据权利要求9所述的方法,所述方法进一步包括:
蚀刻所述膜堆叠以暴露蚀刻终止层。
11.根据权利要求9所述的方法,其中所述定向修改沉积在基板的表面上的膜堆叠的暴露层的步骤,包括:
供应非反应性气体。
12.根据权利要求11所述的方法,其中所述非反应性气体为氢气的形式。
13.根据权利要求9所述的方法,其中所述将蚀刻剂选择性地沉积至暴露层的经修改的表面上的步骤,包括:
将含氟气体提供至所述暴露层的所述经修改的表面。
14.根据权利要求9所述的方法,其中所述将所述基板暴露至高温升华工艺的步骤,包括:
提升腔室的温度,所述基板在所述腔室中被暴露至所述高温升华工艺。
15.根据权利要求9所述的方法,其中所述定向修改沉积在基板的表面上的膜堆叠的暴露层的步骤,包括:
减少腔室中的压力,在所述腔室中沉积在所述基板的所述表面上的所述膜堆叠的所述暴露层被定向修改至5mT。
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US20150079799A1 (en) * | 2013-09-17 | 2015-03-19 | Applied Materials, Inc. | Method for stabilizing an interface post etch to minimize queue time issues before next processing step |
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US20050230350A1 (en) * | 2004-02-26 | 2005-10-20 | Applied Materials, Inc. | In-situ dry clean chamber for front end of line fabrication |
JP4727170B2 (ja) * | 2004-06-23 | 2011-07-20 | 東京エレクトロン株式会社 | プラズマ処理方法、および後処理方法 |
US8187486B1 (en) * | 2007-12-13 | 2012-05-29 | Novellus Systems, Inc. | Modulating etch selectivity and etch rate of silicon nitride thin films |
JP5554951B2 (ja) * | 2008-09-11 | 2014-07-23 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US8679983B2 (en) * | 2011-09-01 | 2014-03-25 | Applied Materials, Inc. | Selective suppression of dry-etch rate of materials containing both silicon and nitrogen |
US9666414B2 (en) * | 2011-10-27 | 2017-05-30 | Applied Materials, Inc. | Process chamber for etching low k and other dielectric films |
JP2015056519A (ja) * | 2013-09-12 | 2015-03-23 | 東京エレクトロン株式会社 | エッチング方法、エッチング装置及び記憶媒体 |
US8980758B1 (en) * | 2013-09-17 | 2015-03-17 | Applied Materials, Inc. | Methods for etching an etching stop layer utilizing a cyclical etching process |
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US20150079799A1 (en) * | 2013-09-17 | 2015-03-19 | Applied Materials, Inc. | Method for stabilizing an interface post etch to minimize queue time issues before next processing step |
US20150206764A1 (en) * | 2014-01-17 | 2015-07-23 | Applied Materials, Inc. | Titanium oxide etch |
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