JP6448852B2 - 電力用半導体装置 - Google Patents
電力用半導体装置 Download PDFInfo
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- JP6448852B2 JP6448852B2 JP2018510227A JP2018510227A JP6448852B2 JP 6448852 B2 JP6448852 B2 JP 6448852B2 JP 2018510227 A JP2018510227 A JP 2018510227A JP 2018510227 A JP2018510227 A JP 2018510227A JP 6448852 B2 JP6448852 B2 JP 6448852B2
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- 230000003247 decreasing effect Effects 0.000 claims 1
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- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
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Description
図1は、本発明の実施の形態1による電力用半導体装置1の構成の一例を示す断面図である。
図10は、本発明の実施の形態2による電力用半導体装置21の構成の一例を示す断面図である。
実施の形態1,2で説明したように、導電ペーストはエミッタ電極を平面視で覆うように形成することが望ましいが、電力用半導体装置のパターンまたは製造方法によってはエミッタ電極3の端部の直上に導電ペーストを形成することができない可能性がある。また、導電層および焼結金属層を同じ幅で形成すれば、製造工程における例えばスクリーン印刷を2回繰り返すことによって形成することができるため、製造が容易となる。本実施の形態3では、このような場合であっても放熱性を向上させて短絡耐量を確保することが可能な電力用半導体装置について説明する。
図14は、本発明の実施の形態4による電力用半導体装置31の構成の一例を示す断面図である。なお、図14において、F−Fで示す領域(以下、F−F領域という)は、エミッタ電極3の活性領域を示している。
Claims (15)
- 半導体基板上に形成され主電流が流れる表面電極と、
前記表面電極上に形成された焼結体でない第1の金属層と、
前記第1の金属層上に形成された焼結体である第2の金属層と、
を備え、
前記第2の金属層は、平面視において前記表面電極の全体を覆う大きさを有し、かつ前記第1の金属層よりも熱伝導性が高いことを特徴とする、電力用半導体装置。 - 前記第2の金属層は、平面視において前記表面電極の端部をはみ出す大きさを有することを特徴とする、請求項1に記載の電力用半導体装置。
- 前記第1の金属層は、平面視において前記表面電極の全体を覆い、かつ前記表面電極の端部をはみ出す大きさを有することを特徴とする、請求項1または2に記載の電力用半導体装置。
- 前記半導体基板は、前記半導体基板の表面に形成された活性領域と、前記活性領域を囲むように形成された終端領域とを有し、
前記半導体基板の前記終端領域において前記第1の金属層上に形成されたポリイミド層をさらに備え、
前記ポリイミド層は、前記第2の金属層と離間して形成されていることを特徴とする、請求項1から3のいずれか1項に記載の電力用半導体装置。 - 前記第2の金属層を覆うように形成されたはんだをさらに備え、
前記はんだは、前記第1の金属層とも接合されていることを特徴とする、請求項1から4のいずれか1項に記載の電力用半導体装置。 - 前記第1の金属層は、少なくとも前記はんだとの接合部分がAuであることを特徴とする、請求項5に記載の電力用半導体装置。
- 前記第2の金属層上に一端が接合された金属ワイヤーをさらに備えることを特徴とする、請求項1から4のいずれか1項に記載の電力用半導体装置。
- 半導体基板上に形成され主電流が流れる表面電極と、
前記表面電極上に形成された焼結体でない第1の金属層と、
前記第1の金属層上に形成された焼結体である第2の金属層と、
を備え、
前記半導体基板は、前記半導体基板の表面に形成された活性領域と、前記活性領域を囲むように形成された終端領域とを有し、
前記第1の金属層および前記第2の金属層は、平面視において前記活性領域を覆う大きさを有し、
前記第2の金属層を覆うように形成されたはんだをさらに備えることを特徴とする、電力用半導体装置。 - 半導体基板上に形成され主電流が流れる表面電極と、
前記表面電極上に形成された焼結体でない第1の金属層と、
前記第1の金属層上に形成された焼結体である第2の金属層と、
を備え、
前記半導体基板は、前記半導体基板の表面に形成された活性領域と、前記活性領域を囲むように形成された終端領域とを有し、
前記第1の金属層および前記第2の金属層は、平面視において前記活性領域を覆う大きさを有し、
前記第2の金属層上に一端が接合された金属ワイヤーをさらに備えることを特徴とする、電力用半導体装置。 - 半導体基板上に形成され主電流が流れる表面電極と、
前記表面電極上に形成された焼結体でない第1の金属層と、
前記第1の金属層上に形成された焼結体である第2の金属層と、
を備え、
前記半導体基板は、前記半導体基板の表面に形成された活性領域と、前記活性領域を囲むように形成された終端領域とを有し、
前記第1の金属層の端部および前記第2の金属層の端部は、平面視において前記活性領域と前記終端領域との境界位置から前記活性領域側に前記第2の金属層の厚み以下の距離を空けた位置に対応し、
前記第2の金属層を覆うように形成されたはんだをさらに備えることを特徴とする、電力用半導体装置。 - 半導体基板上に形成され主電流が流れる表面電極と、
前記表面電極上に形成された焼結体でない第1の金属層と、
前記第1の金属層上に形成された焼結体である第2の金属層と、
を備え、
前記半導体基板は、前記半導体基板の表面に形成された活性領域と、前記活性領域を囲むように形成された終端領域とを有し、
前記第1の金属層の端部および前記第2の金属層の端部は、平面視において前記活性領域と前記終端領域との境界位置から前記活性領域側に前記第2の金属層の厚み以下の距離を空けた位置に対応し、
前記第2の金属層上に一端が接合された金属ワイヤーをさらに備えることを特徴とする、電力用半導体装置。 - 前記第1の金属層および前記第2の金属層は、平面視において同じ幅であることを特徴とする、請求項8から11のいずれか1項に記載の電力用半導体装置。
- 平面視において前記活性領域と前記終端領域との境界位置から前記活性領域側に前記第2の金属層の厚さ以下の距離を空けた位置までの前記活性領域上に形成されたポリイミド層をさらに備えることを特徴とする、請求項8から12のいずれか1項に記載の電力用半導体装置。
- 前記第1の金属層は、Ni、Au、Niの合金、またはAuの合金からなり、
前記第2の金属層は、Ag焼結体またはCu焼結体からなることを特徴とする、請求項1から13のいずれか1項に記載の電力用半導体装置。 - 前記第2の金属層は、複数存在し、
各前記第2の金属層は、互いに空孔の単位体積当たりの密度が異なり、かつ前記第1の金属層上に前記空孔の単位体積当たりの密度が小さい順に積層して形成されることを特徴とする、請求項1から14のいずれか1項に記載の電力用半導体装置。
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US8643150B1 (en) * | 2012-02-15 | 2014-02-04 | Maxim Integrated Products, Inc. | Wafer-level package device having solder bump assemblies that include an inner pillar structure |
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US8716864B2 (en) * | 2012-06-07 | 2014-05-06 | Ixys Corporation | Solderless die attach to a direct bonded aluminum substrate |
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