JP6437246B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6437246B2 JP6437246B2 JP2014173454A JP2014173454A JP6437246B2 JP 6437246 B2 JP6437246 B2 JP 6437246B2 JP 2014173454 A JP2014173454 A JP 2014173454A JP 2014173454 A JP2014173454 A JP 2014173454A JP 6437246 B2 JP6437246 B2 JP 6437246B2
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Description
<関連技術の説明>
まず、実施の形態1における技術的思想を説明する前に、関連技術における再配線構造について説明し、この関連技術に存在する改善の余地を説明する。
続いて、関連技術に存在する改善の余地について説明する。図2は、関連技術に存在する第1の改善の余地を説明するための図であり、互いに隣り合うように配置された再配線RDL1と再配線RDL2とを示す図である。図2に示すように、関連技術では、例えば、再配線RDL1の側面に、銅の拡散を防止するバリア膜BFが存在しないことから、ポリイミド樹脂膜PI1とポリイミド樹脂膜PI2との界面に沿って銅のマイグレーションMG1が生じやすくなる。同様に、再配線RDL2の側面にも、銅の拡散を防止するバリア膜BFが存在しないことから、ポリイミド樹脂膜PI1とポリイミド樹脂膜PI2との界面に沿って銅のマイグレーションMG2が生じやすくなる。この結果、再配線RDL1と再配線RDL2との絶縁距離は、再配線RDL1と再配線RDL2との間の距離よりも狭い距離L1となる。このことは、再配線RDL1と再配線RDL2との間の耐圧が低下することを意味する。したがって、関連技術においては、ポリイミド樹脂膜PI1とポリイミド樹脂膜PI2との界面に沿った銅のマイグレーションによって、互いに隣り合う再配線RDL1と再配線RDL2との間での絶縁耐圧が低下することになる。この結果、関連技術では、半導体装置の信頼性低下を招くことになる。
図5は、本実施の形態1における半導体装置のデバイス構造の一例を示す断面図である。図5に示すように、例えば、シリコンからなる半導体基板1Sの主面には、集積回路を構成する複数の電界効果トランジスタQが形成されている。そして、この電界効果トランジスタQを覆うように層間絶縁膜が形成されており、この層間絶縁膜を貫通して、電界効果トランジスタQと電気的に接続されるプラグPLGが形成されている。そして、プラグPLGを形成した層間絶縁膜上には、例えば、ダマシン法によって、配線WL1が形成されている。この配線WL1は、プラグPLGを介して、電界効果トランジスタQと電気的に接続されている。ここで、図5では、図示を省略するが、配線WL1上には、多層配線が形成されており、この多層配線層を覆うように最上層の層間絶縁膜ILが形成されている。
続いて、本実施の形態1における特徴点について説明する。まず、本実施の形態1における第1特徴点は、図5に示すように、単層のポリイミド樹脂膜PIに開口部OP2と再配線溝WDとが一体的に形成されている点にある。これにより、単層のポリイミド樹脂膜PIに再配線RDLを形成することができるため、再配線RDLを構成する配線材料(銀)のマイグレーションを抑制することができる。なお、本明細書において、再配線RDLを構成する「配線材料」とは、特に、明示した場合を除き、再配線RDLの主要な膜である銀膜AGFの配線材料(銀)を示している。
本実施の形態1における半導体装置は、上記のように構成されており、以下にその製造方法について図面を参照しながら説明する。以下では、まず、フローチャートを使用して、本実施の形態1における半導体装置の製造方法の概要について説明し、その後、模式的な断面図を使用して、本実施の形態1における半導体装置の製造方法について説明する。
上述した本実施の形態1における半導体装置の製造方法の第1特徴点は、例えば、図12に示すように、インプリント技術を使用することにより、ポリイミド樹脂膜PIに開口部OP2と再配線溝WDとを一体的に形成する点にある。これにより、本実施の形態1における第1特徴点によれば、開口部OP2および再配線溝WDの形成にフォトリソグラフィ技術(露光・現像処理)を使用しなくても済むため、製造コストを削減できる。
上述した実施の形態1では、例えば、図5に示すように、ポリイミド樹脂膜PIに開口部OP2と再配線溝WDとを一体的に形成する例について説明している。この場合、再配線RDLの下層の構造設計の自由度を拡大する利点を得ることができる。ただし、本実施の形態1における技術的思想は、これに限らず、例えば、変形例として、ポリイミド樹脂膜PIに開口部OP2を形成せずに、再配線溝WDだけを形成して、この再配線溝WDと、表面保護膜PASに形成されている開口部OP1とを直接連通させるように構成することもできる。特に、表面保護膜PASの機械的強度の向上対策が実施されている場合や、表面保護膜PASの膜厚が厚い場合には、本変形例の構成が有用である。
前記実施の形態1では、再配線RDLの配線材料として銀膜AGFを使用する例について説明したが、本実施の形態2では、再配線RDLの配線材料として銅膜CUFを使用する例について説明する。本実施の形態2における半導体装置のデバイス構造は、前記実施の形態1における半導体装置のデバイス構造とほぼ同様の構成をしているため、相違点を中心に説明することにする。
図18は、本実施の形態2における半導体装置のデバイス構造を示す模式的な断面図である。図18において、再配線RDLは、バリア膜BFと密着膜CFと銅を主成分とする銅膜CUFとから構成されている。そして、再配線RDLを構成する銅膜CUFの表面の一部領域上にワイヤ接続用導体膜WCFが形成されており、このワイヤ接続用導体膜WCF上にワイヤWが接続されている。なお、ワイヤ接続用導体膜WCFは、例えば、銀膜や銀合金膜から形成することができる。
本実施の形態2における半導体装置は、上記のように構成されており、以下に、その製造方法について、図面を参照しながら説明する。
続いて、本実施の形態2の変形例1について説明する。図23は、本変形例1における再配線構造を模式的に示す断面図である。図23に示すように、本変形例1においては、再配線RDLを構成する銅膜CUFの表面の全体にわたって、ワイヤ接続用導体膜WCFが形成されている。この場合、ワイヤWの接続位置にフレキシビリティを持たせることができる。この場合も、ワイヤ接続用導体膜WCFは、印刷法を使用して形成することができるが、これに限らず、例えば、無電解めっき法を使用することもできる。
次に、本実施の形態2の変形例2について説明する。図24は、本変形例2における再配線構造を模式的に示す断面図である。図24に示すように、本変形例2においては、再配線RDLを構成する銅膜CUFの表面の一部領域上にワイヤ接続用導体膜WCFが形成されており、このワイヤ接続用導体膜WCF上にワイヤWが接続されている。一方、銅膜CUFの表面の一部領域以外のその他の領域は、絶縁膜IF1で覆われている、これにより、絶縁膜IF1によって、再配線RDLの表面を保護することができるとともに、再配線RDLの表面に導電異物が付着することによって、互いに隣り合う再配線RDL間にショート不良が発生することを抑制できる効果も得ることができる。
続いて、本実施の形態2の変形例3について説明する。図25は、本変形例3における再配線構造を模式的に示す断面図である。図25に示すように、本変形例3においても、変形例2と同様に、再配線RDLを構成する銅膜CUFの表面の一部領域以外の他の領域を覆うように絶縁膜IF1が形成されている。そして、本変形例3においては、銅膜CUFの表面の一部領域から絶縁膜IF1上の部分領域にわたって延在するようにワイヤ接続用導体膜WCFが形成されており、このワイヤ接続用導体膜WCFにワイヤWが接続している。このとき、ワイヤ接続用導体膜WCFは、例えば、スパッタリング法およびフォトリソグラフィ技術によるパターニング技術を使用することにより形成できる。
本実施の形態3では、前記実施の形態1および前記実施の形態2で説明した再配線構造の適用例について説明する。図26は、本実施の形態3における半導体チップCHPの模式的なレイアウト構成を示す図である。図26において、本実施の形態3における半導体チップCHPは、矩形形状をしており、矩形形状をした半導体チップCHPの内部領域に複数のパッドPDが形成されている。そして、図26に示すように、複数のパッドPDの一部と接続するように再配線RDLが形成されている。このような再配線RDLによって、半導体チップCHPの外縁領域でワイヤWと再配線RDLとを接続することができる。つまり、再配線RDLには、ワイヤWとの接続位置を再配置する機能を有し、再配線RDLの再配置機能によって、ワイヤWと再配線RDLとを半導体チップCHPの外縁領域で接続することができる。また、この再配置を内部配線よりも幅の広い再配線RDLで実現することにより、半導体チップCHPのオン抵抗も低減することができる。さらには、再配線RDLのいずれの位置においてもワイヤWと接続することが可能なため、ワイヤWの接続位置のフレキシビリティを実現することができる。このことは、本実施の形態3における再配線RDLを使用することにより、同一の半導体チップCHPを様々なパッケージ形態で実装することができることを意味し、これによって、半導体チップCHPの汎用性を高めることができる。
図27は、本変形例1における半導体チップCHPのレイアウト構成を示す図である。図27において、本変形例1では、パッケージの形態に合わせた再配置を再配線で行なう例が示されている。具体的には、例えば、電源電位が供給されるラインを再配線RDL(VDD)で束ねることによって、電源ラインの強化を図ることができる。同様に、例えば、基準電位(GND電位)が供給されるラインを再配線RDL(GND)で束ねることによって、グランドラインの強化を図ることができる。さらには、図27に示すように、再配線RDL(VDD)および再配線RDL(GND)によって、パッドフリー化が実現されており、ワイヤW1およびワイヤW2の接続自由度が高まる結果、半導体装置のピン数を削減することができる。また、本変形例1によれば、再配線RDL(VDD)に複数のワイヤW1を接続できるため、電源ラインの抵抗低減を図ることができる。同様に、本変形例1によれば、再配線RDL(GND)に複数のワイヤW2を接続できるため、グランドラインの抵抗低減を図ることができる。
図28は、本変形例2における積層半導体チップのレイアウト構成を示す図である。図28に示すように、本変形例2では、再配線構造を形成した半導体チップCHP1〜CHP3を積層配置する例が示されている、具体的に、半導体チップCHP1には、電源電位が供給される再配線RDL(VDD)と、基準電位が供給される再配線RDL(GND)とが配置されている。同様に、半導体チップCHP2にも、電源電位が供給される再配線RDL(VDD)と、基準電位が供給される再配線RDL(GND)とが配置され、半導体チップCHP3にも、電源電位が供給される再配線RDL(VDD)と、基準電位が供給される再配線RDL(GND)とが配置されている。そして、図28に示すように、半導体チップCHP1の再配線RDL(VDD)と半導体チップCHP2の再配線RDL(VDD)がワイヤW1(VDD)で接続され、半導体チップCHP1の再配線RDL(GND)と半導体チップCHP2の再配線RDL(GND)がワイヤW1(GND)で接続されている。同様に、半導体チップCHP2の再配線RDL(VDD)と半導体チップCHP3の再配線RDL(VDD)がワイヤW2(VDD)で接続され、半導体チップCHP2の再配線RDL(GND)と半導体チップCHP3の再配線RDL(GND)がワイヤW2(GND)で接続されている。また、半導体チップCHP3の再配線RDL(VDD)とワイヤW3(VDD)が接続され、半導体チップCHP3の再配線RDL(GND)とワイヤW3(GND)が接続されている。
PI ポリイミド樹脂膜
RDL 再配線
WD 再配線溝
Claims (10)
- 半導体基板、
前記半導体基板の上方に形成されたパッド、
前記パッドを覆う表面保護膜、
前記表面保護膜に形成され、前記パッドの表面の一部を露出する第1開口部、
前記表面保護膜上に形成された保護絶縁膜、
前記保護絶縁膜に形成され、前記第1開口部と連通する配線溝、
前記第1開口部と前記配線溝とに埋め込まれ、前記パッドと電気的に接続された配線、
を備え、
前記配線溝と前記配線との間に、前記配線を構成する配線材料の前記保護絶縁膜中へのマイグレーションを抑制するバリア膜が形成され、
前記バリア膜と前記配線との間に、前記配線材料とは異なる材料から構成され、かつ、前記配線の密着性を向上するための密着膜が形成され、
前記配線は、銀を主成分とする配線材料から形成され、
前記配線の表面には、ボンディングワイヤが接続され、
前記ボンディングワイヤは、銅を主成分とする材料から形成され、
前記配線と前記ボンディングワイヤとは直接接触している、半導体装置。 - 請求項1に記載の半導体装置において、
前記保護絶縁膜には、
前記第1開口部と連通する第2開口部、
前記第2開口部と一体的に形成された前記配線溝、
が形成されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記配線溝の側面は、テーパ状に傾斜している、半導体装置。 - 請求項1に記載の半導体装置において、
前記配線の表面は、前記保護絶縁膜の表面よりも低くなっている、半導体装置。 - 請求項1に記載の半導体装置において、
前記配線の表面は、露出している、半導体装置。 - 請求項1に記載の半導体装置において、
前記保護絶縁膜は、ポリイミド樹脂膜から形成されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記保護絶縁膜には、前記配線溝の底面から延在する界面は存在しない、半導体装置。 - (a)パッドと、前記パッドを覆い、かつ、前記パッドの表面の一部を露出する第1開口部が形成された表面保護膜とが形成された半導体基板を用意する工程、
(b)前記第1開口部内を含む前記表面保護膜上に保護絶縁膜を形成する工程、
(c)第1凸部と第2凸部とが形成された型を前記保護絶縁膜に押し付けることにより、前記保護絶縁膜に、前記第1凸部に対応した第2開口部であって、前記第1開口部と連通した前記第2開口部と、前記第2凸部に対応した配線溝であって、前記第2開口部と連通した前記配線溝とを一体的に形成する工程、
(d)前記配線溝の内部に、銀を主成分とする配線材料からなる配線を形成する工程、
(e)前記(d)工程の後、前記配線と、銅を主成分とする材料からなるボンディングワイヤとを直接接触する工程、
を備え、
前記(c)工程と前記(d)工程との間に、
(f1)前記第1開口部から露出する前記パッドの表面と、前記第1開口部の側面と、前記第2開口部の内壁と、前記保護絶縁膜上とにわたって、前記配線を構成する配線材料の前記保護絶縁膜中へのマイグレーションを抑制するバリア膜を形成する工程、
(f2)前記バリア膜上に、前記配線材料とは異なる材料から構成され、かつ、前記配線の密着性を向上するための密着膜を形成する工程、
を有する、半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記(d)工程は、
(d1)前記配線溝の内部に前記配線の配線材料を印刷する工程、
(d2)前記配線材料に対して加熱処理を施す工程、
を有する、半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記(c)工程と前記(f1)工程との間に、
(g)前記型を前記保護絶縁膜から離型する工程、
(h)前記(g)工程後、前記保護絶縁膜に対して、加熱処理を施す工程、
を有する、半導体装置の製造方法。
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