JP7074463B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- JP7074463B2 JP7074463B2 JP2017229040A JP2017229040A JP7074463B2 JP 7074463 B2 JP7074463 B2 JP 7074463B2 JP 2017229040 A JP2017229040 A JP 2017229040A JP 2017229040 A JP2017229040 A JP 2017229040A JP 7074463 B2 JP7074463 B2 JP 7074463B2
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Description
10 半導体基板
11 層間絶縁膜
12 下層配線
13 電極パッド
14 パッシベーション膜
15 下層絶縁層
16 再配線
17 密着層
18 導電層
19 シールド
20 シールド部
21 配線部
22 導電部材
22a 第1の導電部材
22b 第2の導電部材
23 上層絶縁層
24 バリアメタル部
24a Ti層
24b Cu層
24c Ni層
25 外部接続端子
31 下層絶縁膜
32 UBM膜
32a Ti層
32b Cu層
33 レジストマスク
34 レジストマスク
35 上層絶縁膜
36 UBM膜
36a Ti層
36b Cu層
37 レジストマスク
40 密着層
41 導電部材
42 レジスト膜
OP,AP 開口部
Claims (10)
- 内部配線が形成された半導体基板の1の面上に形成された下層絶縁層と、
前記下層絶縁層の上面に接して形成された密着層と、
前記密着層の上面の互いに離間した複数の領域に夫々形成され、前記内部配線に接続され、前記下層絶縁層から露出した複数の内部電極の各々に夫々接続され且つ外部に露出した複数の外部電極の各々に夫々接続される複数の配線層と、
前記密着層の上面に前記複数の配線層とは離間して形成され、前記複数の内部電極のうちの1つに接続される第1の領域と、前記複数の外部電極のうちの1つに接続される第2の領域と、前記第1の領域と前記第2の領域とを接続し且つ前記密着層の上面の前記複数の配線層の間の領域を覆うように形成された第3の領域と、を有する導電部と、
を備え、
前記導電部の前記第1の領域及び前記第2の領域は第1の膜厚を有し、
前記導電部の前記第3の領域は、前記第1の膜厚より薄い第2の膜厚を有することを特徴とする半導体装置。 - 前記下層絶縁層は前記上面に対向する下面を電極の表面に接して形成され、前記電極の前記表面の一部を露出すると共に上面側の外周と前記下層絶縁層の前記下面側の内周と前記外周と前記内周とを接続するテーパ形状の側壁とからなる第1開口部を備え、
前記密着層は、前記下層絶縁層の前記上面上と、前記第1開口部の側壁上と、前記第1
開口部が露出する前記電極の表面と、に延在し、
前記導電部の前記第1の領域は前記第1開口部を介して前記電極に接続され、平面視における前記第1の領域の前記下層絶縁層の上面に対応する領域は前記第1開口部の前記外周を内包する、
ことを特徴とする請求項1に記載の半導体装置。 - 前記導電部材上に形成され、前記第2の領域の表面の一部を露出する第2開口部を有する上層絶縁層と、
前記上層絶縁層の表面上に形成されると共に前記第2開口部を介して前記導電部の前記2の領域に接続される外部接続端子と、
を備えることを特徴とする請求項1又は2に記載の半導体装置。 - 平面視において、前記外部接続端子の前記上層絶縁層の表面に対応する領域は、前記導電部の前記2の領域の前記上層絶縁層の表面に対応する領域を内包することを特徴とする請求項3に記載の半導体装置。
- 前記導電部の前記第1の領域は、前記下層絶縁層の開口部を介して前記内部電極と接続され、
前記導電部の前記第2の領域は、外部接続端子に接続される、
ことを特徴とする請求項1に記載の半導体装置。 - 前記外部接続端子は、バリアメタル部を介して前記導電部の前記第2の領域と接続されることを特徴とする請求項3乃至5のいずれか1項に記載の半導体装置。
- 前記配線層は、前記第1の膜厚を有し、
前記導電部の前記第3の領域は、前記下層絶縁層の上面上に延在すると共に前記配線層の少なくとも2辺と所定の距離を離間して近接する、
ことを特徴とする請求項3乃至6のいずれか1項に記載の半導体装置。 - 前記導電部の前記第3の領域は、前記配線層と所定の距離を離間して前記配線層を囲むことを特徴とする請求項7に記載の半導体装置。
- 前記導電部は、前記外部接続端子を介して固定電位に接続されることを特徴とする請求項3乃至8のいずれか1項に記載の半導体装置。
- 前記導電部の前記第1の領域及び前記第2の領域はメッキにより形成され、前記導電部の前記第3の領域はスパッタにより形成されることを特徴とする請求項1乃至9のいずれか1項に記載の半導体装置。
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US16/202,187 US11004813B2 (en) | 2017-11-29 | 2018-11-28 | Semiconductor device and manufacturing method of semiconductor device |
CN201811443056.9A CN109841586A (zh) | 2017-11-29 | 2018-11-29 | 半导体装置和半导体装置的制造方法 |
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JP2001156209A (ja) | 1999-11-29 | 2001-06-08 | Casio Comput Co Ltd | 半導体装置 |
JP2002313930A (ja) | 2001-04-11 | 2002-10-25 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2016048742A (ja) | 2014-08-28 | 2016-04-07 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
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US9368398B2 (en) * | 2012-01-12 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method of fabricating same |
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