JP6395299B2 - Silicon carbide semiconductor element and method for manufacturing silicon carbide semiconductor element - Google Patents

Silicon carbide semiconductor element and method for manufacturing silicon carbide semiconductor element Download PDF

Info

Publication number
JP6395299B2
JP6395299B2 JP2014185714A JP2014185714A JP6395299B2 JP 6395299 B2 JP6395299 B2 JP 6395299B2 JP 2014185714 A JP2014185714 A JP 2014185714A JP 2014185714 A JP2014185714 A JP 2014185714A JP 6395299 B2 JP6395299 B2 JP 6395299B2
Authority
JP
Japan
Prior art keywords
silicon carbide
carbide semiconductor
region
film
nickel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014185714A
Other languages
Japanese (ja)
Other versions
JP2016058657A (en
Inventor
内海　誠
誠 内海
善行 酒井
善行 酒井
福田　憲司
憲司 福田
原田　信介
信介 原田
岡本　光央
光央 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Fuji Electric Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, National Institute of Advanced Industrial Science and Technology AIST filed Critical Fuji Electric Co Ltd
Priority to JP2014185714A priority Critical patent/JP6395299B2/en
Publication of JP2016058657A publication Critical patent/JP2016058657A/en
Application granted granted Critical
Publication of JP6395299B2 publication Critical patent/JP6395299B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0485—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes

Description

この発明は、炭化珪素半導体素子及び炭化珪素半導体素子の製造方法に関する。   The present invention relates to a silicon carbide semiconductor element and a method for manufacturing a silicon carbide semiconductor element.

炭化珪素半導体素子は、次世代の低損失な電力用半導体素子として期待されており、ショットキーバリアダイオード、ＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ−Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ、絶縁ゲート型電界効果トランジスタ）、ＰＮダイオード、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ、絶縁ゲート型バイポーラトランジスタ）、ＧＴＯ（Ｇａｔｅ Ｔｕｒｎ−Ｏｆｆ ｔｈｙｒｉｓｔｏｒ、ゲートターンオフサイリスタ）などが開発されている。従来、炭化珪素半導体素子では、オーミック電極の材料として炭化珪素（ＳｉＣ）とニッケルとを反応させたニッケルシリサイド（ＮｉＳｉ）が用いられることがある（例えば、特許文献１、２参照）。   Silicon carbide semiconductor elements are expected as next-generation low-loss power semiconductor elements, including Schottky barrier diodes, MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), PN diodes, IGBTs (insulated gate field effect transistors). Insulated Gate Bipolar Transistors (insulated gate bipolar transistors), GTO (Gate Turn-Off thyristors), and the like have been developed. Conventionally, in a silicon carbide semiconductor element, nickel silicide (NiSi) obtained by reacting silicon carbide (SiC) and nickel may be used as a material for the ohmic electrode (see, for example, Patent Documents 1 and 2).

特開２０１２−１８６３２４号公報JP 2012-186324 A 特開２０１３−５８６０３号公報JP2013-58603A

しかしながら、ニッケルシリサイドを形成する際に、炭化珪素半導体中で炭素が分離し、その分離した炭素がニッケルシリサイド中に凝集することがあり、それによってオーミック電極が、ニッケルシリサイドと炭素とが混合した状態になってしまうことがある。オーミック電極がそのような混合状態になると、剥離の起点となる部位がオーミック電極の内部に発生することがあるため、オーミック電極の機械的強度が低くなるおそれがある。従って、長期にわたる駆動信頼性が得られないという問題点がある。   However, when nickel silicide is formed, carbon is separated in the silicon carbide semiconductor, and the separated carbon may be aggregated in nickel silicide, so that the ohmic electrode is a state in which nickel silicide and carbon are mixed. It may become. When the ohmic electrode is in such a mixed state, a site that is a starting point of peeling may be generated inside the ohmic electrode, which may reduce the mechanical strength of the ohmic electrode. Therefore, there is a problem that long-term drive reliability cannot be obtained.

この発明は、上述した従来技術による問題点を解消するため、長期にわたる駆動信頼性を有する炭化珪素半導体素子を提供することを目的とする。この発明は、長期にわたる駆動信頼性を有する炭化珪素半導体素子を製造することができる炭化珪素半導体素子の製造方法を提供することを目的とする。   An object of the present invention is to provide a silicon carbide semiconductor device having long-term driving reliability in order to solve the above-described problems caused by the conventional technology. An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device capable of manufacturing a silicon carbide semiconductor device having long-term driving reliability.

上述した課題を解決し、目的を達成するため、この発明にかかる炭化珪素半導体素子は、炭化珪素半導体の表面にニッケルシリサイド膜でできた電極を有し、前記ニッケルシリサイド膜の表面凹凸が２０ｎｍ以上１５０ｎｍ以下の高低差を有し、前記炭化珪素半導体と前記ニッケルシリサイド膜との境界線が不連続な点を有することを特徴とする。 In order to solve the above-described problems and achieve the object, a silicon carbide semiconductor device according to the present invention has an electrode made of a nickel silicide film on the surface of a silicon carbide semiconductor, and the surface roughness of the nickel silicide film is 20 nm or more. It has a height difference of 150 nm or less , and a boundary line between the silicon carbide semiconductor and the nickel silicide film has a discontinuous point.

また、前記電極には、ニッケルシリサイドと、前記ニッケルシリサイドよりも炭素濃度の高い部位とが混在していることを特徴とする。   Further, the electrode is characterized in that nickel silicide and a portion having a higher carbon concentration than the nickel silicide are mixed.

また、この発明にかかる炭化珪素半導体素子の製造方法は、炭化珪素半導体の表面に酸化膜を形成後、前記炭化珪素半導体を０．５ｗｔ％の希弗酸液に３０秒以下の時間浸漬し、前記酸化膜の一部を除去する第１の工程と、表面の高低差が１０ｎｍ未満の前記炭化珪素半導体の表面にニッケル膜を設ける第２の工程と、前記炭化珪素半導体と前記ニッケル膜との界面に酸素が存在する状態でアニール処理を行って、前記炭化珪素半導体の表面にシリサイドを設ける第３の工程と、を含むことを特徴とする。 In the method for manufacturing a silicon carbide semiconductor device according to the present invention, after forming an oxide film on the surface of the silicon carbide semiconductor, the silicon carbide semiconductor is immersed in a 0.5 wt% dilute hydrofluoric acid solution for 30 seconds or less. A first step of removing a part of the oxide film, a second step of providing a nickel film on the surface of the silicon carbide semiconductor having a surface height difference of less than 10 nm, the silicon carbide semiconductor and the nickel film, And a third step of performing an annealing process in the presence of oxygen at the interface of the silicon carbide to provide silicide on the surface of the silicon carbide semiconductor.

また、前記炭化珪素半導体と前記ニッケル膜との界面に存在する酸素が、プロセス中に生じる酸化膜であることを特徴とする。   The oxygen present at the interface between the silicon carbide semiconductor and the nickel film is an oxide film generated during the process.

この発明によれば、電極が不連続な島状となり、電極と炭化珪素半導体との境界線が途切れ途切れになることによって、剥離の起点となる部位が電極内部に発生するのが抑制されるため、電極の機械的強度が高まる。また、ニッケルシリサイドよりも炭素濃度の高い部位が不連続な状態になるため、炭素濃度の高い部位が連続した層状になる場合よりも、炭化珪素半導体に対する電極の接触抵抗率が小さくなる。また、炭化珪素半導体の表面の酸化膜を全て除去した場合よりも、炭化珪素半導体に対する電極の接触抵抗率が小さくなる。また、炭化珪素半導体とニッケル膜との界面に酸素を設ける処理を行わずに済むため、工程数の増加を抑えることができる。   According to the present invention, the electrode becomes a discontinuous island shape, and the boundary line between the electrode and the silicon carbide semiconductor is interrupted, thereby suppressing the occurrence of the site that is the starting point of peeling inside the electrode. The mechanical strength of the electrode is increased. In addition, since the portion having a higher carbon concentration than nickel silicide is in a discontinuous state, the contact resistivity of the electrode with respect to the silicon carbide semiconductor is smaller than when the portion having a higher carbon concentration is in a continuous layered form. In addition, the contact resistivity of the electrode with respect to the silicon carbide semiconductor is smaller than when all the oxide film on the surface of the silicon carbide semiconductor is removed. In addition, since it is not necessary to perform a process of providing oxygen at the interface between the silicon carbide semiconductor and the nickel film, an increase in the number of steps can be suppressed.

本発明にかかる炭化珪素半導体素子によれば、長期にわたる駆動信頼性が得られる。本発明にかかる炭化珪素半導体素子の製造方法によれば、長期にわたる駆動信頼性を有する炭化珪素半導体素子を製造することができる。   According to the silicon carbide semiconductor device of the present invention, long-term driving reliability can be obtained. According to the method for manufacturing a silicon carbide semiconductor device according to the present invention, a silicon carbide semiconductor device having long-term driving reliability can be manufactured.

図１は、本発明の実施の形態にかかる炭化珪素半導体素子の一例を示す断面図である。FIG. 1 is a cross-sectional view showing an example of a silicon carbide semiconductor element according to an embodiment of the present invention. 図２は、本発明の実施の形態にかかる炭化珪素半導体素子のオーミック電極／炭化珪素半導体界面の様子を示す模式図を示す図である。FIG. 2 is a schematic diagram showing a state of the ohmic electrode / silicon carbide semiconductor interface of the silicon carbide semiconductor device according to the embodiment of the present invention. 図３は、本発明の実施の形態にかかる炭化珪素半導体素子のオーミック電極／炭化珪素半導体界面の様子を示す模式図を示す図である。FIG. 3 is a schematic diagram showing a state of the ohmic electrode / silicon carbide semiconductor interface of the silicon carbide semiconductor device according to the embodiment of the present invention. 図４は、本発明の実施の形態にかかる炭化珪素半導体素子のオーミック電極／炭化珪素半導体界面の様子を示す模式図を示す図である。FIG. 4 is a schematic diagram showing a state of the ohmic electrode / silicon carbide semiconductor interface of the silicon carbide semiconductor device according to the embodiment of the present invention. 図５は、本発明の実施の形態にかかる炭化珪素半導体素子の特性を示す図表である。FIG. 5 is a chart showing characteristics of the silicon carbide semiconductor device according to the embodiment of the present invention. 図６は、本発明の実施の形態にかかる炭化珪素半導体素子の製造方法の一例を示す工程図である。FIG. 6 is a process diagram showing an example of a method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present invention. 図７は、本発明の実施の形態にかかる炭化珪素半導体素子の製造方法の別の例を示す工程図である。FIG. 7 is a process diagram showing another example of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present invention.

以下に添付図面を参照して、この発明にかかる炭化珪素半導体素子及び炭化珪素半導体素子の製造方法の好適な実施の形態を詳細に説明する。本明細書及び添付図面においては、ｎまたはｐを冠記した層や領域では、それぞれ電子または正孔が多数キャリアであることを意味する。また、ｎやｐに付す＋及び−は、それぞれそれが付されていない層や領域よりも高不純物濃度及び低不純物濃度であることを意味する。なお、以下の実施の形態の説明及び添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。   Exemplary embodiments of a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached thereto. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

以下の説明では、実施の形態にかかる炭化珪素半導体素子の一例として、ｐ型のウェル領域とｎ型のソース領域とをそれぞれイオン注入で形成する二重注入（Ｄｏｕｂｌｅ Ｉｍｐｌａｎｔｅｄ）プロセスによって製造される二重注入型ＭＯＳＦＥＴ（ＤＩＭＯＳＦＥＴ）を挙げる。なお、本発明にかかる炭化珪素半導体素子は、二重注入型ＭＯＳＦＥＴに限らない。   In the following description, as an example of the silicon carbide semiconductor device according to the embodiment, a two-implanted process in which a p-type well region and an n-type source region are respectively formed by ion implantation is used. A double injection type MOSFET (DIMOSFET) is mentioned. In addition, the silicon carbide semiconductor element concerning this invention is not restricted to double injection type MOSFET.

・炭化珪素半導体素子の一例
図１は、本発明の実施の形態にかかる炭化珪素半導体素子の一例を示す断面図である。図１に示すように、炭化珪素半導体素子は、ｎ-炭化珪素基板１を用いて作製されている。ｎ-炭化珪素基板１は、炭化珪素の四層周期六方晶（４Ｈ−ＳｉＣ）からなるｎ-炭化珪素単結晶半導体基板のおもて面側に、例えばｎ-炭化珪素エピタキシャル層を有していてもよい。 FIG. 1 is a cross-sectional view showing an example of a silicon carbide semiconductor element according to an embodiment of the present invention. As shown in FIG. 1, the silicon carbide semiconductor element is manufactured using n − silicon carbide substrate 1. n - silicon carbide substrate 1 is composed of four layers periodic hexagonal silicon carbide (4H-SiC) n - on the front surface side of the silicon carbide single crystal semiconductor substrate, for example, n - have a silicon carbide epitaxial layer May be.

炭化珪素半導体素子は、ｎ-炭化珪素基板１のおもて面側にｐウェル領域２、ｐコンタクト領域３、ｎソース領域４、ゲート絶縁膜５、ゲート電極６、層間絶縁膜７、オーミックコンタクト電極部８及び取出し電極９を有する。炭化珪素半導体素子は、ｎ-炭化珪素基板１の裏面に、ドレイン電極１０となる裏面電極を有する。 The silicon carbide semiconductor element includes a p well region 2, a p contact region 3, an n source region 4, a gate insulating film 5, a gate electrode 6, an interlayer insulating film 7, an ohmic contact on the front surface side of the n − silicon carbide substrate 1. It has an electrode part 8 and an extraction electrode 9. The silicon carbide semiconductor element has a back electrode serving as drain electrode 10 on the back surface of n − silicon carbide substrate 1.

ｐウェル領域２は、ｎ-炭化珪素基板１の表面領域に選択的に設けられている。ｐウェル領域２は、例えばアルミニウムイオンなどのｐ型不純物のイオン注入及び活性加熱処理によって形成されていてもよい。 P well region 2 is selectively provided in the surface region of n − silicon carbide substrate 1. The p well region 2 may be formed by ion implantation of p-type impurities such as aluminum ions and active heat treatment.

ｐコンタクト領域３は、ｐウェル領域２の表面領域に選択的に設けられている。ｐコンタクト領域３は、例えばアルミニウムイオンなどのｐ型不純物のイオン注入及び活性加熱処理によって形成されていてもよい。   The p contact region 3 is selectively provided in the surface region of the p well region 2. The p contact region 3 may be formed by ion implantation of p-type impurities such as aluminum ions and active heat treatment.

ｎソース領域４は、ｐウェル領域２の表面領域に選択的に設けられている。ｎソース領域４は、例えば燐イオンや窒素イオンなどのｎ型不純物のイオン注入及び活性加熱処理によって形成されていてもよい。   The n source region 4 is selectively provided in the surface region of the p well region 2. The n source region 4 may be formed by ion implantation of n-type impurities such as phosphorus ions and nitrogen ions and active heat treatment.

ゲート絶縁膜５は、隣り合うｎソース領域４とｎソース領域４との間のｐウェル領域２の表面上に設けられている。ゲート絶縁膜５は、隣り合うｎソース領域４とｎソース領域４との間の領域において、一方のｐウェル領域２の表面上からｎ-炭化珪素基板１の表面上を経由してもう一方のｐウェル領域２の表面上まで設けられていてもよい。ゲート絶縁膜５は、例えば酸化珪素膜でできていてもよい。ゲート絶縁膜５は、例えば熱酸化及びパターニングによって形成されていてもよい。 Gate insulating film 5 is provided on the surface of p well region 2 between adjacent n source regions 4 and n source regions 4. Gate insulating film 5 is formed in the region between adjacent n source region 4 and n source region 4 from the surface of one p well region 2 to the other via the surface of n − silicon carbide substrate 1. It may be provided up to the surface of p well region 2. The gate insulating film 5 may be made of, for example, a silicon oxide film. The gate insulating film 5 may be formed by, for example, thermal oxidation and patterning.

ゲート電極６は、ゲート絶縁膜５の表面上に設けられている。ゲート電極６は、隣り合うｎソース領域４とｎソース領域４との間の領域において、一方のｐウェル領域２の上からｎ-炭化珪素基板１の上を経由してもう一方のｐウェル領域２の上まで設けられていてもよい。ゲート電極６は、例えばポリシリコン膜でできていてもよい。ゲート電極６のポリシリコン膜は、例えばＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ、化学気相成長）法及びパターニングによって形成されていてもよい。 The gate electrode 6 is provided on the surface of the gate insulating film 5. Gate electrode 6 is located in the region between adjacent n source regions 4 and n source regions 4 from the top of one p well region 2 through the top of n − silicon carbide substrate 1 to the other p well region. Up to 2 may be provided. The gate electrode 6 may be made of, for example, a polysilicon film. The polysilicon film of the gate electrode 6 may be formed by, for example, a CVD (Chemical Vapor Deposition) method and patterning.

層間絶縁膜７は、ゲート電極６を覆うように設けられている。層間絶縁膜７は、例えば酸化珪素膜でできていてもよい。層間絶縁膜７の酸化珪素膜は、例えばＣＶＤ法及びパターニングによって形成されていてもよい。   The interlayer insulating film 7 is provided so as to cover the gate electrode 6. The interlayer insulating film 7 may be made of, for example, a silicon oxide film. The silicon oxide film of the interlayer insulating film 7 may be formed by, for example, a CVD method and patterning.

オーミックコンタクト電極部８は、ｐコンタクト領域３及びｎソース領域４に接して設けられている。オーミックコンタクト電極部８は、ｐコンタクト領域３及びｎソース領域４に電気的に接続する。オーミックコンタクト電極部８は、ニッケルシリサイド膜でできていてもよい。オーミックコンタクト電極部８のニッケルシリサイド膜の表面凹凸は、２０ｎｍ以上の高低差を有する。ｐコンタクト領域３やｎソース領域４などの炭化珪素半導体とニッケルシリサイド膜との境界線は、不連続な点を有していてもよい。オーミックコンタクト電極部８には、ニッケルシリサイドと、ニッケルシリサイドよりも炭素濃度の高い部位とが混在していてもよい。   The ohmic contact electrode portion 8 is provided in contact with the p contact region 3 and the n source region 4. The ohmic contact electrode portion 8 is electrically connected to the p contact region 3 and the n source region 4. The ohmic contact electrode portion 8 may be made of a nickel silicide film. The surface unevenness of the nickel silicide film of the ohmic contact electrode portion 8 has a height difference of 20 nm or more. The boundary line between the silicon carbide semiconductor such as the p contact region 3 and the n source region 4 and the nickel silicide film may have discontinuous points. In the ohmic contact electrode portion 8, nickel silicide and a portion having a higher carbon concentration than nickel silicide may be mixed.

取出し電極９は、オーミックコンタクト電極部８を覆うように設けられている。取出し電極９は、例えばアルミニウム（Ａｌ）でできていてもよい。取出し電極９の厚さは、例えば５μｍ程度であってもよい。取出し電極９は、ゲート電極６上にもｎソース領域４と分離して形成される。それによって、ソースとゲートとが独立して駆動される。   The extraction electrode 9 is provided so as to cover the ohmic contact electrode portion 8. The extraction electrode 9 may be made of, for example, aluminum (Al). The thickness of the extraction electrode 9 may be about 5 μm, for example. The extraction electrode 9 is also formed on the gate electrode 6 separately from the n source region 4. Thereby, the source and the gate are driven independently.

ドレイン電極１０は、ｎ-炭化珪素基板１の裏面に、ｎ-炭化珪素基板１に接して設けられている。ドレイン電極１０は、チタン（Ｔｉ）とニッケルの積層膜でできていてもよい。 The drain electrode 10, n - on the back surface of the silicon carbide substrate 1, n - is provided in contact with the silicon carbide substrate 1. The drain electrode 10 may be made of a laminated film of titanium (Ti) and nickel.

・図１に示す炭化珪素半導体素子の製造手順の一例
まず、ｎ-炭化珪素基板１を用意する。ｎ-炭化珪素基板１は、例えば炭化珪素の四層周期六方晶（４Ｈ−ＳｉＣ）からなるｎ-炭化珪素単結晶半導体基板のおもて面にｎ-炭化珪素エピタキシャル層が積層されたものである。 Example of Manufacturing Procedure for Silicon Carbide Semiconductor Element Shown in FIG. 1 First, an n − silicon carbide substrate 1 is prepared. n - silicon carbide substrate 1 is made of, for example, four-layer periodic hexagonal silicon carbide (4H-SiC) n - in which the silicon carbide epitaxial layer is stacked - n on the front surface of the silicon carbide single crystal semiconductor substrate is there.

次いで、ｎ-炭化珪素基板１のおもて面に、ｐウェル領域２に対応する開口部を有する酸化珪素膜等のイオン注入用マスクを形成する。そして、ｎ-炭化珪素基板１をイオン注入装置に導入し、アルミニウムイオンなどのｐ型不純物をイオン注入して、ｎ-炭化珪素基板１の表面領域、すなわちｎ-炭化珪素エピタキシャル層の表面領域に、ｐウェル領域２となるｐ型のイオン注入領域を設ける。 Next, an ion implantation mask such as a silicon oxide film having an opening corresponding to p well region 2 is formed on the front surface of n − silicon carbide substrate 1. Then, n − silicon carbide substrate 1 is introduced into an ion implantation apparatus, and p-type impurities such as aluminum ions are ion-implanted to form a surface region of n − silicon carbide substrate 1, that is, a surface region of an n − silicon carbide epitaxial layer. A p-type ion implantation region to be the p well region 2 is provided.

次いで、イオン注入用マスクを取り除いた後に、ｐウェル領域２となるｐ型のイオン注入領域の表面に、ｐコンタクト領域３に対応する開口部を有する酸化珪素膜等のイオン注入用マスクを形成する。そして、ｎ-炭化珪素基板１をイオン注入装置に導入し、アルミニウムイオンなどのｐ型不純物をイオン注入して、ｐウェル領域２となるｐ型のイオン注入領域の表面領域に、ｐコンタクト領域３となるｐ型のイオン注入領域を設ける。 Next, after removing the ion implantation mask, an ion implantation mask such as a silicon oxide film having an opening corresponding to the p contact region 3 is formed on the surface of the p-type ion implantation region to be the p well region 2. . Then, the n − silicon carbide substrate 1 is introduced into an ion implantation apparatus, and a p-type impurity such as aluminum ion is ion-implanted. A p-type ion implantation region is provided.

次いで、イオン注入用マスクを取り除いた後に、ｐウェル領域２となるｐ型のイオン注入領域の表面に、ｎソース領域４に対応する開口部を有する酸化珪素膜等のイオン注入用マスクを形成する。そして、ｎ-炭化珪素基板１をイオン注入装置に導入し、燐イオンや窒素イオンなどのｎ型不純物をイオン注入して、ｐウェル領域２となるｐ型のイオン注入領域の表面領域に、ｎソース領域４となるｎ型のイオン注入領域を設ける。 Next, after removing the ion implantation mask, an ion implantation mask such as a silicon oxide film having an opening corresponding to the n source region 4 is formed on the surface of the p-type ion implantation region to be the p well region 2. . Then, the n − silicon carbide substrate 1 is introduced into an ion implantation apparatus, and n-type impurities such as phosphorus ions and nitrogen ions are ion-implanted. An n-type ion implantation region to be the source region 4 is provided.

ｐコンタクト領域３となるｐ型のイオン注入領域、及びｎソース領域４となるｎ型のイオン注入領域を設けるためのイオン注入の順序は、上述した順序に限らず、種々、入れ替え可能である。   The order of ion implantation for providing the p-type ion implantation region to be the p-contact region 3 and the n-type ion implantation region to be the n-source region 4 is not limited to the order described above, and can be variously changed.

次いで、イオン注入用マスクを取り除いた後に、ｎ-炭化珪素基板１のおもて面に、耐圧リング構造部を設けるためのイオン注入用マスクを形成する。そして、イオン注入によって、ｐウェル領域２が集中して設けられる活性領域を取り囲むように、耐圧リング構造部（図１には示されていない）となるｐ型のイオン注入領域を設ける。ｐ型の耐圧リング構造部が設けられた領域までが、１つのＭＯＳＦＥＴ素子などの炭化珪素半導体素子の領域となる。１つのｎ-炭化珪素基板１上には、複数の素子が配列される。 Next, after removing the ion implantation mask, an ion implantation mask for providing a pressure-resistant ring structure is formed on the front surface of the n − silicon carbide substrate 1. Then, by ion implantation, a p-type ion implantation region serving as a pressure-resistant ring structure (not shown in FIG. 1) is provided so as to surround the active region where the p-well region 2 is concentrated. The region up to the region where the p-type breakdown voltage ring structure is provided is a region of a silicon carbide semiconductor element such as one MOSFET element. A plurality of elements are arranged on one n − silicon carbide substrate 1.

次いで、イオン注入用マスクを取り除いた後に、アルゴンなどの不活性雰囲気において１７００℃程度の温度で活性化アニールを行う。それによって、ｐウェル領域２となるｐ型のイオン注入領域がｐウェル領域２となる。ｐコンタクト領域３となるｐ型のイオン注入領域がｐコンタクト領域３となる。ｎソース領域４となるｎ型のイオン注入領域がｎソース領域４となる。耐圧リング構造部となるｐ型のイオン注入領域がｐ型の耐圧リング構造部となる。   Next, after removing the ion implantation mask, activation annealing is performed at a temperature of about 1700 ° C. in an inert atmosphere such as argon. As a result, the p-type ion implantation region that becomes the p-well region 2 becomes the p-well region 2. The p-type ion implantation region that becomes the p-contact region 3 becomes the p-contact region 3. The n-type ion implantation region that becomes the n source region 4 becomes the n source region 4. The p-type ion-implanted region that becomes the breakdown voltage ring structure portion becomes the p-type breakdown voltage ring structure portion.

次いで、熱酸化を行って、ｎ-炭化珪素基板１のおもて面にゲート絶縁膜５を設ける。次いで、ＣＶＤ法によって、ｎ-炭化珪素基板１のおもて面にポリシリコン膜を設け、フォトリソグラフ技術によって、隣り合うｐウェル領域２とｐウェル領域２とに跨る領域にゲート電極６を形成する。ｐ型の耐圧リング構造部上などのように、ゲート絶縁膜５が不要な部分に、予め酸化珪素膜パターンを形成する場合もある。 Next, thermal oxidation is performed to provide a gate insulating film 5 on the front surface of the n − silicon carbide substrate 1. Next, a polysilicon film is provided on the front surface of the n − silicon carbide substrate 1 by CVD, and a gate electrode 6 is formed in a region straddling the adjacent p well region 2 and p well region 2 by photolithography. To do. In some cases, a silicon oxide film pattern is formed in advance on a portion where the gate insulating film 5 is unnecessary, such as on a p-type pressure-resistant ring structure.

次いで、ＣＶＤ法によって酸化珪素膜からなる層間絶縁膜７を形成し、フォトリソグラフ技術によって、ｎソース領域４及びｐコンタクト領域３の上に層間絶縁膜７の開口部を形成する。また、ゲート電極６とゲート電極６の取出し電極９との接合部（図１には示されていない）にも、層間絶縁膜７の開口部を形成する。   Next, an interlayer insulating film 7 made of a silicon oxide film is formed by CVD, and an opening of the interlayer insulating film 7 is formed on the n source region 4 and the p contact region 3 by photolithography. Further, an opening of the interlayer insulating film 7 is also formed at the junction (not shown in FIG. 1) between the gate electrode 6 and the extraction electrode 9 of the gate electrode 6.

次いで、必要に応じて、希弗酸液にｎ-炭化珪素基板１を浸漬し、層間絶縁膜７の開口部に露出するｎ-炭化珪素基板１の表面の酸化膜を除去する。これにより、ｎソース領域４及びｐコンタクト領域３の露出面が清浄な面となる。この処理は、オーミック電極を形成する際の前処理となる。 Next, if necessary, n − silicon carbide substrate 1 is immersed in a dilute hydrofluoric acid solution, and the oxide film on the surface of n − silicon carbide substrate 1 exposed at the opening of interlayer insulating film 7 is removed. As a result, the exposed surfaces of the n source region 4 and the p contact region 3 become clean surfaces. This treatment is a pretreatment when forming an ohmic electrode.

層間絶縁膜７に開口部を形成した後に大気に触れさせる段階や、レジストを除去するために行うアッシング工程で、炭化珪素基板１の露出面に酸化膜が生成される。また、層間絶縁膜７の残渣によっても、炭化珪素基板１の露出面に酸化膜が生成される。断面観察により測定した結果、層間絶縁膜７の開口部に生成された酸化膜の平均膜厚は約４．５ｎｍであった。また、この酸化膜の高低差、すなわちｎ-炭化珪素基板１の、オーミックコンタクト電極部８と接触する部位の表面の高低差は４．５ｎｍよりも小さかった。したがって、プロセス幅や測定位置の分布を考え、ｎ-炭化珪素基板１の、オーミックコンタクト電極部８と接触する部位の表面の最大の高低差は、１０ｎｍ未満になると考えられる。 An oxide film is formed on the exposed surface of the silicon carbide substrate 1 in the step of exposing to the atmosphere after the opening is formed in the interlayer insulating film 7 or the ashing process performed for removing the resist. An oxide film is also generated on the exposed surface of silicon carbide substrate 1 due to the residue of interlayer insulating film 7. As a result of measurement by cross-sectional observation, the average film thickness of the oxide film formed in the opening of the interlayer insulating film 7 was about 4.5 nm. Further, the difference in height of the oxide film, that is, the difference in height of the surface of the n − silicon carbide substrate 1 at the portion in contact with the ohmic contact electrode portion 8 was smaller than 4.5 nm. Therefore, in consideration of the process width and the distribution of measurement positions, it is considered that the maximum height difference of the surface of the n − silicon carbide substrate 1 in contact with the ohmic contact electrode portion 8 is less than 10 nm.

次いで、スパッタ法などの成膜技術によって、ｎ-炭化珪素基板１のおもて面に５０ｎｍのニッケル膜を設け、フォトリソグラフ技術によって、ｎソース領域４及びｐコンタクト領域３を被覆する領域にニッケルパターンを形成する。ニッケル膜の厚さは、シリサイドが効率よく形成され、かつパターニングによる寸法制御性の良い厚さであるのが望ましく、例えば２０ｎｍ〜１００ｎｍ程度の厚さであるのが適当である。 Next, a nickel film of 50 nm is provided on the front surface of the n − silicon carbide substrate 1 by a film forming technique such as sputtering, and nickel is applied to the area covering the n source region 4 and the p contact region 3 by a photolithographic technique. Form a pattern. The thickness of the nickel film is preferably such that silicide is efficiently formed and has good dimensional controllability by patterning, for example, about 20 nm to 100 nm.

次いで、ＲＴＡ（Ｒａｐｉｄ Ｔｈｅｒｍａｌ Ａｎｎｅａｌｉｎｇ）法によって、不活性ガス雰囲気または減圧雰囲気において約１０００℃の温度での加熱を実施する。それによって、ｐコンタクト領域３及びｎソース領域４の上のニッケルパターンをニッケルシリサイド化し、オーミックコンタクト電極部８を設ける。   Next, heating is performed at a temperature of about 1000 ° C. in an inert gas atmosphere or a reduced pressure atmosphere by an RTA (Rapid Thermal Annealing) method. Thereby, the nickel pattern on the p contact region 3 and the n source region 4 is converted to nickel silicide, and the ohmic contact electrode portion 8 is provided.

次いでオーミックコンタクト電極部８を被覆するように、またｎソース領域４から分離してゲート電極６の上に、厚さ５μｍのアルミニウムでできた取出し電極９を形成する。そして、ｎ-炭化珪素基板１の裏面にチタンとニッケルの積層膜を設け、ドレイン電極１０とすることによって、図１に示す炭化珪素半導体素子ができあがる。 Next, an extraction electrode 9 made of aluminum having a thickness of 5 μm is formed on the gate electrode 6 so as to cover the ohmic contact electrode portion 8 and separated from the n source region 4. Then, by providing a laminated film of titanium and nickel on the back surface of n − silicon carbide substrate 1 to form drain electrode 10, the silicon carbide semiconductor element shown in FIG. 1 is completed.

・オーミック電極／炭化珪素半導体界面の様子
層間絶縁膜７の開口部に露出するｎ-炭化珪素基板１の表面の酸化膜を除去する際、酸化膜の除去時間、すなわち希弗酸液への浸漬時間によって、ニッケルを用いたオーミック電極の状態が異なる。図２〜図４は、本発明の実施の形態にかかる炭化珪素半導体素子のオーミック電極／炭化珪素半導体界面の様子を示すＳＥＭ（Ｓｃａｎｎｉｎｇ Ｅｌｅｃｔｒｏｎ Ｍｉｃｒｏｓｃｏｐｅ、走査型電子顕微鏡）画像を模式図にしたものである。 -State of the ohmic electrode / silicon carbide semiconductor interface When removing the oxide film on the surface of the n - silicon carbide substrate 1 exposed at the opening of the interlayer insulating film 7, the removal time of the oxide film, that is, immersion in dilute hydrofluoric acid solution The state of the ohmic electrode using nickel varies depending on time. 2 to 4 are schematic diagrams of SEM (Scanning Electron Microscope) images showing the state of the ohmic electrode / silicon carbide semiconductor interface of the silicon carbide semiconductor device according to the embodiment of the present invention. is there.

図２には、層間絶縁膜７の開口部に露出するｎ-炭化珪素基板１の表面の酸化膜を全く除去しなかった場合の断面の様子が示されている。酸化膜を全く除去しなかった場合、図２に示すように、オーミックコンタクト電極部８が不連続な島状に形成されており、オーミックコンタクト電極部８とｎ-炭化珪素基板１との境界線が途切れ途切れで不連続になっている。図２から、オーミックコンタクト電極部８とｎ-炭化珪素基板１との境界線において、オーミックコンタクト電極部８が形成されていない領域があることがわかる。接触抵抗は、約８×１０-3Ωｃｍ2であった。この状態では、ｎソース領域４及びｐコンタクト領域３におけるオーミックコンタクト電極部８の有効面積が小さいため、算出した接触抵抗率が大きくなったと推測される。 FIG. 2 shows the state of the cross section when the oxide film on the surface of n − silicon carbide substrate 1 exposed at the opening of interlayer insulating film 7 is not removed at all. When the oxide film is not removed at all, as shown in FIG. 2, the ohmic contact electrode portion 8 is formed in a discontinuous island shape, and the boundary line between the ohmic contact electrode portion 8 and the n − silicon carbide substrate 1 is formed. Is discontinuous and discontinuous. FIG. 2 shows that there is a region where the ohmic contact electrode portion 8 is not formed at the boundary line between the ohmic contact electrode portion 8 and the n − silicon carbide substrate 1. The contact resistance was about 8 × 10 −3 Ωcm 2 . In this state, since the effective area of the ohmic contact electrode portion 8 in the n source region 4 and the p contact region 3 is small, it is estimated that the calculated contact resistivity has increased.

図３には、層間絶縁膜７の開口部に露出するｎ-炭化珪素基板１の表面の酸化膜を十分に除去した場合の断面の様子が示されている。酸化膜を十分に除去した場合、図３に示すように、オーミックコンタクト電極部８の表面の高低差が２０ｎｍよりも小さく、オーミックコンタクト電極部８とｎ-炭化珪素基板１の境界線が途切れることがなく、なめらかな形状のオーミックコンタクト電極部８が形成される。オーミックコンタクト電極部８は、ニッケルシリサイドの下に、ニッケルシリサイドよりも炭素濃度の高い炭素層を有する積層構造となっている。 FIG. 3 shows the state of the cross section when the oxide film on the surface of n − silicon carbide substrate 1 exposed at the opening of interlayer insulating film 7 is sufficiently removed. When the oxide film is sufficiently removed, as shown in FIG. 3, the height difference of the surface of the ohmic contact electrode portion 8 is smaller than 20 nm, and the boundary line between the ohmic contact electrode portion 8 and the n − silicon carbide substrate 1 is interrupted. Thus, the smooth ohmic contact electrode portion 8 is formed. The ohmic contact electrode portion 8 has a laminated structure having a carbon layer having a carbon concentration higher than that of nickel silicide under the nickel silicide.

図４には、層間絶縁膜７の開口部に露出するｎ-炭化珪素基板１の表面の酸化膜を適当に除去した場合の断面の様子が示されている。酸化膜を適当に除去した場合、図４に示すように、オーミックコンタクト電極部８の表面凹凸が大きく、オーミックコンタクト電極部８とｎ-炭化珪素基板１との境界線の傾きが場所によって大きく変わり、不連続なオーミックコンタクト電極部８が形成される。オーミックコンタクト電極部８の表面凹凸の高低差は、最も高低差のある部位でおよそ１００ｎｍ程度であり、比較的平坦な部分でも２０ｎｍ以上はある。図４から、炭素濃度の高い層が連続した層として形成されず、ニッケルシリサイド中に不連続に形成されることがわかる。 FIG. 4 shows a state of a cross section when the oxide film on the surface of n − silicon carbide substrate 1 exposed at the opening of interlayer insulating film 7 is appropriately removed. When the oxide film is appropriately removed, as shown in FIG. 4, the surface irregularities of the ohmic contact electrode portion 8 are large, and the inclination of the boundary line between the ohmic contact electrode portion 8 and the n − silicon carbide substrate 1 varies greatly depending on the location. A discontinuous ohmic contact electrode portion 8 is formed. The level difference of the surface unevenness of the ohmic contact electrode portion 8 is about 100 nm at a portion having the highest level difference, and is 20 nm or more even in a relatively flat portion. FIG. 4 shows that the layer with a high carbon concentration is not formed as a continuous layer but is formed discontinuously in the nickel silicide.

・特性の評価
図５は、本発明の実施の形態にかかる炭化珪素半導体素子の特性を示す図表である。図５の図表には、室温の０．５ｗｔ％弗酸への浸漬時間（単位：秒）を変化させた場合の、ｎ-炭化珪素基板１の表面の酸化膜の厚さ（単位：ｎｍ）、及びオーミックコンタクト電極部８の表面凹凸の高低差（単位：ｎｍ）の評価結果が示されている。また、図５の図表には、室温の０．５ｗｔ％弗酸への浸漬時間（単位：秒）を変化させた場合の、ｐ型の炭化珪素半導体に対するオーミックコンタクト電極部８の接触抵抗率（単位：１０-3Ωｃｍ2）、及びテープ剥離試験によるオーミックコンタクト電極部８の密着性の評価結果が示されている。 Evaluation of Characteristics FIG. 5 is a chart showing characteristics of the silicon carbide semiconductor element according to the embodiment of the present invention. The chart of FIG. 5 shows the thickness (unit: nm) of the oxide film on the surface of the n − silicon carbide substrate 1 when the immersion time (unit: second) in 0.5 wt% hydrofluoric acid at room temperature is changed. And the evaluation result of the height difference (unit: nm) of the surface unevenness | corrugation of the ohmic contact electrode part 8 is shown. Further, in the chart of FIG. 5, the contact resistivity of the ohmic contact electrode part 8 with respect to the p-type silicon carbide semiconductor when the immersion time (unit: second) in 0.5 wt% hydrofluoric acid at room temperature is changed is shown. The unit: 10 −3 Ωcm 2 ), and the evaluation results of the adhesion of the ohmic contact electrode portion 8 by the tape peeling test are shown.

接触抵抗率の測定については、オーミックコンタクト電極部８上に取出し電極９を形成した後に行い、電極面積を一定として、ＴＬＭ（Ｔｒａｎｓｍｉｓｓｉｏｎ Ｌｉｎｅ Ｍｏｄｅｌ）法により測定した。オーミックコンタクト電極部８の密着性の評価結果については、図５の図表に、剥離の発生しなかった状態を○とし、一部剥離が発生した状態を△とし、剥離の面積が５０％を超えた状態を×として示した。   The contact resistivity was measured after the extraction electrode 9 was formed on the ohmic contact electrode portion 8, and was measured by a TLM (Transmission Line Model) method with a constant electrode area. As for the evaluation results of the adhesiveness of the ohmic contact electrode portion 8, in the chart of FIG. 5, the state where peeling did not occur was indicated as ◯, the state where partial peeling occurred was indicated as △, and the peeling area exceeded 50%. The state was indicated as x.

図５から以下のことがわかる。ｎ-炭化珪素基板１の表面の酸化膜の厚さは、浸漬時間が長くなるに連れて小さくなる。オーミックコンタクト電極部８の表面凹凸の高低差は、浸漬時間が長くなるに連れて小さくなる。接触抵抗率は、浸漬時間が長くなるに連れて小さくなっていき、その後、大きくなっていく。初期の接触抵抗率の低下は、ニッケルシリサイドが島状に形成される状態が徐々に緩和されることによる効果であると考えられる。その後の接触抵抗率の上昇は、シリサイドの下に炭素層２１が層状に形成され、見かけ上、オーミックコンタクト電極部８の内部で炭素層２１が抵抗体になるためと推定される。ｎ-炭化珪素基板１の表面の酸化膜を十分に除去すると、オーミックコンタクト電極部８の剥離面積が大きくなる傾向が得られた。剥離面の断面を観察したところ、炭素層２１を起点にしてオーミックコンタクト電極部８が剥離していることがわかった。つまり、炭素層２１が連続して形成されることによって機械的な強度が低下すると推定される。以上の評価結果から、０．５ｗｔ％弗酸での処理時間の最適範囲を０秒から３０秒とした。この処理時間であれば、オーミックコンタクト電極部８の密着性と接触抵抗率を両立することができる。 The following can be understood from FIG. The thickness of the oxide film on the surface of n − silicon carbide substrate 1 decreases as the immersion time increases. The level difference of the surface unevenness of the ohmic contact electrode portion 8 becomes smaller as the immersion time becomes longer. The contact resistivity decreases with increasing immersion time and then increases. The decrease in the initial contact resistivity is considered to be an effect due to the gradual relaxation of the state where nickel silicide is formed in an island shape. The subsequent increase in contact resistivity is presumed to be because the carbon layer 21 is formed in a layer shape under the silicide, and apparently the carbon layer 21 becomes a resistor inside the ohmic contact electrode portion 8. When the oxide film on the surface of the n − silicon carbide substrate 1 was sufficiently removed, the peeling area of the ohmic contact electrode portion 8 tended to increase. When the cross section of the peeled surface was observed, it was found that the ohmic contact electrode portion 8 was peeled from the carbon layer 21 as a starting point. That is, it is presumed that the mechanical strength is reduced by continuously forming the carbon layer 21. From the above evaluation results, the optimum range of treatment time with 0.5 wt% hydrofluoric acid was set from 0 seconds to 30 seconds. If it is this processing time, the adhesiveness of the ohmic contact electrode part 8 and contact resistivity can be made compatible.

・実施例
上述した炭化珪素半導体素子の製造手順に従い、以下のようにして二重注入型ＭＯＳＦＥＴを作製した。まず、ｎ型不純物のドーピング濃度が２×１０15／ｃｍ3である高抵抗層を１５μｍの厚さでエピタキシャル成長したｎ-炭化珪素基板１を用意した。次いで、厚さ１．５μｍのシリコン酸化膜からなるイオン注入用マスクを形成し、５００℃の温度でアルミニウムイオンを注入することによって、ｐウェル領域２となるイオン注入領域を設けた。ｐウェル領域２を形成するためのドーピング濃度を１×１０16／ｃｍ3とし、注入深さを１μｍとした。 Example According to the above-described manufacturing procedure of the silicon carbide semiconductor element, a double-injection MOSFET was manufactured as follows. First, an n − silicon carbide substrate 1 was prepared by epitaxially growing a high resistance layer having an n-type impurity doping concentration of 2 × 10 15 / cm 3 to a thickness of 15 μm. Next, an ion implantation mask made of a silicon oxide film having a thickness of 1.5 μm was formed, and aluminum ions were implanted at a temperature of 500 ° C., thereby providing an ion implantation region serving as the p well region 2. The doping concentration for forming the p-well region 2 was 1 × 10 16 / cm 3 and the implantation depth was 1 μm.

次いで、ｐウェル領域２となるイオン注入領域の表面に、ｐコンタクト領域３に対応する開口部を有するシリコン酸化膜からなるイオン注入用マスクを形成し、アルミニウムイオンを注入することによって、ｐコンタクト領域３となるイオン注入領域を設けた。ｐコンタクト領域３を形成するためのドーピング濃度を１×１０18／ｃｍ3とした。ｐコンタクト領域３を形成するためのイオン注入と同時に、素子近傍にｐコンタクト領域３のコンタクト抵抗を測定するためのＴＬＭパターン領域を形成した。 Next, an ion implantation mask made of a silicon oxide film having an opening corresponding to the p contact region 3 is formed on the surface of the ion implantation region to be the p well region 2, and aluminum ions are implanted to form the p contact region. 3 was provided. The doping concentration for forming the p contact region 3 was 1 × 10 18 / cm 3 . Simultaneously with the ion implantation for forming the p contact region 3, a TLM pattern region for measuring the contact resistance of the p contact region 3 was formed in the vicinity of the element.

次いで、ｎ-炭化珪素基板１をアニール炉に挿入し、アルゴン雰囲気において１７００℃で５分間の活性化処理を行い、ｐウェル領域２となるイオン注入領域をｐウェル領域２とし、ｐコンタクト領域３となるイオン注入領域をｐコンタクト領域３とした。 Then, n - silicon carbide substrate 1 is inserted into an annealing furnace, subjected to activation treatment for 5 minutes at 1700 ° C. in an argon atmosphere, the ion implantation region to be the p-well region 2 and p-well region 2, p contact region 3 The ion-implanted region which becomes

次いで、ｐウェル領域２となるイオン注入領域の表面に、ｎソース領域４に対応する開口部を有するシリコン酸化膜からなるイオン注入用マスクを形成し、燐イオンを注入することによって、ｎソース領域４となるイオン注入領域を設けた。ｎソース領域４を形成するためのドーピング濃度を１×１０19／ｃｍ3とした。 Next, an ion implantation mask made of a silicon oxide film having an opening corresponding to the n source region 4 is formed on the surface of the ion implantation region to be the p well region 2, and phosphorus ions are implanted to thereby form the n source region. 4 was provided. The doping concentration for forming the n source region 4 was 1 × 10 19 / cm 3 .

次いで、ｎ-炭化珪素基板１を再度アニール炉に挿入し、アルゴン雰囲気において１７００℃で５分間の活性化処理を行い、ｎソース領域４となるイオン注入領域をｎソース領域４とした。 Next, the n − silicon carbide substrate 1 was again inserted into the annealing furnace, and an activation treatment was performed at 1700 ° C. for 5 minutes in an argon atmosphere, so that the ion implantation region to be the n source region 4 was defined as the n source region 4.

次いで、ｎ-炭化珪素基板１を石英管内に挿入し、酸素を純水に通して水蒸気を含ませた雰囲気において１２００℃で熱酸化処理を行い、ｎ-炭化珪素基板１の表面、すなわちエピタキシャル成長させた高抵抗層の表面に、ゲート絶縁膜５となるシリコン酸化膜を成長させた。シリコン酸化膜の厚さを７００Åとした。 Then, n - silicon carbide substrate 1 was inserted into the quartz tube, subjected to thermal oxidation treatment at 1200 ° C. in an atmosphere moistened with water vapor through the oxygen in pure water, n - surface of the silicon carbide substrate 1, i.e. epitaxially grown A silicon oxide film to be the gate insulating film 5 was grown on the surface of the high resistance layer. The thickness of the silicon oxide film was 700 mm.

次いで、ＣＶＤ法によって、燐をドープした厚さ０．５μｍのポリシリコン膜を形成し、フォトリソグラフ技術によってポリシリコン膜をパターニングして、隣り合うｐウェル領域２とｐウェル領域２とに跨る領域にゲート電極６を形成した。   Next, a phosphorous-doped polysilicon film having a thickness of 0.5 μm is formed by a CVD method, and the polysilicon film is patterned by a photolithographic technique, so as to straddle the adjacent p-well region 2 and the p-well region 2. A gate electrode 6 was formed.

次いで、ＣＶＤ法によって、ｎ-炭化珪素基板１の表面に厚さ１μｍのＰＳＧ（Ｐｈｏｓｐｈｏｒｕｓ Ｓｉｌｉｃｏｎ Ｇｌａｓｓ）膜を形成した。そして、フォトリソグラフ技術によってＰＳＧ膜をパターニングして、ゲート電極６を被覆するように層間絶縁膜７を形成した。 Next, a PSG (Phosphorus Silicon Glass) film having a thickness of 1 μm was formed on the surface of the n − silicon carbide substrate 1 by CVD. Then, the PSG film was patterned by a photolithographic technique to form an interlayer insulating film 7 so as to cover the gate electrode 6.

次いで、室温の０．５ｗｔ％弗酸にｎ-炭化珪素基板１を浸漬し、オーミックコンタクト電極部８を設ける面の酸化膜を除去した。浸漬時間０秒の試料、浸漬時間１５秒の試料及び浸漬時間３０秒の試料を用意した。浸漬時間０秒の試料は、弗酸にｎ-炭化珪素基板１を浸漬していない、すなわち酸化膜を除去していない試料である。 Next, the n − silicon carbide substrate 1 was immersed in 0.5 wt% hydrofluoric acid at room temperature, and the oxide film on the surface on which the ohmic contact electrode portion 8 was provided was removed. A sample with an immersion time of 0 seconds, a sample with an immersion time of 15 seconds, and a sample with an immersion time of 30 seconds were prepared. The sample with an immersion time of 0 seconds is a sample in which the n - silicon carbide substrate 1 is not immersed in hydrofluoric acid, that is, the oxide film is not removed.

次いで、スパッタ法によって厚さ６０ｎｍのニッケル膜を成膜し、オーミックコンタクト電極部８及びＴＬＭパターン領域上に残留するようにニッケル膜をパターニングした。また、ｎ-炭化珪素基板１の裏面にも厚さ６０ｎｍのニッケル膜を成膜した。 Next, a nickel film having a thickness of 60 nm was formed by sputtering, and the nickel film was patterned so as to remain on the ohmic contact electrode portion 8 and the TLM pattern region. A nickel film having a thickness of 60 nm was also formed on the back surface of the n − silicon carbide substrate 1.

次いで、ｎ-炭化珪素基板１をＲＴＡ炉に挿入し、窒素雰囲気で、カーボンサセプタに設置した熱電対で測定しながら毎秒４℃で１０００℃まで昇温し、５分間保持して、オーミックコンタクト電極部８となるニッケル膜及びＴＬＭパターン領域のニッケル膜をシリサイド化した。このとき、ＴＬＭパターン領域のニッケル膜の表面段差を触針式粗さ計（デクタック３０３０）で測定したところ、最も高低差のある部位の値は、浸漬時間１５秒の試料で約６０ｎｍであり、浸漬時間３０秒の試料で約５０ｎｍであった。 Then, n - silicon carbide substrate 1 is inserted into RTA furnace in a nitrogen atmosphere, the temperature was raised to 1000 ° C. per second 4 ° C. while measuring with a thermocouple placed on the carbon susceptor, and held for 5 minutes, ohmic contact electrode The nickel film to be the portion 8 and the nickel film in the TLM pattern region were silicided. At this time, when the surface level difference of the nickel film in the TLM pattern region was measured with a stylus type roughness meter (Dectac 3030), the value of the portion with the highest difference was about 60 nm for the sample with an immersion time of 15 seconds, The sample with an immersion time of 30 seconds was about 50 nm.

次いで、スパッタ法によって厚さ５μｍのアルミニウム膜を成膜し、ソースコンタクトパッド、ゲートコンタクトパッド及びＴＬＭ用の電極パッドとなる取出し電極９を形成した。   Next, an aluminum film having a thickness of 5 μm was formed by a sputtering method to form a takeout electrode 9 to be a source contact pad, a gate contact pad, and an electrode pad for TLM.

次いで、加熱による蒸着法によって、ｎ-炭化珪素基板１の裏面に厚さ１００ｎｍのチタン及び厚さ２００ｎｍの金（Ａｕ）を成膜し、ドレイン電極１０となる裏面電極を設けた。 Then, by an evaporation method by heating, n - depositing a gold (Au) titanium and thickness 200nm thick 100nm on the rear surface of the silicon carbide substrate 1, provided with a back electrode serving as the drain electrode 10.

以上のようにして、実施例として、酸化膜を除去するための弗酸への浸漬時間が０秒であるＭＯＳＦＥＴ素子、１５秒であるＭＯＳＦＥＴ素子、及び３０秒であるＭＯＳＦＥＴ素子を用意した。この３種のＭＯＳＦＥＴ素子に対して、ＴＬＭパターン領域において接触抵抗を測定した。この接触抵抗は、ｐコンタクト領域３と取出し電極９とのコンタクト抵抗に相当する。ウエハ面内の測定値から平均値を算出し、数式［（最大値−最小値）／（最大値＋最小値）］を用いて接触抵抗の分布を算出した。   As described above, as an example, a MOSFET element whose immersion time in hydrofluoric acid for removing an oxide film was 0 second, a MOSFET element of 15 seconds, and a MOSFET element of 30 seconds were prepared. The contact resistance was measured in the TLM pattern region for these three types of MOSFET elements. This contact resistance corresponds to the contact resistance between the p contact region 3 and the extraction electrode 9. The average value was calculated from the measured values in the wafer surface, and the contact resistance distribution was calculated using the formula [(maximum value−minimum value) / (maximum value + minimum value)].

・比較例
比較例として、実施例と同様の手順によって、酸化膜を除去するための弗酸への浸漬時間が４５秒であるＭＯＳＦＥＴ素子、及び６０秒であるＭＯＳＦＥＴ素子を作製した。ＴＬＭパターン領域のニッケル膜の表面段差を触針式粗さ計（デクタック３０３０）で測定したところ、最も高低差のある部位の値が、浸漬時間４５秒の試料及び６０秒の試料で、触針式粗さ計の測定ばらつきと同程度であった。従って、表面段差の最も高低差のある部位の値は２０ｎｍよりも小さいと判定した。 Comparative Example As a comparative example, a MOSFET element having an immersion time of 45 seconds in hydrofluoric acid for removing an oxide film and a MOSFET element having a duration of 60 seconds were manufactured by the same procedure as in the example. When the surface level difference of the nickel film in the TLM pattern area was measured with a stylus-type roughness meter (Dectac 3030), the values of the parts with the highest difference were the samples with a dipping time of 45 seconds and the samples with 60 seconds. It was almost the same as the measurement variation of the expression roughness meter. Therefore, it was determined that the value of the portion having the highest level difference in surface step was smaller than 20 nm.

・実施例と比較例との比較結果
実施例のＭＯＳＦＥＴ素子の方が比較例のＭＯＳＦＥＴ素子よりも、接触抵抗（平均値）及び接触抵抗分布のいずれも小さくなることを確認することができた。 -The comparison result of an Example and a comparative example It was able to confirm that the contact resistance (average value) and contact resistance distribution of the MOSFET element of an Example became smaller than the MOSFET element of a comparative example.

・炭化珪素半導体素子の製造方法の一例
図６は、本発明の実施の形態にかかる炭化珪素半導体素子の製造方法の一例を示す工程図である。図６に示すように、炭化珪素半導体素子の製造方法は、表面の高低差が１０ｎｍ未満の炭化珪素半導体の表面にニッケル膜を設ける工程（ステップＳ１）を含む。ステップＳ１に続いて、炭化珪素半導体とニッケル膜との界面に酸素が存在する状態でアニール処理を行って、炭化珪素半導体の表面にシリサイドを設ける工程（ステップＳ２）を含む。 FIG. 6 is a process diagram showing an example of a method for manufacturing a silicon carbide semiconductor element according to an embodiment of the present invention. As shown in FIG. 6, the method for manufacturing a silicon carbide semiconductor element includes a step (step S1) of providing a nickel film on the surface of a silicon carbide semiconductor having a surface height difference of less than 10 nm. Subsequent to step S1, an annealing process is performed in a state where oxygen is present at the interface between the silicon carbide semiconductor and the nickel film to provide silicide on the surface of the silicon carbide semiconductor (step S2).

・炭化珪素半導体素子の製造方法の別の例
図７は、本発明の実施の形態にかかる炭化珪素半導体素子の製造方法の別の例を示す工程図である。図７に示すように、炭化珪素半導体素子の製造方法は、炭化珪素半導体の表面の酸化膜の一部を除去する工程（ステップＳ１１）を含む。ステップＳ１１に続いて、表面の高低差が１０ｎｍ未満の炭化珪素半導体の表面にニッケル膜を設ける工程（ステップＳ１２）を含む。ステップＳ１２に続いて、炭化珪素半導体とニッケル膜との界面に酸素が存在する状態でアニール処理を行って、炭化珪素半導体の表面にシリサイドを設ける工程（ステップＳ１３）を含む。 FIG. 7 is a process diagram showing another example of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present invention. As shown in FIG. 7, the method for manufacturing the silicon carbide semiconductor element includes a step (step S11) of removing a part of the oxide film on the surface of the silicon carbide semiconductor. Subsequent to step S11, a step (step S12) of providing a nickel film on the surface of the silicon carbide semiconductor whose surface height difference is less than 10 nm is included. Subsequent to step S12, an annealing process is performed in a state in which oxygen is present at the interface between the silicon carbide semiconductor and the nickel film to provide silicide on the surface of the silicon carbide semiconductor (step S13).

実施の形態によれば、オーミックコンタクト電極部８が不連続な島状となり、オーミックコンタクト電極部８と炭化珪素半導体との境界線が途切れ途切れになることによって、剥離の起点となる部位がオーミックコンタクト電極部８の内部に発生するのが抑制される。そのため、オーミックコンタクト電極部８の機械的強度が高まる。また、ニッケルシリサイドよりも炭素濃度の高い炭素層２１が不連続な状態になるため、炭素層２１が連続した層状になる場合よりも、炭化珪素半導体に対するオーミックコンタクト電極部８の接触抵抗率が小さくなる。また、炭化珪素半導体の表面の酸化膜を残すことによって、酸化膜を全て除去する場合よりも、炭化珪素半導体に対するオーミックコンタクト電極部８の接触抵抗率が小さくなる。従って、コンタクト抵抗のばらつきを防ぎ、オーミックコンタクト電極部８の接触抵抗と密着性とを両立することができるため、長期にわたる駆動信頼性が得られる。また、炭化珪素半導体の表面の酸化膜を残すことによって、炭化珪素半導体とニッケル膜との界面に酸素を設ける処理を行わずに済むため、工程数の増加を抑えることができる。   According to the embodiment, the ohmic contact electrode portion 8 has a discontinuous island shape, and the boundary line between the ohmic contact electrode portion 8 and the silicon carbide semiconductor is interrupted. Generation | occurrence | production inside the electrode part 8 is suppressed. Therefore, the mechanical strength of the ohmic contact electrode portion 8 is increased. Further, since the carbon layer 21 having a carbon concentration higher than that of nickel silicide is in a discontinuous state, the contact resistivity of the ohmic contact electrode portion 8 with respect to the silicon carbide semiconductor is smaller than that in the case where the carbon layer 21 has a continuous layer shape. Become. Further, by leaving the oxide film on the surface of the silicon carbide semiconductor, the contact resistivity of the ohmic contact electrode portion 8 with respect to the silicon carbide semiconductor becomes smaller than when the oxide film is completely removed. Accordingly, variations in contact resistance can be prevented and both the contact resistance and the adhesiveness of the ohmic contact electrode portion 8 can be achieved, so that long-term driving reliability can be obtained. In addition, by leaving the oxide film on the surface of the silicon carbide semiconductor, it is not necessary to perform a process of providing oxygen at the interface between the silicon carbide semiconductor and the nickel film, so that an increase in the number of steps can be suppressed.

以上において本発明は、上述した実施の形態に限らず、種々変更可能である。例えば、実施の形態中に記載した寸法や濃度などは一例であり、本発明はそれらの値に限定されるものではない。また、ｐ型とｎ型の導電型を入れ替えた場合や、炭化珪素基板のおもて面側に炭化珪素基板と異なる導電型のエピタキシャル層を有する場合も、同様に成り立つ。この場合、ソース領域またはコンタクト領域となるｐ型の領域に接するｐコンタクトパターンを形成し、ソース領域またはコンタクト領域となるｎ型の領域に接するニッケルパターンを形成すればよい。   As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions and concentrations described in the embodiments are examples, and the present invention is not limited to these values. The same holds true when the p-type and n-type conductivity types are switched or when the silicon carbide substrate has an epitaxial layer having a conductivity type different from that of the silicon carbide substrate on the front surface side. In this case, a p-contact pattern in contact with the p-type region serving as the source region or contact region may be formed, and a nickel pattern in contact with the n-type region serving as the source region or contact region may be formed.

以上のように、本発明にかかる炭化珪素半導体素子及び炭化珪素半導体素子の製造方法は、半導体素子のおもて面側から裏面側へ電流が流れる縦型半導体装置に有用であり、特に、パワーデバイス等の電力用半導体装置、または産業用のモーター制御やエンジン制御に用いられるパワー半導体装置に適している。   As described above, the silicon carbide semiconductor element and the method for manufacturing the silicon carbide semiconductor element according to the present invention are useful for a vertical semiconductor device in which a current flows from the front surface side to the back surface side of the semiconductor element. It is suitable for power semiconductor devices such as devices, or power semiconductor devices used for industrial motor control and engine control.

１ ｎ-炭化珪素基板
８ オーミックコンタクト電極部
２１ 炭素層 1 n - silicon carbide substrate 8 ohmic contact electrode portion 21 carbon layer

Claims (4)

炭化珪素半導体の表面にニッケルシリサイド膜でできた電極を有し、
前記ニッケルシリサイド膜の表面凹凸が２０ｎｍ以上１５０ｎｍ以下の高低差を有し、
前記炭化珪素半導体と前記ニッケルシリサイド膜との境界線が不連続な点を有することを特徴とする炭化珪素半導体素子。 Having an electrode made of a nickel silicide film on the surface of the silicon carbide semiconductor;
The surface roughness of the nickel silicide film has a height difference of 20 nm to 150 nm,
A silicon carbide semiconductor element, wherein a boundary line between the silicon carbide semiconductor and the nickel silicide film has a discontinuous point. 前記電極には、ニッケルシリサイドと、前記ニッケルシリサイドよりも炭素濃度の高い部位とが混在していることを特徴とする請求項１に記載の炭化珪素半導体素子。   The silicon carbide semiconductor element according to claim 1, wherein nickel silicide and a portion having a higher carbon concentration than the nickel silicide are mixed in the electrode. 炭化珪素半導体の表面に酸化膜を形成後、前記炭化珪素半導体を０．５ｗｔ％の希弗酸液に３０秒以下の時間浸漬し、前記酸化膜の一部を除去する第１の工程と、
表面の高低差が１０ｎｍ未満の前記炭化珪素半導体の表面にニッケル膜を設ける第２の工程と、
前記炭化珪素半導体と前記ニッケル膜との界面に酸素が存在する状態でアニール処理を行って、前記炭化珪素半導体の表面にシリサイドを設ける第３の工程と、を含むことを特徴とする炭化珪素半導体素子の製造方法。 A first step of forming an oxide film on the surface of the silicon carbide semiconductor and then immersing the silicon carbide semiconductor in a 0.5 wt% dilute hydrofluoric acid solution for a period of 30 seconds or less to remove a portion of the oxide film; ,
A second step of providing a nickel film on the surface of the silicon carbide semiconductor having a surface height difference of less than 10 nm;
And a third step of performing an annealing process in the presence of oxygen at the interface between the silicon carbide semiconductor and the nickel film to provide silicide on the surface of the silicon carbide semiconductor. Device manufacturing method. 前記炭化珪素半導体と前記ニッケル膜との界面に存在する酸素が、プロセス中に生じる酸化膜であることを特徴とする請求項３に記載の炭化珪素半導体素子の製造方法。   The method for manufacturing a silicon carbide semiconductor element according to claim 3, wherein oxygen present at an interface between the silicon carbide semiconductor and the nickel film is an oxide film generated during the process.
JP2014185714A 2014-09-11 2014-09-11 Silicon carbide semiconductor element and method for manufacturing silicon carbide semiconductor element Active JP6395299B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014185714A JP6395299B2 (en) 2014-09-11 2014-09-11 Silicon carbide semiconductor element and method for manufacturing silicon carbide semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014185714A JP6395299B2 (en) 2014-09-11 2014-09-11 Silicon carbide semiconductor element and method for manufacturing silicon carbide semiconductor element

Publications (2)

Publication Number Publication Date
JP2016058657A JP2016058657A (en) 2016-04-21
JP6395299B2 true JP6395299B2 (en) 2018-09-26

Family

ID=55758902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014185714A Active JP6395299B2 (en) 2014-09-11 2014-09-11 Silicon carbide semiconductor element and method for manufacturing silicon carbide semiconductor element

Country Status (1)

Country Link
JP (1) JP6395299B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6584966B2 (en) * 2016-01-12 2019-10-02 株式会社東芝 Semiconductor device, semiconductor device manufacturing method, inverter circuit, drive device, vehicle, and elevator
DE102016125030A1 (en) 2016-12-20 2018-06-21 Infineon Technologies Ag Forming a metal contact layer on silicon carbide and semiconductor device having a metal contact structure
US11393911B2 (en) 2018-04-11 2022-07-19 Shindengen Electric Manufacturing Co., Ltd. Method of manufacturing semiconductor device and semiconductor device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3784393B2 (en) * 2003-07-02 2006-06-07 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JP4365894B2 (en) * 2007-08-07 2009-11-18 パナソニック株式会社 Method for manufacturing silicon carbide semiconductor element
CN101842878B (en) * 2007-10-24 2012-05-23 松下电器产业株式会社 Semiconductor device and method for manufacturing the same
JP5141227B2 (en) * 2007-12-12 2013-02-13 住友電気工業株式会社 Manufacturing method of semiconductor device
JP5448652B2 (en) * 2009-09-01 2014-03-19 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP2011146622A (en) * 2010-01-18 2011-07-28 Mitsubishi Electric Corp Method of manufacturing silicon carbide semiconductor device
JP5540331B2 (en) * 2010-01-29 2014-07-02 独立行政法人産業技術総合研究所 Field electron emission device and manufacturing method thereof
US8872189B2 (en) * 2011-08-05 2014-10-28 Sumitomo Electric Industries, Ltd. Substrate, semiconductor device, and method of manufacturing the same
JP5803786B2 (en) * 2012-04-02 2015-11-04 住友電気工業株式会社 Silicon carbide substrate, semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JP2016058657A (en) 2016-04-21

Similar Documents

Publication Publication Date Title
JP5525940B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP4942134B2 (en) Method for manufacturing silicon carbide semiconductor device
KR101230680B1 (en) Semiconductor device and method for manufacturing the same
JP6222771B2 (en) Method for manufacturing silicon carbide semiconductor device
JP5415650B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
JP2008235331A (en) Silicon carbide semiconductor device and manufacturing method of the same
JP4956783B2 (en) Method for manufacturing silicon carbide semiconductor device
JP5408248B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
JP2014170891A (en) Silicon carbide substrate, silicon carbide substrate manufacturing method and silicon carbide semiconductor device manufacturing method
JP2011151350A (en) Semiconductor device manufacturing method and the semiconductor device
JP2012160485A (en) Semiconductor device and manufacturing method of the same
JP5885284B2 (en) Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
JP6395299B2 (en) Silicon carbide semiconductor element and method for manufacturing silicon carbide semiconductor element
WO2015045628A1 (en) Method for manufacturing silicon-carbide semiconductor device
JP6376729B2 (en) Manufacturing method of semiconductor device
JP2006032457A (en) SiC SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
JP2010157547A (en) Method of manufacturing silicon carbide semiconductor device
JP6686581B2 (en) Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
JP2015065318A (en) Method for manufacturing silicon carbide semiconductor device
JP4645641B2 (en) Method for manufacturing SiC Schottky diode
JP5228308B2 (en) Manufacturing method of semiconductor device
JP6724444B2 (en) Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
JP5352999B2 (en) Manufacturing method of semiconductor device
JP2006093206A (en) Sic semiconductor device and manufacturing method thereof
JP7294156B2 (en) Semiconductor device manufacturing method

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170426

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170526

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170526

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180215

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180220

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180423

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180515

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180717

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180731

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180827

R150 Certificate of patent or registration of utility model

Ref document number: 6395299

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250