JP6333672B2 - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 41
- 239000002184 metal Substances 0.000 claims description 102
- 229910052751 metal Inorganic materials 0.000 claims description 102
- 238000009792 diffusion process Methods 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 description 25
- 230000003071 parasitic effect Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 12
- 150000002739 metals Chemical class 0.000 description 8
- 230000004048 modification Effects 0.000 description 8
- 238000012986 modification Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Description
図1は、実施形態1のESD保護素子の原理を模式的に説明する図である。
図2(A)は、実施形態1に基づくESD保護素子を上視した図である。
図2(B)に示されるように、拡散層130,132,134,136を跨ぐようにストライプコンタクト128が形成される。また、メタル142は、ビア154を介してストライプコンタクト128と接続される。また、メタル140は、ビア152を介してストライプコンタクト128と接続される。
図2(C)に示されるように、ダミーゲート電極126を跨ぐようにメタル140が配置される。ESD電流は、ストライプコンタクト128〜ビア152〜メタル140〜ストライプコンタクト124の経路に流れる。
図3に示されるように、パッドSPに対して並列に複数の経路を設けることも可能である。
図4に示されるように、半導体集積回路1は、外周領域に設けられる周回I/O領域4と、内側領域に配置され、所定の機能を有するASIC(application specific integrated circuit)として構成されるコアロジック領域2と、アナログ回路が形成されるアナログ領域3とを備える。
抵抗512およびNチャネルMOSトランジスタ514は、保護ダイオードD2と並列に設けられ、ノードN6と接地線GMとの間に直列に接続される。NチャネルMOSトランジスタ514のゲートは、接地線GMと接続される。
内部回路520は、ドライバ504,508を駆動する出力論理521と、パッドSPからの抵抗510を介する入力信号を処理する入力回路522と、信号レベルを昇圧/降圧するレベルシフタ523とを含む。
[実施形態1の変形例]
上記の実施形態1においては、ESD放電経路のトランジスタのソース側にバラスト抵抗を形成した場合について説明したが、ソース側およびドレイン側の両方に形成することも可能である。
半導体装置は、半導体基板22のウェル26上に形成するトランジスタの複数のゲート電極122,125,126と、トランジスタのソース・ドレインを形成するために各ゲート電極122,125,126の長さ方向(Y方向)に沿って形成される複数のストライプコンタクト120,123,124,128とを含む。また、ゲート電極125およびその両側に設けられたストライプコンタクト123,124で導電型トランジスタが形成される。ゲート電極122,126は、ダミーゲート電極として用いられる。
複数フィンガーの寄生バイポーラを動作させ易くする効果も生じる。
図8に示されるように、導電型トランジスタのドレイン側およびソース側の両方にバラスト抵抗を付加することでバラスト抵抗値を実施形態1の場合の2倍にすることが可能である。
[実施形態2]
図9は、実施形態2のESD保護素子の原理を模式的に説明する図である。
半導体装置は、半導体基板22のウェル26上に形成するトランジスタの複数のゲート電極122,125,126と、トランジスタのソース・ドレインを形成するために各ゲート電極122,125,126の長さ方向(Y方向)に沿って形成される複数のストライプコンタクト120,123,124,128とを含む。また、ゲート電極122およびその両側に設けられたストライプコンタクト120,123で導電型トランジスタが形成される。導電型トランジスタのストライプコンタクト120には、図示しないが基準電位(一例として接地電圧VSS)が印加される。ゲート電極125,126は、ダミーゲート電極として用いられる。半導体装置は、ダミーゲート電極125を跨ぐように両側に形成されるストライプコンタクト123,124を互いに電気的に接続するメタル140と、ダミーゲート電極126を跨ぐように両側に形成されるストライプコンタクト124,128を互いに電気的に接続するメタル143と、ストライプコンタクト128と接続されるパッドSPとをさらに含む。
図10は、実施形態3のESD保護素子の原理を模式的に説明する図である。
Claims (8)
- 半導体基板上に形成するトランジスタの複数のゲート電極と、
前記トランジスタのソース・ドレインを形成するために各前記ゲート電極と交互に前記ゲート電極の長さ方向に沿って形成される複数のストライプコンタクトとを備え、
ソース・ドレインの一方に基準電位が印加される導電型トランジスタが形成され、
前記導電型トランジスタのソース・ドレインの他方のストライプコンタクトと隣接するゲート電極は、第1のダミーゲート電極として用いられ、
前記第1のダミーゲート電極を跨ぐように両側に形成されるストライプコンタクトを互いに電気的に接続する第1のメタルと、
前記第1のダミーゲート電極の両側に形成されるストライプコンタクトのうち前記導電型トランジスタと反対側に設けられるストライプコンタクトと接続されるパッドとをさらに備える、半導体装置。 - 前記パッドに対して、前記導電型トランジスタと並列に接続された集積回路部をさらに備え、
前記導電型トランジスタは、前記パッドに入力された静電気放電電流を流す、請求項1記載の半導体装置。 - 前記パッドは、前記集積回路部の入力および出力の信号の少なくともいずれか一方の信号パッドである、請求項2記載の半導体装置。
- 前記パッドは、前記集積回路部の電源パッドである、請求項2記載の半導体装置。
- 前記導電型トランジスタのソース・ドレインの一方のストライプコンタクトと隣接するゲート電極は、第2のダミーゲート電極としてさらに用いられ、
前記第2のダミーゲート電極を跨ぐように両側に形成されるストライプコンタクトを互いに電気的に接続する第2のメタルをさらに備える、請求項1〜4のいずれか1項に記載の半導体装置。 - 前記導電型トランジスタに隣接する複数個の前記第1のダミーゲート電極が設けられ、
前記メタルは、各前記第1のダミーゲート電極を跨ぐように両側に形成されるストライプコンタクトを互いに電気的に結合し、
前記パッドは、前記第1のダミーゲート電極の両側に形成されるストライプコンタクトのうち前記導電型トランジスタと反対側の端部に設けられるストライプコンタクトと接続される、請求項1に記載の半導体装置。 - 隣接する前記ストライプコンタクト間同士の間に設けられる拡散層をさらに備え、
前記ゲート電極は、長さ方向に前記拡散層を跨ぐように形成される、請求項1〜6のいずれか一項に記載の半導体装置。 - 半導体基板上に形成するトランジスタの複数のゲート電極と、
前記トランジスタのソース・ドレインを形成するために各前記ゲート電極と交互に複数形成される複数の導電型拡散層と、
各前記導電型拡散層の直上域に設けられ、前記ゲート電極の長さ方向に沿って形成される複数のストライプコンタクトとを備え、
ソース・ドレインの一方に基準電位が印加される導電型トランジスタが形成され、
前記導電型トランジスタのソース・ドレインの他方のストライプコンタクトと隣接するゲート電極は、ダミーゲート電極として用いられ、
前記ダミーゲート電極の両側に形成される一方のストライプコンタクトと、前記導電型トランジスタのソース・ドレインの他方のストライプコンタクトとを電気的に接続するメタルと、
前記ダミーゲート電極の両側に形成される前記一方のストライプコンタクトと接続される配線と、
パッドと、
前記パッドから前記配線に対して順方向電流を流すように設けられたダイオードとをさらに備える、半導体装置。
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JP2014173798A JP6333672B2 (ja) | 2014-08-28 | 2014-08-28 | 半導体装置 |
US14/807,735 US9640526B2 (en) | 2014-08-28 | 2015-07-23 | Semiconductor device |
TW104127254A TW201614794A (en) | 2014-08-28 | 2015-08-21 | Semiconductor device |
KR1020150119113A KR20160026719A (ko) | 2014-08-28 | 2015-08-24 | 반도체 장치 |
CN201510535935.4A CN105390492B (zh) | 2014-08-28 | 2015-08-27 | 半导体器件 |
US15/446,470 US20170179112A1 (en) | 2014-08-28 | 2017-03-01 | Semiconductor device |
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US9773731B2 (en) | 2016-01-28 | 2017-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
US10332871B2 (en) * | 2016-03-18 | 2019-06-25 | Intel IP Corporation | Area-efficient and robust electrostatic discharge circuit |
WO2018025580A1 (ja) * | 2016-08-01 | 2018-02-08 | 株式会社ソシオネクスト | 半導体集積回路装置 |
US10325845B2 (en) * | 2017-06-21 | 2019-06-18 | Qualcomm Incorporated | Layout technique for middle-end-of-line |
EP3675167B1 (en) * | 2018-12-28 | 2021-06-09 | IMEC vzw | A semiconductor device and a method for forming a semiconductor device |
US10867917B1 (en) * | 2019-06-14 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device, associated method and layout |
KR20210071134A (ko) | 2019-12-05 | 2021-06-16 | 삼성전자주식회사 | 반도체 장치 |
US11315874B2 (en) | 2020-09-15 | 2022-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell structure with intermediate metal layers for power supplies |
KR20220106892A (ko) * | 2021-01-22 | 2022-08-01 | 삼성디스플레이 주식회사 | 표시 장치 |
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JP2006128422A (ja) * | 2004-10-29 | 2006-05-18 | Renesas Technology Corp | 半導体集積回路 |
JP5086797B2 (ja) * | 2007-12-26 | 2012-11-28 | 株式会社東芝 | 半導体装置 |
JP5593160B2 (ja) * | 2010-08-13 | 2014-09-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8648425B2 (en) * | 2011-06-28 | 2014-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resistors formed based on metal-oxide-semiconductor structures |
KR20130004834A (ko) * | 2011-07-04 | 2013-01-14 | 삼성전자주식회사 | 반도체 칩 및 그 반도체 칩을 포함한 플립-칩 패키지 |
US8691646B2 (en) * | 2012-05-03 | 2014-04-08 | Globalfoundries Inc. | FINFET compatible PC-bounded ESD diode |
US8884400B2 (en) * | 2012-12-27 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor in Post-Passivation structures and methods of forming the same |
US9620502B2 (en) * | 2013-04-10 | 2017-04-11 | Samsung Electronics Co., Ltd. | Semiconductor device including an extended impurity region |
KR102002453B1 (ko) * | 2013-04-10 | 2019-10-01 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US9461170B2 (en) * | 2014-04-23 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company Ltd. | FinFET with ESD protection |
-
2014
- 2014-08-28 JP JP2014173798A patent/JP6333672B2/ja active Active
-
2015
- 2015-07-23 US US14/807,735 patent/US9640526B2/en active Active
- 2015-08-21 TW TW104127254A patent/TW201614794A/zh unknown
- 2015-08-24 KR KR1020150119113A patent/KR20160026719A/ko unknown
- 2015-08-27 CN CN201510535935.4A patent/CN105390492B/zh active Active
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US20160064373A1 (en) | 2016-03-03 |
US20170179112A1 (en) | 2017-06-22 |
CN105390492B (zh) | 2020-08-04 |
US9640526B2 (en) | 2017-05-02 |
KR20160026719A (ko) | 2016-03-09 |
CN105390492A (zh) | 2016-03-09 |
JP2016048761A (ja) | 2016-04-07 |
TW201614794A (en) | 2016-04-16 |
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