JP6271440B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6271440B2 JP6271440B2 JP2014551475A JP2014551475A JP6271440B2 JP 6271440 B2 JP6271440 B2 JP 6271440B2 JP 2014551475 A JP2014551475 A JP 2014551475A JP 2014551475 A JP2014551475 A JP 2014551475A JP 6271440 B2 JP6271440 B2 JP 6271440B2
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Description
<半導体装置の構造について>
本実施の形態の半導体装置を、図面を参照して説明する。図1は、本実施の形態の半導体装置(半導体チップ)CPの全体平面図であり、半導体装置CPの上面側の全体平面図が示されている。また、図2および図3も、本実施の形態の半導体装置CPの全体平面図であるが、図1とは異なる層が示されている。図4〜図6は、本実施の形態の半導体装置CPの要部平面図である。図1〜図3に示される二点鎖線で囲まれた領域RG2を拡大したものが、図4〜図6に対応しているが、図4〜図6は、互いに異なる層が示されている。図7〜図13は、本実施の形態の半導体装置CPの要部断面図である。
次に、本実施の形態の半導体装置の製造工程の一例について図14〜図39を参照して説明する。図14〜図39は、本実施の形態の半導体装置の製造工程中の要部断面図である。図14〜図39のうち、図14、図16、図18、図20、図22、図24、図26、図28、図30、図32、図34、図36および図38には、上記図7に相当する断面図(図4のA−A線に相当する位置での断面図)が示されている。また、図14〜図39のうち、図15、図17、図19、図21、図23、図25、図27、図29、図31、図33、図35、図37および図39には、上記図10にほぼ相当する断面図(図4のD−D線に相当する位置での断面図)が示されている。なお、ここでは、本実施の形態の半導体装置の製造工程の好適な一例について説明するが、これに限定されず、種々変更可能である。
本実施の形態の半導体装置CPは、半導体基板SUBの主面のトランジスタ形成領域RG1に、パワートランジスタを構成するトレンチゲート型電界効果トランジスタを有する半導体装置である。
次に、本実施の形態の半導体装置CPにおける配線M1(ソース用配線M1S、ゲート用配線M1Gおよび制御電極用配線M1C)の平面レイアウトについて更に説明する。
まず、第2変形例について説明する。図48は、本実施の形態の半導体装置CPの第2変形例を示す平面図であり、上記図2に対応する全体平面図が示されている。図48に示される第2変形例の半導体装置CPを、半導体装置CP2と称することとする。
次に、第3変形例について説明する。図49〜図52は、本実施の形態の半導体装置CPの第3変形例を示す平面図または断面図である。図49〜図52に示される第3変形例の半導体装置CPを、半導体装置CP3と称することとする。図49〜図52のうち、図49は、上記図1に対応する全体平面図であり、図50は、上記図2に対応する全体平面図であり、図51は、上記図3に対応する全体平面図である。また、図52は、半導体装置CP3の要部断面図であるが、ゲート用配線部M1G4に沿った断面(後述の図59と同様の断面)が示されている。
次に、第4変形例について説明する。図53〜図62は、本実施の形態の半導体装置CPの第4変形例を示す平面図または断面図である。図53〜図62に示される第4変形例の半導体装置CPを、半導体装置CP4と称することとする。図53〜図62のうち、図53は、上記図1に対応する全体平面図であり、図54は、上記図2に対応する全体平面図であり、図55は、上記図3に対応する全体平面図であり、図56は、上記図4に対応する要部平面図であり、図57は、上記図5に対応する要部平面図であり、図58は、上記図6に対応する要部平面図である。但し、図53および図54に示される二点鎖線で囲まれた領域RG3を拡大したものが、図56〜図58に対応している。また、図59は、図56および図57のG−G線の断面図にほぼ対応し、図60は、図56および図57のH−H線の断面図にほぼ対応し、図61は、図56および図57のJ−J線の断面図にほぼ対応し、図62は、図56および図57のK−K線の断面図にほぼ対応している。
次に、第5変形例について説明する。図63〜図72は、本実施の形態の半導体装置CPの第5変形例を示す平面図または断面図である。図63〜図72に示される第5変形例の半導体装置CPを、半導体装置CP5と称することとする。図63〜図72のうち、図63は、上記図1に対応する全体平面図であり、図64は、上記図2に対応する全体平面図であり、図65は、上記図3に対応する全体平面図であり、図66は、上記図4に対応する要部平面図であり、図67は、上記図5に対応する要部平面図であり、図68は、上記図6に対応する要部平面図である。但し、図63および図64に示される二点鎖線で囲まれた領域RG3を拡大したものが、図66〜図68に対応している。また、図69は、図66および図67のL−L線の断面図にほぼ対応し、図70は、図66および図67のM−M線の断面図にほぼ対応し、図71は、図66および図67のN−N線の断面図にほぼ対応し、図72は、図66および図67のP−P線の断面図にほぼ対応している。
次に、第6変形例について説明する。図73〜図80は、本実施の形態の半導体装置CPの第6変形例を示す平面図または断面図である。図73〜図80に示される第6変形例の半導体装置CPを、半導体装置CP6と称することとする。図73〜図80のうち、図73は、上記図1に対応する全体平面図であり、図74は、上記図2に対応する全体平面図であり、図75および図77は、上記図4に対応する要部平面図であり、図76および図78は、上記図6に対応する要部平面図である。但し、図73および図74に示される二点鎖線で囲まれた領域RG4を拡大したものが、図75および図76に対応し、図73および図74に示される二点鎖線で囲まれた領域RG5を拡大したものが、図77および図78に対応している。また、図79は、図75のQ−Q線の断面図にほぼ対応し、図80は、図77のR−R線の断面図にほぼ対応している。
次に、第7変形例について説明する。図81〜図83は、本実施の形態の半導体装置CPの第7変形例を示す平面図である。図81〜図83に示される第7変形例の半導体装置CPを、半導体装置CP7と称することとする。図81〜図83は、いずれも、上記図2に対応する全体平面図である。
本実施の形態2では、上記実施の形態1の半導体装置(半導体チップ)を用いた半導体装置または電子装置の例について説明する。
C1 コンデンサ
CC 制御回路
CD1,CD2 導電膜
CP,CP1,CP2,CP3,CP,CP5,CP6,CP7 半導体装置
CP11,CP12,CP13,CP14 半導体チップ
CT1,CT2,CT3 コンタクトホール
DP1,DP2,DP3,DP4 ダイパッド
DR1,DR2 ドライバ回路
DR3 制御回路
EP エピタキシャル層
EP1 n−型エピタキシャル層
G1,G1a,G2,G2a,G3 絶縁膜
GE1 制御電極
GE2 ゲート電極
H1,H2,H3,H4 辺
I1,I2 電流
IL 絶縁膜
L1 コイル
LD,LD1,LD2,LD3,LD4,LD5,LD6,LD7,LD8 リード
LDR 連結部
LOD 負荷
M1 配線
M1C 制御電極用配線
M1C1,M1C2,M1C3,M1C4 制御電極用配線部
M1C5,M1C6,M1C7 制御電極用配線部
M1G ゲート用配線
M1G1,M1G2,M1G3,M1G4,M1G5 ゲート用配線部
M1S,M1S1,M1S2,M1S3,M1S4 ソース用配線
MP1,MP2,MP3 金属板
MR 封止部
MRa 上面
MRb 裏面
ND 出力ノード
NR n+型半導体領域(n+型ソース領域)
OP 開口部
PA 絶縁膜
PD3 パッド
PDC 制御電極用パッド
PDG ゲート用パッド
PDS,PDS1,PDS2,PDS3,PDS4 ソース用パッド
PDS5,PDS6 ソース用パッド
PKG,PKG1 半導体装置(半導体パッケージ)
PR p型半導体領域
PR2 n+型半導体領域
Q1 単位トランジスタセル
QH,QL パワーMOSトランジスタ(パワーMOSFET)
RG1,RG1a,RG1b,RG1c,RG1d トランジスタ形成領域
RG2,RG3,RG4,RG5 領域
RP1 フォトレジストパターン
SB 基板本体
SR シールリング
SUB 半導体基板
TE1,TE2 端子
TR1,TR1a,TR1b,TR2,TR2a,TR2b,TR2c 溝
TR3 積層領域
TR4 単層領域
Vout 出力電圧
W1,W2 幅
WA ワイヤ
Claims (21)
- 半導体基板の主面のトランジスタ形成領域に、パワートランジスタを構成するトレンチゲート型電界効果トランジスタを有する半導体装置であって、
前記半導体基板の前記トランジスタ形成領域に形成された第1溝と、
前記トランジスタ形成領域の周囲の前記半導体基板に形成され、前記第1溝に繋がっている第2溝と、
前記第1溝内の下部に形成された第1電極と、
前記第1溝内の上部に形成された、前記トレンチゲート型電界効果トランジスタ用のゲート電極と、
前記第1溝の側壁および底面と前記第1電極との間に形成された第1絶縁膜と、
前記第1溝の側壁と前記ゲート電極との間に形成された第2絶縁膜と、
前記第1電極と前記ゲート電極との間に形成された第3絶縁膜と、
前記半導体基板における前記第1溝に隣接する領域に形成された、第1導電型のソース用半導体領域、前記ソース用半導体領域の下に位置する前記第1導電型とは反対の第2導電型のチャネル形成用半導体領域、および、前記チャネル形成用半導体領域の下に位置する前記第1導電型のドレイン用半導体領域と、
前記半導体基板の前記主面上に形成された層間絶縁膜と、
前記層間絶縁膜上に形成され、前記ソース用半導体領域と電気的に接続されたソース用配線と、
前記層間絶縁膜上に形成され、前記ゲート電極と電気的に接続されたゲート用配線と、
前記層間絶縁膜上に形成され、前記第1電極と電気的に接続された第1配線と、
前記第2溝と前記ゲート用配線とが平面視で重なる領域の前記層間絶縁膜に形成されたゲート用コンタクトホールと、
前記第2溝と前記第1配線とが平面視で重なる領域の前記層間絶縁膜に形成された第1コンタクトホールと、
前記層間絶縁膜に形成されたソース用コンタクトホールと、
を有し、
前記第1配線は、導体を通じて前記ソース用配線と繋がっておらず、かつ、導体を通じて前記ゲート用配線と繋がっておらず、
前記第2溝は、内部に前記第1電極と前記ゲート電極とが埋め込まれている第1領域と、内部に前記第1電極が埋め込まれているが前記ゲート電極は埋め込まれていない第2領域とを有し、
前記第1領域の前記第2溝内の下部には、前記第1絶縁膜を介して前記第1電極が形成され、前記第1領域の前記第2溝内の上部には、前記第2絶縁膜を介して前記ゲート電極が形成され、前記第1領域の前記第2溝内の前記第1電極と前記ゲート電極との間には前記第3絶縁膜が形成され、
前記第2領域の前記第2溝内には、前記第1絶縁膜を介して前記第1電極が形成され、
前記ゲート用配線は、前記トランジスタ形成領域の周囲の前記層間絶縁膜上に形成され、
前記ゲート用コンタクトホールは、前記第1領域の前記第2溝の上方に形成され、前記ゲート用配線は、前記ゲート用コンタクトホールから露出する前記ゲート電極に電気的に接続され、
前記第1配線は、前記トランジスタ形成領域の周囲の前記層間絶縁膜上に形成され、
前記第1コンタクトホールは、前記第2領域の前記第2溝の上方に形成され、前記第1配線は、前記第1コンタクトホールから露出する前記第1電極に電気的に接続され、
前記ソース用配線は、前記トランジスタ形成領域の前記層間絶縁膜上に形成され、
前記ソース用配線は、前記層間絶縁膜に形成された前記ソース用コンタクトホールを通じて、前記ソース用半導体領域と電気的に接続され、
前記ソース用配線は、互いに第2方向に離間するように複数領域に分割されており、
前記ゲート用配線は、分割された前記ソース用配線の間を、前記第2方向に交差する第1方向に延在する第3ゲート用配線部を有し、
前記第1方向に延在する前記第3ゲート用配線部の下には、前記第2方向に延在する前記第2溝が、前記第1方向に複数並んでおり、
前記第3ゲート用配線部が前記第2方向に延在する前記第2溝と平面視で重なる領域に、前記ゲート用コンタクトホールが形成され、
前記第1配線は、分割された前記ソース用配線の間に配置され、前記第3ゲート用配線部と前記第2方向に隣り合うように前記第1方向に延在する第3配線部を有し、
前記第3配線部が前記第2方向に延在する前記第2溝と平面視で重なる領域に、前記第1コンタクトホールが形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1方向に延在する前記第3ゲート用配線部および前記第3配線部の下に配置され、前記第2方向にそれぞれ延在しかつ前記第1方向に並んだ複数の前記第2溝は、前記第1領域と前記第2領域とを有する前記第2溝と、前記第1領域を有するが前記第2領域を有さない前記第2溝とが混在している、半導体装置。 - 請求項1記載の半導体装置において、
前記第1溝内の前記ゲート電極の側面は、前記第2絶縁膜を介して、前記ソース用半導体領域および前記チャネル形成用半導体領域に対向し、
前記第1溝内の前記第1電極の側面および底面は、前記第1絶縁膜を介して、前記ドレイン用半導体領域に対向している、半導体装置。 - 請求項1記載の半導体装置において、
前記層間絶縁膜上に、前記ソース用配線、前記ゲート用配線および前記第1配線を覆うように形成された第4絶縁膜を更に有し、
前記ソース用配線の一部が前記第4絶縁膜のソース用開口部から露出されることにより、ソース用パッドが形成され、
前記ゲート用配線の一部が前記第4絶縁膜のゲート用開口部から露出されることにより、ゲート用パッドが形成され、
前記第1配線の一部が前記第4絶縁膜の第1開口部から露出されることにより、第1パッドが形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記半導体基板の前記主面とは反対側の裏面に形成された裏面ドレイン電極を更に有し、
前記裏面ドレイン電極は、前記ドレイン用半導体領域と電気的に接続されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2溝に埋め込まれた部分の前記ゲート電極は、前記第1溝に埋め込まれた部分の前記ゲート電極を前記ゲート用配線に接続するための配線部として機能し、
前記第2溝に埋め込まれた部分の前記第1電極は、前記第1溝に埋め込まれた部分の前記第1電極を前記第1配線に接続するための配線部として機能する、半導体装置。 - 請求項1記載の半導体装置において、
前記ゲート用配線は、前記半導体装置の主面の第1の辺に沿って前記第1方向に延在する第1ゲート用配線部を有し、
前記第1配線は、前記第1の辺に沿って前記第1方向に延在する第1配線部を有し、
前記第1方向は、前記第1の辺に沿った方向であり、
前記第1配線部は、平面視で、前記第1ゲート用配線部と前記第1の辺との間に配置されている、半導体装置。 - 請求項7記載の半導体装置において、
前記第1の辺に沿って前記第1ゲート用配線部および前記第1配線部が延在する領域では、前記第2方向に延在する前記第2溝が、前記第1方向に複数並んでおり、
前記第1ゲート用配線部が前記第2方向に延在する前記第2溝と平面視で重なる領域に、前記ゲート用コンタクトホールが形成され、
前記第1配線部が前記第2方向に延在する前記第2溝と平面視で重なる領域に、前記第1コンタクトホールが形成されている、半導体装置。 - 請求項8記載の半導体装置において、
前記トランジスタ形成領域内では、前記第2方向に延在する前記第1溝が前記第1方向に複数並んでいる、半導体装置。 - 請求項9記載の半導体装置において、
前記ゲート用配線は、前記半導体装置の主面の前記第1の辺に対向する第2の辺に沿って前記第1方向に延在する第2ゲート用配線部を有し、
前記第1配線は、前記第2の辺に沿って前記第1方向に延在する第2配線部を有し、
前記第2配線部は、平面視で、前記第2ゲート用配線部と前記第2の辺との間に配置されている、半導体装置。 - 半導体基板の主面のトランジスタ形成領域に、パワートランジスタを構成するトレンチゲート型電界効果トランジスタを有する半導体装置であって、
前記半導体基板の前記トランジスタ形成領域に形成された第1溝と、
前記トランジスタ形成領域の周囲の前記半導体基板に形成され、前記第1溝に繋がっている第2溝と、
前記第1溝内の下部に形成された第1電極と、
前記第1溝内の上部に形成された、前記トレンチゲート型電界効果トランジスタ用のゲート電極と、
前記第1溝の側壁および底面と前記第1電極との間に形成された第1絶縁膜と、
前記第1溝の側壁と前記ゲート電極との間に形成された第2絶縁膜と、
前記第1電極と前記ゲート電極との間に形成された第3絶縁膜と、
前記半導体基板における前記第1溝に隣接する領域に形成された、第1導電型のソース用半導体領域、前記ソース用半導体領域の下に位置する前記第1導電型とは反対の第2導電型のチャネル形成用半導体領域、および、前記チャネル形成用半導体領域の下に位置する前記第1導電型のドレイン用半導体領域と、
前記半導体基板の前記主面上に形成された層間絶縁膜と、
前記層間絶縁膜上に形成され、前記ソース用半導体領域と電気的に接続されたソース用配線と、
前記層間絶縁膜上に形成され、前記ゲート電極と電気的に接続されたゲート用配線と、
前記層間絶縁膜上に形成され、前記第1電極と電気的に接続された第1配線と、
前記第2溝と前記ゲート用配線とが平面視で重なる領域の前記層間絶縁膜に形成されたゲート用コンタクトホールと、
前記第2溝と前記第1配線とが平面視で重なる領域の前記層間絶縁膜に形成された第1コンタクトホールと、
前記層間絶縁膜に形成されたソース用コンタクトホールと、
を有し、
前記第1配線は、導体を通じて前記ソース用配線と繋がっておらず、かつ、導体を通じて前記ゲート用配線と繋がっておらず、
前記第2溝は、内部に前記第1電極と前記ゲート電極とが埋め込まれている第1領域と、内部に前記第1電極が埋め込まれているが前記ゲート電極は埋め込まれていない第2領域とを有し、
前記第1領域の前記第2溝内の下部には、前記第1絶縁膜を介して前記第1電極が形成され、前記第1領域の前記第2溝内の上部には、前記第2絶縁膜を介して前記ゲート電極が形成され、前記第1領域の前記第2溝内の前記第1電極と前記ゲート電極との間には前記第3絶縁膜が形成され、
前記第2領域の前記第2溝内には、前記第1絶縁膜を介して前記第1電極が形成され、
前記ゲート用配線は、前記トランジスタ形成領域の周囲の前記層間絶縁膜上に形成され、
前記ゲート用コンタクトホールは、前記第1領域の前記第2溝の上方に形成され、前記ゲート用配線は、前記ゲート用コンタクトホールから露出する前記ゲート電極に電気的に接続され、
前記第1配線は、前記トランジスタ形成領域の周囲の前記層間絶縁膜上に形成され、
前記第1コンタクトホールは、前記第2領域の前記第2溝の上方に形成され、前記第1配線は、前記第1コンタクトホールから露出する前記第1電極に電気的に接続され、
前記ソース用配線は、前記トランジスタ形成領域の前記層間絶縁膜上に形成され、
前記ソース用配線は、前記層間絶縁膜に形成された前記ソース用コンタクトホールを通じて、前記ソース用半導体領域と電気的に接続され、
前記ソース用配線は、互いに第2方向に離間するように複数領域に分割されており、
前記第1配線は、分割された前記ソース用配線の間を、前記第2方向に交差する第1方向に延在する第4配線部を有し、
前記ゲート用配線は、分割された前記ソース用配線の間に配置され、前記第4配線部を挟むように前記第1方向にそれぞれ延在する第4ゲート用配線部および第5ゲート用配線部を有している、半導体装置。 - 請求項11記載の半導体装置において、
前記第1方向に延在する前記第4ゲート用配線部、前記第4配線部および前記第5ゲート用配線部の下には、前記第2方向に延在する前記第2溝が、前記第1方向に複数並んでおり、
前記第4配線部が前記第2方向に延在する前記第2溝と平面視で重なる領域に、前記第1コンタクトホールが形成され、
前記第4ゲート用配線部が前記第2方向に延在する前記第2溝と平面視で重なる領域と、前記第5ゲート用配線部が前記第2方向に延在する前記第2溝と平面視で重なる領域とに、前記ゲート用コンタクトホールが形成されている、半導体装置。 - 請求項12記載の半導体装置において、
前記第1方向に延在する前記第4ゲート用配線部、前記第4配線部および前記第5ゲート用配線部の下に配置され、前記第2方向にそれぞれ延在しかつ前記第1方向に並んだ複数の前記第2溝のそれぞれは、前記第1領域と前記第2領域とを有している、半導体装置。 - 請求項11記載の半導体装置において、
前記第1溝内の前記ゲート電極の側面は、前記第2絶縁膜を介して、前記ソース用半導体領域および前記チャネル形成用半導体領域に対向し、
前記第1溝内の前記第1電極の側面および底面は、前記第1絶縁膜を介して、前記ドレイン用半導体領域に対向している、半導体装置。 - 請求項11記載の半導体装置において、
前記層間絶縁膜上に、前記ソース用配線、前記ゲート用配線および前記第1配線を覆うように形成された第4絶縁膜を更に有し、
前記ソース用配線の一部が前記第4絶縁膜のソース用開口部から露出されることにより、ソース用パッドが形成され、
前記ゲート用配線の一部が前記第4絶縁膜のゲート用開口部から露出されることにより、ゲート用パッドが形成され、
前記第1配線の一部が前記第4絶縁膜の第1開口部から露出されることにより、第1パッドが形成されている、半導体装置。 - 請求項11記載の半導体装置において、
前記半導体基板の前記主面とは反対側の裏面に形成された裏面ドレイン電極を更に有し、
前記裏面ドレイン電極は、前記ドレイン用半導体領域と電気的に接続されている、半導体装置。 - 請求項11記載の半導体装置において、
前記第2溝に埋め込まれた部分の前記ゲート電極は、前記第1溝に埋め込まれた部分の前記ゲート電極を前記ゲート用配線に接続するための配線部として機能し、
前記第2溝に埋め込まれた部分の前記第1電極は、前記第1溝に埋め込まれた部分の前記第1電極を前記第1配線に接続するための配線部として機能する、半導体装置。 - 請求項11記載の半導体装置において、
前記ゲート用配線は、前記半導体装置の主面の第1の辺に沿って前記第1方向に延在する第1ゲート用配線部を有し、
前記第1配線は、前記第1の辺に沿って前記第1方向に延在する第1配線部を有し、
前記第1方向は、前記第1の辺に沿った方向であり、
前記第1配線部は、平面視で、前記第1ゲート用配線部と前記第1の辺との間に配置されている、半導体装置。 - 請求項18記載の半導体装置において、
前記第1の辺に沿って前記第1ゲート用配線部および前記第1配線部が延在する領域では、前記第2方向に延在する前記第2溝が、前記第1方向に複数並んでおり、
前記第1ゲート用配線部が前記第2方向に延在する前記第2溝と平面視で重なる領域に、前記ゲート用コンタクトホールが形成され、
前記第1配線部が前記第2方向に延在する前記第2溝と平面視で重なる領域に、前記第1コンタクトホールが形成されている、半導体装置。 - 請求項19記載の半導体装置において、
前記トランジスタ形成領域内では、前記第2方向に延在する前記第1溝が前記第1方向に複数並んでいる、半導体装置。 - 請求項20記載の半導体装置において、
前記ゲート用配線は、前記半導体装置の主面の前記第1の辺に対向する第2の辺に沿って前記第1方向に延在する第2ゲート用配線部を有し、
前記第1配線は、前記第2の辺に沿って前記第1方向に延在する第2配線部を有し、
前記第2配線部は、平面視で、前記第2ゲート用配線部と前記第2の辺との間に配置されている、半導体装置。
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