JP6271021B2 - 超微細ピッチのPoPコアレスパッケージ - Google Patents
超微細ピッチのPoPコアレスパッケージ Download PDFInfo
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- JP6271021B2 JP6271021B2 JP2016538945A JP2016538945A JP6271021B2 JP 6271021 B2 JP6271021 B2 JP 6271021B2 JP 2016538945 A JP2016538945 A JP 2016538945A JP 2016538945 A JP2016538945 A JP 2016538945A JP 6271021 B2 JP6271021 B2 JP 6271021B2
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Description
しかし、より薄い基板をパッケージにおいて使用することから、材料の熱特性の違いを原因とする反りが生じる確率が高まり得る。薄型又はコアレス基板は、材料間の熱特性の違いがもたらす影響に抗する機械的強度が低いため、反りが生じる確率が高まり得る。
Claims (14)
- 半導体デバイスパッケージ組立体であって、
誘電材料の1つ以上の層を備え、誘電材料の前記層のうちの1つ以上内に1つ以上の導電配線を有する基板と、
前記基板と直接接触しており、前記基板の上面を少なくとも部分的に覆う補強層であって、前記基板に結合されるとともに前記補強層の上面で露出した1つ以上の端子を含み、前記基板の前記上面の少なくとも一部において端子パッドパターンを露出させる開口を含む補強層と、
前記基板の前記上面の前記端子パッドパターンに結合されたダイであって、前記補強層の前記開口内に位置しているダイと、
を備え、
前記基板の前記上面の前記端子パッドパターンが前記基板の前記上面で前記誘電材料の層内の前記導電配線によって画定され、前記上面の前記導電配線が前記補強層の前記開口で露出されている、組立体。 - 前記基板がコアレス基板である、請求項1に記載の組立体。
- 前記誘電材料がポリマー材料を含む、請求項1に記載の組立体。
- 前記補強層が、コア材料、ラミネート層、及び金属層、を含む、請求項1に記載の組立体。
- 前記補強層内の前記端子が、金属で少なくとも部分的に満たされた、前記補強層を貫通するビアを含む、請求項1に記載の組立体。
- 前記基板より上の前記補強層の高さが、前記基板より上の前記ダイの高さと略同様である、請求項1に記載の組立体。
- 前記ダイがシステムオンチップ(「SoC」)ダイを含む、請求項1に記載の組立体。
- 半導体デバイスパッケージ組立体を形成する方法であって、
キャリア上で補強層を形成することと、
前記補強層上で基板を形成することであって、前記基板の上面は前記補強層に直接接触している、ことと、
前記キャリアを前記補強層及び前記基板から除去することと、
前記基板の前記上面の少なくとも一部が露出する開口を前記補強層に形成するように前記補強層の一部分を除去することと、
前記基板の前記上面の前記露出した部分にダイを結合することと、
を含む、方法。 - 前記補強層がコア材料を含み、前記方法は、前記コア材料を貫通する1つ以上のビアを形成することと、前記ビアを金属で少なくとも部分的に満たすことと、を更に含む、請求項8に記載の方法。
- 前記補強層がコア材料を含み、前記方法は、前記コア材料のレーザーアブレーションを用いて前記開口の少なくとも一部を形成することを更に含む、請求項8に記載の方法。
- 前記補強層を形成し、その後前記補強層を前記キャリアに結合することによって前記補強層が前記キャリア上に形成される、請求項8に記載の方法。
- 前記基板が、1層以上のポリマー材料を含み、前記1層以上のポリマー材料内に1つ以上の導電配線を有し、前記方法は、前記開口内の前記基板の前記上面上で前記導電配線のうちの少なくとも1つを露出させることと、前記ダイを前記露出した導電配線に結合することと、を更に含む、請求項8に記載の方法。
- 前記基板が、前記補強層上に形成されており、かつ、介在材料なしで前記補強層と直接接触している、請求項8に記載の方法。
- 前記補強層とは反対側の前記基板の表面にマスクを形成することと、前記基板の前記表面で、前記マスクによって画定されるように1つ以上の端子を形成することと、を更に含む、請求項8に記載の方法。
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US14/088,736 US9305853B2 (en) | 2013-08-30 | 2013-11-25 | Ultra fine pitch PoP coreless package |
PCT/US2014/050312 WO2015031030A1 (en) | 2013-08-30 | 2014-08-08 | ULTRA FINE PITCH PoP CORELESS PACKAGE |
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