JP6220188B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6220188B2 JP6220188B2 JP2013168869A JP2013168869A JP6220188B2 JP 6220188 B2 JP6220188 B2 JP 6220188B2 JP 2013168869 A JP2013168869 A JP 2013168869A JP 2013168869 A JP2013168869 A JP 2013168869A JP 6220188 B2 JP6220188 B2 JP 6220188B2
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- insulating film
- trench
- groove
- layer
- semiconductor device
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Description
特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。
以下、図面を参照しながら本実施の形態の半導体装置について詳細に説明する。図1は、本実施の形態の半導体装置の構成を示す断面図である。図2〜図8は、本実施の形態の半導体装置の製造工程を示す断面図である。
図1は、本実施の形態の半導体装置の構成を示す断面図である。図1に示す半導体装置は、窒化物半導体を用いたMIS(Metal Insulator Semiconductor)型の電界効果トランジスタ(FET;Field Effect Transistor)である。この半導体装置は、高電子移動度トランジスタ(HEMT:High Electron Mobility Transistor)やパワートランジスタとも呼ばれる。本実施の形態の半導体装置は、いわゆるリセスゲート型の半導体装置である。
次いで、図2〜図8を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。図2〜図8は、本実施の形態の半導体装置の製造工程を示す断面図である。
以下に、本実施の形態の変形例について説明する。上記実施の形態においては、溝Tの内部を含む障壁層BA上の絶縁膜IF、ゲート絶縁膜GIおよびゲート電極GEを同時にエッチングした、即ち、同一のレジストマスクを用いて同じ平面外形状にパターニングしたが、これらを異なる平面形状としてもよい。図14は、本実施の形態の半導体装置の変形例の構成を模式的に示す断面図である。図14(A)は、第1変形例の半導体装置の断面図、図14(B)は、第2変形例の半導体装置の断面図である。なお、本変形例において、絶縁膜IF、ゲート絶縁膜GIおよびゲート電極GE以外の構成や製造工程は、上記実施の形態と同様であるため、その説明を省略する。
実施の形態1においては、溝Tの底面の端部をラウンド化、言い換えれば、溝Tの底面の端部に丸みを持たせたが、溝Tの底面の端部の形状は曲面である必要はなく、溝Tの底面のL字状の端部を面取りした形状としてもよい。図15は、本実施の形態の半導体装置の構成を模式的に示す断面図である。なお、本実施の形態において、溝T以外の構成や製造工程は、実施の形態1と同様であるため、その説明を省略する。
(第1例)
実施の形態1においては、溝Tの側面を、チャネル層CHや障壁層BAの表面、または溝Tの底面の中央部の表面である(0001)Ga面に対し、ほぼ垂直(θ=90°)としたが、溝Tの側面(側壁)を、テーパー形状としてもよい。図17は、本実施の形態の半導体装置の第1例の構成を模式的に示す断面図である。なお、本実施の形態において、溝T以外の構成や製造工程は、実施の形態1と同様であるため、その説明を省略する。
上記第1例においては、溝Tにテーパー形状の側面を設けたが、溝Tの側面と底面とを一体としてラウンド化してもよい。図18は、本実施の形態の半導体装置の第2例の構成を模式的に示す断面図である。なお、本実施の形態において、溝T以外の構成や製造工程は、実施の形態1と同様であるため、その説明を省略する。
(第1例)
実施の形態1(図10)においては、ゲート電極GEの底部が、障壁層BAの表面の位置よりも低い位置に表示されているが、ゲート電極GEの底部を、障壁層BAの表面の位置よりも高い位置に配置してもよい。図19は、本実施の形態の半導体装置の第1例の構成を模式的に示す断面図である。なお、本実施の形態において、溝T、ゲート絶縁膜GIおよびゲート電極GE以外の構成や製造工程は、上記実施の形態と同様であるため、その説明を省略する。
実施の形態3(図17)においては、ゲート電極GEの底部が、障壁層BAの表面の位置よりも低い位置に表示されているが、ゲート電極GEの底部を、障壁層BAの表面の位置よりも高い位置に配置してもよい。図20は、本実施の形態の半導体装置の第2例の構成を模式的に示す断面図である。なお、本実施の形態において、溝T、ゲート絶縁膜GIおよびゲート電極GE以外の構成や製造工程は、上記実施の形態と同様であるため、その説明を省略する。
BA 障壁層
BU バッファ層
C チャネル
C1 コンタクトホール
CH チャネル層
D 距離
DE ドレイン電極
DP ドレインパッド
GE ゲート電極
GI ゲート絶縁膜
GL ゲート配線
GP ゲートパッド
IF 絶縁膜
IL1 絶縁層
IL2 絶縁層
NUC 核生成層
OL オーミック層
S 基板
SE ソース電極
SP ソースパッド
STR 歪緩和層
T 溝
Th 膜厚
TP テーパー
TP1 テーパー
TP2 テーパー
Claims (2)
- 基板の上方に形成された第1窒化物半導体層と、
前記第1窒化物半導体層上に形成され、前記第1窒化物半導体層よりバンドギャップが広い第2窒化物半導体層と、
前記第2窒化物半導体層を貫通し、前記第1窒化物半導体層の途中まで到達する溝と、
前記溝内にゲート絶縁膜を介して配置されたゲート電極と、
を有し、
前記溝の底面の端部が面取りされた形状であり、前記溝の底面の端部に接する前記ゲート絶縁膜が面取りされた形状であり、
前記溝の上部の前記ゲート電極の底部が、前記第2窒化物半導体層の表面の位置よりも高い位置に配置され、
前記溝の底面の端部が、第1テーパー形状部および前記第1テーパー形状部の下方に位置する第2テーパー形状部よりなり、前記第2テーパー形状部と前記溝の底面とのなす角が、前記第1テーパー形状部と前記溝の底面とのなす角より小さい、半導体装置。 - 基板の上方に形成された第1窒化物半導体層と、
前記第1窒化物半導体層上に形成され、前記第1窒化物半導体層よりバンドギャップが広い第2窒化物半導体層と、
前記第2窒化物半導体層を貫通し、前記第1窒化物半導体層の途中まで到達する溝と、
前記溝内にゲート絶縁膜を介して配置されたゲート電極と、
を有し、
前記溝の底面の端部が面取りされた形状であり、前記溝の底面の端部に接する前記ゲート絶縁膜が面取りされた形状であり、
前記溝の上部の前記ゲート電極の底部が、前記第2窒化物半導体層の表面の位置よりも高い位置に配置され、
前記溝の底面の端部が、複数のテーパー形状部よりなる、半導体装置。
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KR20140104359A KR20150020105A (ko) | 2013-08-15 | 2014-08-12 | 반도체 장치 및 반도체 장치의 제조 방법 |
CN201410403957.0A CN104377240B (zh) | 2013-08-15 | 2014-08-15 | 半导体器件和制造半导体器件的方法 |
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US10276712B2 (en) | 2014-05-29 | 2019-04-30 | Hrl Laboratories, Llc | III-nitride field-effect transistor with dual gates |
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JP2016164906A (ja) * | 2015-03-06 | 2016-09-08 | 豊田合成株式会社 | 半導体装置およびその製造方法ならびに電力変換装置 |
US9812532B1 (en) | 2015-08-28 | 2017-11-07 | Hrl Laboratories, Llc | III-nitride P-channel transistor |
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US11121229B2 (en) * | 2017-12-28 | 2021-09-14 | Vanguard International Semiconductor Corporation | Methods of fabricating semiconductor structures and high electron mobility transistors |
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