JP6193665B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6193665B2 JP6193665B2 JP2013155546A JP2013155546A JP6193665B2 JP 6193665 B2 JP6193665 B2 JP 6193665B2 JP 2013155546 A JP2013155546 A JP 2013155546A JP 2013155546 A JP2013155546 A JP 2013155546A JP 6193665 B2 JP6193665 B2 JP 6193665B2
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Description
<半導体装置>
図1は実施の形態の半導体装置の構造の一例を示す平面図、図2は図1の半導体装置の構造の一例を示す裏面図、図3は図1の半導体装置の構造の一例を示す断面図、図4は図1の半導体装置の構造の一例を示す側面図、図5は図1の半導体装置の構造を封止体を透過して示す平面図である。
図6は図1の半導体装置の組み立て手順の一例を示すフロー図である。
図7は図1の半導体装置の組み立てで用いられる配線基板のチップ搭載面側の構造の一例を示す平面図、図8は図1の半導体装置の組み立てで用いられる配線基板の実装面側の構造の一例を示す裏面図、図9は図8のA部を拡大して示す部分拡大平面図である。また、図10は図9の基板領域におけるエッチバック後の配線パターンの一例を示す部分拡大平面図、図11は図10のA−A線に沿って切断した構造の一例を示す部分断面図である。
図12は図1の半導体装置の組み立ての基板準備工程で準備する配線基板の構造の一例を示す部分拡大断面図、図13はダイボンディング後の構造の一例を示す部分拡大断面図、図14は図1の半導体装置の組み立てにおけるワイヤボンディング後の構造の一例を示す部分拡大断面図、図15は図12に示す配線基板の構造の一例を示す部分拡大平面図である。さらに、図16は図13に示すダイボンディング後の基板の全体構造の一例を示す平面図、図17は図13に示すダイボンディング後の構造の一例を示す部分拡大平面図、図18は図14に示すワイヤボンディング後の基板の全体構造の一例を示す平面図、図19は図14に示すワイヤボンディング後の構造の一例を示す部分拡大平面図である。
図6のステップS1で配線基板(図12および図15参照)31を準備した後、ダイボンディング工程を行って、図13、図16および図17に示すように、配線基板31の上面31aの半導体装置領域31ba上に半導体チップ2を接着材8を介して搭載して接合(ダイボンディング、チップマウント)する(図6のステップS2)。さらに、配線基板31の半導体装置領域31bb上に半導体チップ7を接着材8を介して搭載して接合する。
図14、図18および図19に示すように、ワイヤボンディングを行って、半導体チップ2の各電極2aと、これに対応する配線基板31に形成された接続端子15とをワイヤ4を介して電気的に接続する(図6のステップS3)。すなわち、配線基板31の上面31aの半導体装置領域31baの複数の接続端子15と、その半導体装置領域31ba上に接合された半導体チップ2の複数の電極2aとを複数のワイヤ4を介して電気的に接続する。同様に、半導体装置領域31bb上に接合された半導体チップ7の複数の電極7aとを複数のワイヤ4を介して電気的に接続する。
次に、図20および図22に示すように、モールド工程(樹脂成形工程、例えばトランスファモールド工程)を行う。本工程では、配線基板31上に搭載された複数の半導体チップ2,7を一括して封止する一括封止体(封止樹脂、封止部、一括封止部)13を形成する(図6のステップS4)。すなわち、本実施の形態のモールド工程では、MAP(Mold Array Package)方式を採用している。
図21に示すように、配線基板31の下面32aのランド(図20参照)16に、導電性部材として半田ボール(外部端子、半田材、メッキ膜)6を接続(接合、形成)する(図6のステップS5)。ステップS5の半田ボール6接続工程では、例えば、配線基板31の下面32aを上方に向け、配線基板31の下面32aの半導体装置領域32baの複数のランド16a上にそれぞれ半田ボール6aを配置(搭載)してフラックスなどで仮固定し、一方、半導体装置領域32bbの複数のランド16b上にそれぞれ半田ボール6bを配置(搭載)してフラックスなどで仮固定する。
まず、図23〜図25を用いて、切断工程の全般について説明する。すなわち、ダイシングブレード(ダイシングソー、ブレード)9などを用い、配線基板31の下面32aの半導体装置領域32baと半導体装置領域32bbとの間のダイシング領域(ダイシングライン、各半導体装置領域の境界部)32cに沿って、配線基板31の下面32a側から、ダイシング(切断、切削)を行う。これにより、ダイシング領域上に形成された一括封止体13と配線基板31の一部(ダイシング領域に対応する部分)とを切断(分割)する(図6のステップS7)。
以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明はこれまで記載した実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
上記実施の形態では、半導体装置の製造方法として、MAP方式を採用した組み立てについて説明したが、上記半導体装置の組み立てとしては、MAP方式に限定されるものではなく、配線基板の個々の半導体装置領域を個別に樹脂モールドし、その後、ダイシングによる切断を行って個々の半導体装置を取得する個片モールド方式の組み立てを採用してもよい。
上記実施の形態では、半導体装置の一例として、半田ボール6を有するBGAの場合を説明したが、上記半導体装置は、BGAに限らず、半田ボール6のような突起状の導電性部材ではなく、メッキ膜のような導電性部材がランドの表面に形成された、あるいはランドの表面が導電性部材で覆われない、LGA(Land Grid Array)であってもよい。
上記実施の形態では、基板準備工程で準備される配線基板31が、そのダイシング領域32cにおいて、メッキ用の給電線がエッチング等によって予め除去されている基板の場合を説明したが、ダイシング領域32c内にメッキ用の給電線が設けられた状態の配線基板を準備した後、ダイシング領域32c内のメッキ用の給電線をエッチング等によって除去してもよい。
図26は図20に示す個片化時の実装面側の基板構造(エッチバック無し)の一例を示す部分拡大平面図、図27は図26のA−A線に沿って切断した構造の一例を示す断面図である。
図28は変形例5の配線基板の実装面側の構造を示す部分拡大平面図である。
図29〜図33に示す変形例6のターゲットマークの構造を示す部分拡大平面図である。
さらに、上記実施の形態で説明した技術思想の要旨を逸脱しない範囲内において、変形例同士を組み合わせて適用することができる。
2 半導体チップ
2a 電極(ボンディングパッド、パッド電極)
2b 表面(主面、上面)
2c 裏面(実装面、下面)
3 配線基板
3a 上面(チップ支持面)
3b 下面(実装面)
4 ボンディングワイヤ
5 封止体(封止樹脂、樹脂体、封止部、封止樹脂部)
6,6a,6b 半田ボール(外部端子)
7 半導体チップ
7a 電極(ボンディングパッド、パッド電極)
8 接着材(ダイボンド材、接合材)
9 ダイシングブレード
10 固定テープ(ダイシングテープ)
11 基材層(コア材)
12 導体層(導体パターン、導体膜パターン、配線層)
13 一括封止体(封止樹脂、封止部、一括封止部)
14 ソルダレジスト層(絶縁層、絶縁膜、半田レジスト層)
15,15a,15b 接続端子(ボンディングリード、電極)
16,16a,16b ランド(バンプランド、ランド部、電極)
16c,16d 最外周ランド列
17 封止構造体
31 配線基板(配線基板母体)
31a 上面(チップ搭載面)
31b,31ba,31bb 半導体装置領域(上面側デバイス領域)
31c ダイシング領域(スクライブ領域、切断領域)
32a 下面(実装面)
32b,32ba,32bb 半導体装置領域(下面側デバイス領域)
32c ダイシング領域(スクライブ領域、切断領域)
32d 周縁部
32e ターゲットマーク(ターゲットパターン)
32ea 第1パターン
32eaa 第1延在部
32eab 第2延在部
32eac 交差部
32eb 第2パターン
32eba 第1延在部
32ebb 第2延在部
32ebc 交差部
32f 開口部
32g アライメントパターン
32h ブレード幅
32i 給電線
33 位置決め孔
34 ガイド孔
41 配線基板
42 ターゲットマーク
43 異物(屑、金属片)
44 ダイシングブレード
44a エッジ部
Claims (4)
- 以下の工程を含む半導体装置の製造方法:
(a)上面と、前記上面とは反対側の下面と、前記下面に設けられた第1デバイス領域と、前記下面に設けられ、かつ、前記第1デバイス領域の隣に設けられた第2デバイス領域と、前記第1デバイス領域と前記第2デバイス領域との間に設けられたダイシング領域と、前記下面に設けられ、かつ、前記第1デバイス領域、前記第2デバイス領域および前記ダイシング領域の周囲に設けられた周縁部と、前記周縁部に設けられ、かつ、前記ダイシング領域の延長線上には設けられないターゲットマークと、前記第1デバイス領域において行列状に設けられた複数の第1バンプランドと、前記第2デバイス領域において行列状に設けられた複数の第2バンプランドと、前記複数の第1バンプランドおよび前記複数の第2バンプランドを露出するように前記下面上に形成された絶縁膜と、を備えた配線基板を準備する工程;
ここで、
前記複数の第1バンプランドは、前記複数の第1バンプランドのうちの最外周列に配置され、かつ、前記ダイシング領域に最も近い第1最外周バンプランド列を有し、
前記複数の第2バンプランドは、前記複数の第2バンプランドのうちの最外周列に配置され、かつ、前記ダイシング領域に最も近い第2最外周バンプランド列を有し、
前記ターゲットマークは、平面視において前記ダイシング領域の前記延長線と前記第1最外周バンプランド列の延長線との間に設けられた第1パターンと、平面視において前記ダイシング領域の前記延長線と前記第2最外周バンプランド列の延長線との間に設けられ、かつ、前記第1パターンから離間した第2パターンと、から成り、
前記第1パターンおよび前記第2パターンには、第1給電線および第2給電線が、それぞれ接続されており、
前記第1給電線および前記第2給電線のそれぞれは、前記絶縁膜から露出した第1部分と、前記絶縁膜で覆われた第2部分と、を有し、
前記第1パターン、前記第2パターン、前記第1給電線および前記第2給電線のそれぞれは、導電性部材から成り、
前記絶縁膜から露出する前記第1パターンの表面および前記絶縁膜から露出する前記第2パターンの表面には、前記第1給電線および前記第2給電線を用いて、電解メッキ膜がそれぞれ形成されており、
(b)前記(a)工程の後、前記配線基板の前記上面に第1半導体チップおよび第2半導体チップを、それぞれ搭載する工程;
(c)前記(b)工程の後、前記第1半導体チップおよび前記第2半導体チップを樹脂で封止する工程;
(d)前記(c)工程の後、前記複数の第1バンプランドに複数の第1外部端子を、前記複数の第2バンプランドに複数の第2外部端子を、それぞれ形成する工程;
(e)前記(d)工程の後、前記ターゲットマークに基づいて前記ダイシング領域を特定し、前記ダイシング領域に沿って前記配線基板を切断する工程、
ここで、
前記(e)工程では、回転する切断刃を用いて、前記配線基板の前記ダイシング領域と、前記配線基板の前記周縁部のうち、前記第1パターン、前記第2パターン、前記第1給電線および前記第2給電線が設けられていない前記第1パターンと前記第2パターンの間の領域を切断する。 - 請求項1に記載の半導体装置の製造方法において、
前記配線基板の前記上面上には、絶縁膜が形成されており、
前記複数の第1バンプランドおよび第2バンプランドのそれぞれの表面にはメッキ膜が形成されており、
前記メッキ膜を形成する工程では、前記ダイシング領域に形成された給電線を用いて前記メッキ膜を形成し、
前記メッキ膜を形成した後、前記配線基板の前記ダイシング領域に形成された前記給電線および前記給電線を覆う前記絶縁膜は除去される、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記配線基板の前記ダイシング領域には、前記第1パターン、前記第2パターン、前記複数の第1バンプランドおよび前記複数の第2バンプランドのそれぞれと電気的に接続する第3給電線が設けられており、
前記第3給電線は前記絶縁膜によって覆われている、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第1パターンと前記第2パターンのそれぞれの大きさは、互いに異なっている、半導体装置の製造方法。
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