JP6129177B2 - 電子部品モジュールとその実装体 - Google Patents
電子部品モジュールとその実装体 Download PDFInfo
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- JP6129177B2 JP6129177B2 JP2014527941A JP2014527941A JP6129177B2 JP 6129177 B2 JP6129177 B2 JP 6129177B2 JP 2014527941 A JP2014527941 A JP 2014527941A JP 2014527941 A JP2014527941 A JP 2014527941A JP 6129177 B2 JP6129177 B2 JP 6129177B2
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- 239000004065 semiconductor Substances 0.000 claims description 180
- 239000000758 substrate Substances 0.000 claims description 135
- 230000017525 heat dissipation Effects 0.000 claims description 73
- 229910052751 metal Inorganic materials 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 50
- 230000020169 heat generation Effects 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000000926 separation method Methods 0.000 description 28
- 230000004048 modification Effects 0.000 description 20
- 238000012986 modification Methods 0.000 description 20
- 238000010586 diagram Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 239000004519 grease Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000010897 surface acoustic wave method Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
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- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/12—Passive devices, e.g. 2 terminal devices
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Description
図1(a)、(b)及び(c)は、本実施形態の例示的電子部品モジュール100を模式的に示す上面図、断面図及び下面図であり、図1(b)は、図1(a)におけるIb-Ib'線及び図1(c)におけるIb-Ib'線に対応する。
次に、第1の実施形態の変形例1について説明する。図4(a)、(b)及び(c)は、本変形例の電子部品モジュール100aを模式的に示す上面図、断面図及び下面図であり、図4(b)は、図4(a)におけるIVb-IVb'線及び図4(c)におけるIVb-IVb'線に対応する。尚、図1(a)〜(c)に示す電子部品モジュール100と同じ構成要素には同じ符号を付し、以下では主に相違点を説明する。
第1の実施形態及びその変形例1において、外部端子51の先端に接続部材57が設けられていると説明した。しかしながら、接続部材は、実装基板60の側に設けられていても良い。
次に、図6(a)及び(b)には、実装基板60に設ける放熱構造について更に示している。
図7(a)及び(b)は、実装基板60に凹部を設けることなく熱放散パターン63を形成し、当該熱放散パターン63上に金属層71を設けた変形例を示している。熱放散パターン63と金属層71との間には、グリース等の絶縁材が介在しても良い。
次に、第2の実施形態の例示的電子部品モジュール100eについて説明する。図8(a)、(b)及び(c)は、本実施形態の例示的電子部品モジュール100eを模式的に示す上面図、断面図及び下面図であり、図8(b)は、図8(a)におけるVIIIb-VIIIb'線及び図8(c)におけるVIIIb-VIIIb'線に対応する。尚、図1(a)〜(c)に示す電子部品モジュール100と同じ構成要素には同じ符号を付している。
次に、第2の実施形態の変形例における例示的電子部品モジュール100fについて説明する。図9(a)、(b)及び(c)は、本変形例の例示的電子部品モジュール100fを模式的に示す上面図、断面図及び下面図であり、図9(b)は、図9(a)におけるIXb-IXb'線及び図8(c)におけるIXb-IXb'線に対応する。尚、図8(a)〜(c)に示す電子部品モジュール100eと同じ構成要素には同じ符号を付している。
図10(a)〜(d)に、第2の実施形態の電子部品モジュール100eの製造工程を模式的な断面図にて示す。
次に、第3の実施形態における例示的電子部品モジュール100gについて説明する。図11(a)は、本実施形態の例示的電子部品モジュール100fを模式的に示す下面図、であり、図11(b)及び(c)は、図11(a)におけるXIb-XIb'線及びXIc-XIc'線に対応する断面を模式的に示す図である。尚、図1(a)〜(c)に示す電子部品モジュール100と同じ構成要素には同じ符号を付している。
次に、第4の実施形態における例示的電子部品モジュール100hについて説明する。図13(a)〜(c)は、それぞれ本実施形態の例示的電子部品モジュールを模式的に示す下面図であり、3種類の例を示している。尚、図8(a)に示す第3の実施形態の電子部品モジュール100gと同じ構成要素には同じ符号を付している。
11 バンプ
12 発熱回路
13 金属層
14 発熱領域
15 高温領域
20 第2の半導体チップ
21 バンプ
31 チップ部品
41 多層基板
42 アンテナ配線
43 熱放散パターン
44 基板分離ライン
45 ブレード
50 枠体
51 外部端子
52 放熱用端子
53 放熱ルート
55 段差部
56 隙間
57 接続部材
57a 接続部材
58 分離壁
60 実装基板
61 レジスト
62 端子実装ランド
63 熱放散パターン
64 放熱ビア
71 金属層
72 金属層
100 電子部品モジュール
100a 電子部品モジュール
100e 電子部品モジュール
100f 電子部品モジュール
100g 電子部品モジュール
100h 電子部品モジュール
100i 電子部品モジュール
100j 電子部品モジュール
Claims (13)
- 基板と、
前記基板の第一面に設けられた複数の外部端子と、
前記第一面における前記複数の外部端子に囲まれた領域に設けられた第1の半導体チップと、
前記基板における前記第一面とは反対側の第二面に設けられた配線部とを備え、
前記第1の半導体チップは、前記外部端子の先端よりも、前記第一面の法線の向きに突出しており、
前記配線部は無線機能を有するアンテナ配線であることを特徴とする電子部品モジュール。 - 請求項1において、
前記配線部と少なくとも1つの前記外部端子とは電気的に接続されていることを特徴とする電子部品モジュール。 - 請求項1又は2において、
前記複数の外部端子の先端上に接続部材を備え、
前記接続部材は、前記第1の半導体チップよりも、前記第一面の法線の向きに突出していることを特徴とする電子部品モジュール。 - 請求項1又は2において、
前記第1の半導体チップが前記外部端子よりも突出する寸法は、前記外部端子を実装基板に接続する際に前記実装基板上に設けられる接続部材の高さよりも小さいことを特徴とする電子部品モジュール。 - 請求項1〜4のいずれか1つにおいて、
前記第二面には前記アンテナ配線の他には電子部品が設けられておらず、
前記基板の前記第一面における周縁部の少なくとも一部に枠体が設けられ、
前記複数の外部端子は、前記枠体に埋め込まれるように形成されていることを特徴とする電子部品モジュール。 - 請求項1〜5のいずれか1つにおいて、
前記第一面における前記複数の外部端子に囲まれた領域に、第2の半導体チップを更に備え、
前記第1の半導体チップはベースバンドICであり、
前記第2の半導体チップは高周波ICであり、
前記第1の半導体チップは、前記第2の半導体チップに比べて面積が大きく、厚さが厚く且つ発熱量が多いことを特徴とする電子部品モジュール。 - 請求項1〜6のいずれか1つにおいて、
前記第1の半導体チップ上に金属層を備え、
前記第1の半導体チップ自体に代えて、前記金属層が、前記外部端子の先端よりも、前記第一面の法線の向きに突出していることを特徴とする電子部品モジュール。 - 請求項6において、
前記第1の半導体チップ及び前記第2の半導体チップは、前記基板の前記第一面にバンプ接続されていることを特徴とする電子部品モジュール。 - 請求項1〜8のいずれか1つの電子部品モジュールが実装基板に実装され、
前記外部端子と、前記実装基板上に設けられた端子実装ランドとは、半田を接続部材として接合され、
前記第1の半導体チップは、前記実装基板の放熱部に接していることを特徴とする電子部品モジュール実装体。 - 請求項9において、
前記放熱部は、前記実装基板上に設けられた金属層からなることを特徴とする電子部品モジュール実装体。 - 請求項9において、
前記放熱部は、前記実装基板に設けられた凹部に金属が埋め込まれた構造を有することを特徴とする電子部品モジュール実装体。 - 請求項9〜11のいずれか1つにおいて、
前記放熱部は、前記実装基板を貫通する放熱ビア上に設けられていることを特徴とする電子部品モジュール実装体。 - 基板と、前記基板の第一面に設けられた複数の外部端子と、前記第一面における前記複数の外部端子に囲まれた領域に設けられた半導体チップとを備える電子部品モジュールが実装基板に実装された電子部品モジュール実装体において、
前記実装基板の第一面には、前記電子部品モジュールとの電気的接続を行う端子実装ランドと、前記電子部品モジュールに搭載された前記半導体チップの熱を放熱するための放熱部とが設けられ、
前記放熱部の先端の、前記端子実装ランドから前記実装基板の前記第一面の法線の向きに突出した量の方が、
前記外部端子の先端の、前記半導体チップから前記基板の前記第一面の法線の向きに突出した量よりも大きいことを特徴とする電子部品モジュール実装体。
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