JP6096442B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP6096442B2 JP6096442B2 JP2012198529A JP2012198529A JP6096442B2 JP 6096442 B2 JP6096442 B2 JP 6096442B2 JP 2012198529 A JP2012198529 A JP 2012198529A JP 2012198529 A JP2012198529 A JP 2012198529A JP 6096442 B2 JP6096442 B2 JP 6096442B2
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- metal film
- semiconductor wafer
- main surface
- plating
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- 239000004065 semiconductor Substances 0.000 title claims description 155
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 238000007747 plating Methods 0.000 claims description 117
- 238000000034 method Methods 0.000 claims description 60
- 229910052751 metal Inorganic materials 0.000 claims description 51
- 239000002184 metal Substances 0.000 claims description 51
- 239000010931 gold Substances 0.000 claims description 29
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 23
- 230000002093 peripheral effect Effects 0.000 claims description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 239000011521 glass Substances 0.000 claims description 15
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 114
- 239000010410 layer Substances 0.000 description 100
- 238000009792 diffusion process Methods 0.000 description 8
- 238000007772 electroless plating Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 239000003550 marker Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 239000003638 chemical reducing agent Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- KWSLGOVYXMQPPX-UHFFFAOYSA-N 5-[3-(trifluoromethyl)phenyl]-2h-tetrazole Chemical compound FC(F)(F)C1=CC=CC(C2=NNN=N2)=C1 KWSLGOVYXMQPPX-UHFFFAOYSA-N 0.000 description 1
- JAJIPIAHCFBEPI-UHFFFAOYSA-N 9,10-dioxoanthracene-1-sulfonic acid Chemical compound O=C1C2=CC=CC=C2C(=O)C2=C1C=CC=C2S(=O)(=O)O JAJIPIAHCFBEPI-UHFFFAOYSA-N 0.000 description 1
- 241000080590 Niso Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 150000002815 nickel Chemical class 0.000 description 1
- LGQLOGILCSXPEA-UHFFFAOYSA-L nickel sulfate Chemical compound [Ni+2].[O-]S([O-])(=O)=O LGQLOGILCSXPEA-UHFFFAOYSA-L 0.000 description 1
- 229910000363 nickel(II) sulfate Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- -1 potassium tetrahydroborate Chemical compound 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910001379 sodium hypophosphite Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Dicing (AREA)
Description
12 素子形成領域
20 ダイシングライン
30 めっきシード層(第1の金属膜)
50 めっき層(第2の金属膜)
P1 第1の主面
P2 第2の主面
Claims (8)
- 半導体ウエハの第1の主面の想定されたダイシングラインに囲まれた複数の素子領域の各々に半導体素子を形成する素子工程と、
前記半導体ウエハの前記第1の主面とは反対側の第2の主面の外周部が内周部よりも厚くなるように前記第2の主面を研削する研削工程と、
前記研削工程において研削された前記第2の主面に前記ダイシングラインに対応する部分を露出する第1の開口部を備えた第1の金属膜を形成する第1の金属膜形成工程と、
前記ダイシングラインに対応する部分を露出する第2の開口部を備えると共に前記第1の金属膜を被覆する第2の金属膜を形成する第2の金属膜形成工程と、
前記ダイシングライン上における前記第1の金属膜および前記第2の金属膜の非形成部に沿って前記半導体ウエハを前記第2の主面側から切断する切断工程と、
を含む半導体装置の製造方法。 - 前記第1の金属膜形成工程は、
前記半導体ウエハの前記第2の主面に前記第1の金属膜を形成する工程と、
前記第1の金属膜の前記ダイシングラインと重なる部分を除去する工程と、
を含む請求項1に記載の製造方法。 - 前記第1の金属膜の前記ダイシングラインと重なる部分を除去する工程は、
前記第1の金属膜上に前記ダイシングラインに沿った開口部を有するレジストマスクを形成する工程と、
前記第1の金属膜を前記レジストマスクを介してエッチングする工程と、
を含む請求項2に記載の製造方法。 - 前記レジストマスクは、前記半導体ウエハの前記第1の主面に形成されたアライメントマークに基づいてアライメントされたガラスマスクを用いて露光処理されて前記開口部が形成される請求項3に記載の製造方法。
- 前記第2の金属膜形成工程は、前記第1の金属膜をめっきシード層として機能させ、前記第2の金属膜を前記第1の金属膜上にめっき処理によって形成する請求項1乃至4のいずれか1項に記載の製造方法。
- 前記第1の金属膜は、前記第2の金属膜よりもイオン化傾向の大きい金属により構成される請求項5に記載の製造方法。
- 前記第1の金属膜はアルミニウムを含み、前記第2の金属膜は金を含む請求項6に記載の製造方法。
- 前記第2の金属膜は、ニッケルめっき層および金めっき層を含む請求項7に記載の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012198529A JP6096442B2 (ja) | 2012-09-10 | 2012-09-10 | 半導体装置および半導体装置の製造方法 |
US14/018,518 US8945988B2 (en) | 2012-09-10 | 2013-09-05 | Method for thinning, metalizing, and dicing a semiconductor wafer and, semiconductor device made using the method |
CN201310408666.6A CN103681238B (zh) | 2012-09-10 | 2013-09-10 | 半导体装置及半导体装置的制造方法 |
US14/580,341 US9564401B2 (en) | 2012-09-10 | 2014-12-23 | Method for thinning, metalizing, and dicing a semiconductor wafer, and semiconductor device made using the method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2012198529A JP6096442B2 (ja) | 2012-09-10 | 2012-09-10 | 半導体装置および半導体装置の製造方法 |
Publications (2)
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JP2014053549A JP2014053549A (ja) | 2014-03-20 |
JP6096442B2 true JP6096442B2 (ja) | 2017-03-15 |
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Country Status (3)
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US (2) | US8945988B2 (ja) |
JP (1) | JP6096442B2 (ja) |
CN (1) | CN103681238B (ja) |
Families Citing this family (9)
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JP6296899B2 (ja) * | 2014-05-26 | 2018-03-20 | 三菱電機株式会社 | レジスト除去装置及びレジスト除去方法 |
CN107533963A (zh) * | 2015-04-20 | 2018-01-02 | 三菱电机株式会社 | 半导体装置的制造方法 |
FR3085575B1 (fr) | 2018-09-03 | 2021-06-18 | St Microelectronics Tours Sas | Boitier de puce electronique |
US10964596B2 (en) * | 2019-01-25 | 2021-03-30 | Semiconductor Components Industries, Llc | Backside metal patterning die singulation system and related methods |
FR3093230B1 (fr) | 2019-02-27 | 2023-01-06 | St Microelectronics Tours Sas | Boîtier de puce électronique |
US10727216B1 (en) | 2019-05-10 | 2020-07-28 | Sandisk Technologies Llc | Method for removing a bulk substrate from a bonded assembly of wafers |
JP2022050231A (ja) * | 2020-09-17 | 2022-03-30 | 株式会社東芝 | 半導体装置の製造方法 |
JP7346374B2 (ja) * | 2020-09-23 | 2023-09-19 | 株式会社東芝 | 半導体基板及び半導体装置の製造方法 |
US20230282502A1 (en) * | 2022-03-03 | 2023-09-07 | Micron Technology, Inc. | Wafer carrier with reticle template for marking reticle fields on a semiconductor wafer |
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JPH05166926A (ja) * | 1991-12-12 | 1993-07-02 | Hitachi Ltd | 半導体基板ダイシング法 |
JPH10154670A (ja) * | 1996-11-26 | 1998-06-09 | Toshiba Corp | 半導体装置の製造方法 |
JP2003059860A (ja) * | 2001-08-13 | 2003-02-28 | Mitsubishi Electric Corp | 半導体装置 |
JP2004165312A (ja) * | 2002-11-12 | 2004-06-10 | Sanyo Electric Co Ltd | 半導体集積装置及びその製造方法 |
JP4753170B2 (ja) * | 2004-03-05 | 2011-08-24 | 三洋電機株式会社 | 半導体装置及びその製造方法 |
JP4749849B2 (ja) | 2005-11-28 | 2011-08-17 | 株式会社ディスコ | ウェーハの分割方法 |
JP2008098529A (ja) * | 2006-10-13 | 2008-04-24 | Toshiba Corp | 半導体装置及びその製造方法 |
JP5168920B2 (ja) * | 2007-01-31 | 2013-03-27 | 富士電機株式会社 | 半導体装置の製造方法およびマーキング装置 |
US20080242052A1 (en) * | 2007-03-30 | 2008-10-02 | Tao Feng | Method of forming ultra thin chips of power devices |
US8456002B2 (en) * | 2007-12-14 | 2013-06-04 | Stats Chippac Ltd. | Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief |
TWI443789B (zh) * | 2008-07-04 | 2014-07-01 | Unimicron Technology Corp | 嵌埋有半導體晶片之電路板及其製法 |
JP5356890B2 (ja) * | 2009-04-02 | 2013-12-04 | 株式会社ディスコ | ウェーハの加工方法 |
US8785296B2 (en) * | 2012-02-14 | 2014-07-22 | Alpha & Omega Semiconductor, Inc. | Packaging method with backside wafer dicing |
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2012
- 2012-09-10 JP JP2012198529A patent/JP6096442B2/ja active Active
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2013
- 2013-09-05 US US14/018,518 patent/US8945988B2/en active Active
- 2013-09-10 CN CN201310408666.6A patent/CN103681238B/zh active Active
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2014
- 2014-12-23 US US14/580,341 patent/US9564401B2/en active Active
Also Published As
Publication number | Publication date |
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US8945988B2 (en) | 2015-02-03 |
CN103681238B (zh) | 2018-03-23 |
JP2014053549A (ja) | 2014-03-20 |
US9564401B2 (en) | 2017-02-07 |
US20150108612A1 (en) | 2015-04-23 |
CN103681238A (zh) | 2014-03-26 |
US20140070374A1 (en) | 2014-03-13 |
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