JP6045243B2 - 積層半導体基板、半導体基板および積層チップパッケージ並びにこれらの製造方法 - Google Patents
積層半導体基板、半導体基板および積層チップパッケージ並びにこれらの製造方法 Download PDFInfo
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- JP6045243B2 JP6045243B2 JP2012171731A JP2012171731A JP6045243B2 JP 6045243 B2 JP6045243 B2 JP 6045243B2 JP 2012171731 A JP2012171731 A JP 2012171731A JP 2012171731 A JP2012171731 A JP 2012171731A JP 6045243 B2 JP6045243 B2 JP 6045243B2
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Description
そして、積層チップパッケージに関する技術として、従来、例えば特許文献1に開示された技術、特許文献2に開示された技術が知られている。
(1)半導体装置が形成されている処理前基板について、スクライブラインに沿った複数のスクライブ溝部を形成することによって、複数のスクライブ溝部のいずれか少なくとも1つに接し、かつ半導体装置が形成されている複数のデバイス領域を形成するデバイス領域形成工程
(2)その複数のデバイス領域のそれぞれに形成されている半導体装置に接続され、かつデバイス領域からスクライブ溝部の内側に延出する複数の配線電極を、複数のデバイス領域それぞれについて、その各デバイス領域とスクライブ溝部との境目に相当する4つの境界辺の一部だけに沿った部分配置パターンで、かつスクライブ溝部に、そのスクライブ溝部を挟んで隣り合う2つのデバイス領域のうちのいずれか一方だけから延出させて形成することによって、電極付き基板を製造する基板製造工程
(3)電極付き基板を複数積層して積層ウェハを製造する積層工程
(4)積層ウェハについて、複数の電極付き基板が積層されている積層方向に重なった複数の電極付き基板のスクライブ溝部を貫通し、かつ配線電極のうちの積層方向に重なった積層電極群を構成している複数の配線電極が出現するようにして貫通孔を形成する貫通孔形成工程
(5)貫通孔に出現しているすべての配線電極に接する貫通電極を貫通孔を通って複数の電極付き基板をすべて貫通するように形成する貫通電極形成工程
第1の実施の形態
(積層半導体ウェハ100の構造)
まず、図1〜図5を参照して積層半導体ウェハ100の構造について説明する。積層半導体ウェハ100は、半導体ウェハ1を用いて製造される。積層半導体ウェハ100は、本発明の第1の実施の形態に係る積層半導体基板であって、半導体ウェハ1が複数積層されている。図1に示されている積層半導体ウェハ100では、8枚の半導体ウェハ1が積層されている。本発明の実施の形態に係る積層半導体基板では、複数の半導体基板が積層されていればよいため、半導体ウェハ1の積層数は8枚には限定されない。
以上のように、積層半導体ウェハ100では、複数の配線電極15が各デバイス領域10の周囲に部分配置パターンで配置されている。そのため、各デバイス領域10において、その周囲に配線電極15が配置される部分と、配線電極15が配置されない部分とが存在している。また、すべての溝部20,21のうちの、2つのデバイス領域10に挟まれるすべての部分において、配線電極15が片側延出構造で形成されている。そのため、積層半導体ウェハ100(半導体ウェハ1も同様)では、溝部20や溝部21の内側に、配線電極15を幅方向に沿って2つ横並びで配置し得るだけのスペースを確保する必要がない。そのため、2つの配線電極15が幅方向に沿って横並びで配置される場合に比べて溝部20、溝部21の幅を狭めることができる。
続いて以上のような構成を有する積層半導体ウェハ100の製造方法について、前述した図1〜図5、図21〜図23に加えて、図11〜図20を参照して説明する。ここで、図11は製造途中の積層半導体ウェハを示す図2と同様の平面図である。図12は図11の後続の積層半導体ウェハを示す図2と同様の平面図である。図13は図11の13−13線断面図である。図14は図12の14−14線断面図である。また、図15は図14の後続の積層半導体ウェハを示す図13と同様の断面図である。さらに、図16〜図20はそれぞれ順次後続の積層半導体ウェハを示す図12と同様の断面図である。
以上のような構成を有する積層半導体ウェハ100を用いることによって、積層チップパッケージ200を製造することができる。積層チップパッケージ200の構造について図6〜図9を参照して説明すると、次のとおりである。ここで、図6は積層チップパッケージ200の表側からみた斜視図、図7は同じく裏側からみた斜視図である。図8は積層チップパッケージ200の要部を示す一部省略した斜視図、図9は図6の9−9線断面図である。
続いて、積層チップパッケージの製造方法について説明する。以上のような構成を備えた積層チップパッケージ200は、前述した積層半導体ウェハ100を用いて製造することができる。この場合、積層半導体ウェハ100をダイシングソーを用いてスクライブライン3A,3Bに沿って切断すると、積層チップ領域40A,40B等の各積層チップ領域がブロック状に分割される。分割されたブロック状の各部分が積層チップパッケージ200となる。
半導体ウェハ1および積層半導体ウェハ110では、図31に示すように、有電極辺10X、10Xと、無電極辺10Y、10Yの位置を変更してもよい。このようにしても、前述した半導体ウェハ1および積層半導体ウェハ110のように、1枚の基板上に形成し得るデバイス領域10の個数を増やすことができる。
続いて、図30を参照して、本発明の第2の実施の形態に係る積層半導体ウェハ105について説明する。ここで、図30は第2の実施の形態に係る積層半導体ウェハ105における配線電極15の配置パターンを模式的に示す平面図である。
続いて、図32、図33を参照して、本発明の別の実施の形態に係る積層半導体ウェハ110について説明する。ここで、図32は積層半導体ウェハ110の2つのデバイス領域10の要部を示す平面図である。図33は製造途中の半導体ウェハ2の要部を示す斜視図である。
Claims (22)
- スクライブラインに沿った複数のスクライブ溝部が形成されている複数の半導体基板が積層されている積層半導体基板であって、
前記複数の半導体基板は、それぞれ
前記複数のスクライブ溝部のいずれか少なくとも1つに接し、かつ半導体装置が形成され、さらに矩形状に形成され、それぞれ絶縁されている複数のデバイス領域と、
該複数のデバイス領域のそれぞれに形成されている前記半導体装置に接続され、かつ前記デバイス領域から前記スクライブ溝部の内側に延出している複数の配線電極とを有し、
前記複数の配線電極が、前記複数のデバイス領域のそれぞれについて、該各デバイス領域と前記スクライブ溝部との境目に相当する4つの境界辺の一部だけに沿った部分配置パターンで配置され、かつ、前記複数のデバイス領域のうちの前記スクライブ溝部を挟んで隣り合う2つのデバイス領域のうちのいずれか一方だけから該スクライブ溝部に延出し、
前記積層半導体基板は、
前記複数の半導体基板が積層されている積層方向に重なった前記複数の半導体基板の前記スクライブ溝部を貫通し、かつ前記複数の配線電極のうちの前記積層方向に重なった積層電極群を構成している複数の前記配線電極が出現している貫通孔が形成され、
該貫通孔を通って前記複数の半導体基板をすべて貫通し、かつ前記貫通孔に出現しているすべての前記配線電極に接する貫通電極と、
前記複数の半導体基板すべてにおける前記積層方向に重なった前記デバイス領域から構成される複数の積層チップ領域とを有する積層半導体基板。 - 前記配線電極は、前記積層方向に沿った孔部が形成されている電極パッドを有し、
該電極パッドが前記境界辺との間に隙間を形成することなく前記スクライブ溝部に配置されている請求項1記載の積層半導体基板。 - 前記複数のスクライブ溝部が、横方向に形成された複数の横溝部と、該横溝部と直交する複数の縦溝部とが十字状に交差した格子状に形成され、
前記複数の横溝部および複数の縦溝部のすべてにおいて、該スクライブ溝部を挟んで隣り合う2つのデバイス領域のうちのいずれか一方だけから前記配線電極が延出している請求項1または2記載の積層半導体基板。 - 前記配線電極が前記デバイス領域から前記スクライブ溝部に延出する方向を延出方向としたときに、該延出方向および前記部分配置パターンが前記複数のデバイス領域すべてについて共通している請求項1〜3のいずれか一項記載の積層半導体基板。
- 前記部分配置パターンが、前記複数のデバイス領域のそれぞれにおける前記4つの境界辺のうちのL字状に接続された2本が前記配線電極の配置された有電極辺に設定され、該有電極辺以外の2本が前記配線電極の配置されない無電極辺に設定されているL字状パターンであり、該L字状パターンが前記複数のデバイス領域のすべてにおいて共通している請求項1〜4のいずれか一項記載の積層半導体基板。
- 前記積層半導体基板を前記スクライブ溝部で切断するときに用いられる切断部材の幅を切断幅とし、前記電極パッドの前記境界辺から張り出す幅をパッド幅としたときに、前記スクライブ溝部の幅が、前記切断幅と前記パッド幅とを加えた大きさ以下に設定されている請求項2記載の積層半導体基板。
- 前記配線電極は、前記積層方向に沿った孔部が形成されている電極パッドを有し、前記貫通孔が前記孔部に沿って形成されている請求項1〜6のいずれか一項記載の積層半導体基板。
- 前記電極パッドは、矩形状または両端部が前記スクライブ溝部の内側に向かって開くように配置されたU字状に形成されている請求項2記載の積層半導体基板。
- 前記半導体基板を4枚積層したユニット積層基板を1または2以上積層することによって、前記積層半導体基板が構成されている請求項1〜8のいずれか一項記載の積層半導体基板。
- スクライブラインに沿った複数のスクライブ溝部が形成されている半導体基板であって、
前記複数のスクライブ溝部のいずれか少なくとも1つに接し、かつ半導体装置が形成され、さらに矩形状に形成され、それぞれ絶縁されている複数のデバイス領域と、
該複数のデバイス領域のそれぞれに形成されている前記半導体装置に接続され、かつ前記デバイス領域から前記スクライブ溝部の内側に延出している複数の配線電極とを有し、
前記複数の配線電極が、前記複数のデバイス領域のそれぞれについて、該各デバイス領域と前記スクライブ溝部との境目に相当する4つの境界辺の一部だけに沿った部分配置パターンで配置され、かつ、前記複数のデバイス領域のうちの前記スクライブ溝部を挟んで隣り合う2つのデバイス領域のうちのいずれか一方だけから該スクライブ溝部に延出し、
前記配線電極は、前記半導体基板の厚さ方向に沿った孔部が形成されている電極パッドを有し、
該電極パッドが前記境界辺との間に隙間を形成することなく前記スクライブ溝部に配置されている半導体基板。 - スクライブラインに沿った複数のスクライブ溝部が形成されている半導体基板であって、
前記複数のスクライブ溝部のいずれか少なくとも1つに接し、かつ半導体装置が形成され、さらに矩形状に形成され、それぞれ絶縁されている複数のデバイス領域と、
該複数のデバイス領域のそれぞれに形成されている前記半導体装置に接続され、かつ前記デバイス領域から前記スクライブ溝部の内側に延出している複数の配線電極とを有し、
前記複数の配線電極が、前記複数のデバイス領域のそれぞれについて、該各デバイス領域と前記スクライブ溝部との境目に相当する4つの境界辺の一部だけに沿った部分配置パターンで配置され、かつ、前記複数のデバイス領域のうちの前記スクライブ溝部を挟んで隣り合う2つのデバイス領域のうちのいずれか一方だけから該スクライブ溝部に延出し、
前記複数のスクライブ溝部が、横方向に形成された複数の横溝部と、該横溝部と直交する複数の縦溝部とが十字状に交差した格子状に形成され、
前記複数の横溝部および複数の縦溝部のすべてにおいて、該スクライブ溝部を挟んで隣り合う2つのデバイス領域のうちのいずれか一方だけから前記配線電極が延出している半導体基板。 - 前記複数のスクライブ溝部が、横方向に形成された複数の横溝部と、該横溝部と直交する複数の縦溝部とが十字状に交差した格子状に形成され、
前記複数の横溝部および複数の縦溝部のすべてにおいて、該スクライブ溝部を挟んで隣り合う2つのデバイス領域のうちのいずれか一方だけから前記配線電極が延出している請求項10記載の半導体基板。 - 前記配線電極が前記デバイス領域から前記スクライブ溝部に延出する方向を延出方向としたときに、該延出方向および前記部分配置パターンが前記複数のデバイス領域すべてについて共通している請求項11または12記載の半導体基板。
- 前記部分配置パターンが、前記複数のデバイス領域のそれぞれにおける前記4つの境界辺のうちのL字状に接続された2本が前記配線電極の配置された有電極辺に設定され、該有電極辺以外の2本が前記配線電極の配置されない無電極辺に設定されているL字状パターンであり、該L字状パターンが前記複数のデバイス領域のすべてにおいて共通している請求項10〜13のいずれか一項記載の半導体基板。
- 前記半導体基板を前記スクライブ溝部で切断するときに用いられる切断部材の幅を切断幅とし、前記電極パッドの前記境界辺から張り出す幅をパッド幅としたときに、前記スクライブ溝部の幅が、前記切断幅と前記パッド幅とを加えた大きさ以下に設定されている請求項10記載の半導体基板。
- 半導体装置が形成されている複数の半導体チップが積層されている積層チップパッケージであって、
前記複数の半導体チップは、それぞれ
前記半導体装置が形成されている矩形状のデバイス領域の周囲を取り囲むように形成された絶縁性の樹脂からなる樹脂絶縁層と、
前記半導体装置に接続され、かつ前記樹脂絶縁層上に端部が配置されている複数の配線電極とを有し、
前記複数の配線電極が前記デバイス領域と前記樹脂絶縁層との境目に相当する4つの境界辺の一部だけに沿った部分配置パターンで配置され、かつ、前記デバイス領域における前記4つの境界辺のうちのL字状に接続された2本が前記配線電極の配置された有電極辺に設定され、該有電極辺以外の2本が前記配線電極の配置されない無電極辺に設定され、
前記積層チップパッケージは、
前記複数の半導体チップが積層されている積層方向に重なった前記複数の半導体チップの前記樹脂絶縁層を貫通し、かつ前記配線電極のうちの前記積層方向に重なった積層電極群を構成している複数の前記配線電極が出現している貫通孔が形成され、
該貫通孔を通って前記複数の半導体チップをすべて貫通し、かつ前記貫通孔に出現しているすべての前記配線電極に接する貫通電極を有する積層チップパッケージ。 - 前記配線電極は、前記樹脂絶縁層上に配置され、かつ前記積層方向に沿った孔部が形成されている電極パッドを有し、
該電極パッドが前記境界辺との間に隙間を形成することなく前記樹脂絶縁層上に配置されている請求項16記載の積層チップパッケージ。 - 半導体装置が形成されている処理前基板について、スクライブラインに沿った複数のスクライブ溝部を形成することによって、前記複数のスクライブ溝部のいずれか少なくとも1つに接し、かつ半導体装置が形成されている複数のデバイス領域を形成するデバイス領域形成工程と、
該複数のデバイス領域のそれぞれに形成されている前記半導体装置に接続され、かつ前記デバイス領域から前記スクライブ溝部の内側に延出する複数の配線電極を、前記複数のデバイス領域それぞれについて、該各デバイス領域と前記スクライブ溝部との境目に相当する4つの境界辺の一部だけに沿った部分配置パターンで、かつ前記スクライブ溝部に、該スクライブ溝部を挟んで隣り合う2つのデバイス領域のうちのいずれか一方だけから延出させて形成することによって、電極付き基板を製造する基板製造工程と、
前記電極付き基板を複数積層して積層ウェハを製造する積層工程と、
前記積層ウェハについて、複数の前記電極付き基板が積層されている積層方向に重なった複数の前記電極付き基板の前記スクライブ溝部を貫通し、かつ前記配線電極のうちの前記積層方向に重なった積層電極群を構成している複数の前記配線電極が出現するようにして貫通孔を形成する貫通孔形成工程と、
前記貫通孔に出現しているすべての前記配線電極に接する貫通電極を前記貫通孔を通って複数の前記電極付き基板をすべて貫通するように形成する貫通電極形成工程とを有する積層半導体基板の製造方法。 - 前記基板製造工程において、前記積層方向に沿った孔部が形成されている電極パッドを有する形状で前記配線電極を形成し、かつ前記電極パッドを前記境界辺との間に隙間を形成することなく前記スクライブ溝部に配置する請求項18記載の積層半導体基板の製造方法。
- 前記基板製造工程において、前記デバイス領域における前記4つの境界辺のうちのL字状に接続された2本を前記配線電極の配置された有電極辺に設定し、該有電極辺以外の2本を前記配線電極の配置されない無電極辺に設定する請求項18または19記載の積層半導体基板の製造方法。
- 前記デバイス領域形成工程において、前記積層半導体基板を前記スクライブ溝部で切断するときに用いられる切断部材の幅を切断幅とし、前記電極パッドの前記境界辺から張り出す幅をパッド幅としたときに、前記スクライブ溝部の幅を前記切断幅と前記パッド幅とを加えた大きさ以下に設定する請求項19記載の積層半導体基板の製造方法。
- 請求項18記載の製造方法によって製造された積層半導体基板をそれぞれの前記スクライブ溝部に沿って切断し、その切断面に絶縁性の樹脂からなる樹脂絶縁層を出現させて積層チップパッケージを製造する積層チップパッケージの製造方法。
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