JP5839267B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5839267B2 JP5839267B2 JP2011212873A JP2011212873A JP5839267B2 JP 5839267 B2 JP5839267 B2 JP 5839267B2 JP 2011212873 A JP2011212873 A JP 2011212873A JP 2011212873 A JP2011212873 A JP 2011212873A JP 5839267 B2 JP5839267 B2 JP 5839267B2
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- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemically Coating (AREA)
Description
11 電極
12 下地層
16 Ni層
16a 第1領域
16b 第2領域
18 カバー層
20 半田ボール
22 凹部
Claims (4)
- 基板上に下地層を設ける工程と、
無電解メッキ法により前記下地層上にニッケル層を設ける工程と、
前記ニッケル層上に半田ボールを設ける工程と、を有し、
前記ニッケル層の前記半田ボール側の領域である第2領域は、前記ニッケル層の前記下地層側の領域である第1領域に比べて硬く、
前記ニッケル層を設ける工程は、前記ニッケル層の上面を熱処理する工程を含むことを特徴とする半導体装置の製造方法。 - 前記ニッケル層を設ける工程におけるメッキ液中のリン濃度を変化させることを特徴とする請求項1記載の半導体装置の製造方法。
- 基板上に下地層を設ける工程と、
無電解メッキ法により前記下地層上にニッケル層を設ける工程と、
前記ニッケル層上に半田ボールを設ける工程と、を有し、
前記ニッケル層の前記半田ボール側の領域である第2領域は、前記ニッケル層の前記下地層側の領域である第1領域に比べて硬く、
前記ニッケル層を設ける工程において、無電解メッキ法に用いるメッキ液の温度は低温から高温に連続的に変化し、
前記第1領域を形成するためのメッキ液の温度は低く、前記第2領域を形成するためのメッキ液の温度は高いことを特徴とする半導体装置の製造方法。 - 前記ニッケル層の表面に凹凸を形成する工程と、
前記ニッケル層上にカバー層を形成する工程と、をさらに有し、
前記カバー層の表面には、前記ニッケル層の凹凸を反映した凹凸が設けられることを特徴とする請求項1から3いずれか一項記載の半導体装置の製造方法。
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JP2011212873A JP5839267B2 (ja) | 2011-09-28 | 2011-09-28 | 半導体装置の製造方法 |
US13/630,171 US8846520B2 (en) | 2011-09-28 | 2012-09-28 | Semiconductor device and method for manufacturing semiconductor device |
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CN106764558A (zh) * | 2016-12-07 | 2017-05-31 | 东莞中之光电股份有限公司 | 一种csp照明闪光模组生产工艺 |
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US8941123B2 (en) | 2013-05-30 | 2015-01-27 | International Business Machines Corporation | Local interconnects by metal-III-V alloy wiring in semi-insulating III-V substrates |
US9437574B2 (en) | 2013-09-30 | 2016-09-06 | Freescale Semiconductor, Inc. | Electronic component package and method for forming same |
US9515034B2 (en) * | 2014-01-03 | 2016-12-06 | Freescale Semiconductor, Inc. | Bond pad having a trench and method for forming |
KR20160037314A (ko) * | 2014-09-26 | 2016-04-06 | 삼성디스플레이 주식회사 | 박막 트랜지스터 기판 및 이의 제조 방법 |
US10115703B2 (en) | 2015-03-17 | 2018-10-30 | Toshiba Memory Corporation | Semiconductor device and manufacturing method thereof |
JP7140822B2 (ja) * | 2018-03-09 | 2022-09-21 | 株式会社カネカ | 配線回路、その製造方法 |
DE102019109200B4 (de) * | 2019-04-08 | 2024-03-07 | Infineon Technologies Ag | Halbleitervorrichtungen mit nicht-galvanischer verbindung |
IT202000001822A1 (it) | 2020-01-30 | 2021-07-30 | St Microelectronics Srl | Circuito integrato e dispositivo elettronico comprendente una pluralita' di circuiti integrati accoppiati elettricamente tramite un segnale di sincronizzazione instradato attraverso il circuito integrato |
IT202000001819A1 (it) * | 2020-01-30 | 2021-07-30 | St Microelectronics Srl | Circuito integrato e dispositivo elettronico comprendente una pluralita' di circuiti integrati accoppiati elettricamente tramite un segnale di sincronizzazione |
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JP3148202B2 (ja) | 1999-06-11 | 2001-03-19 | 株式会社フジクラ | 半導体パッケージ及びその製造方法 |
JP4822694B2 (ja) * | 2004-11-22 | 2011-11-24 | 京セラ株式会社 | 半導体素子及び半導体素子実装基板 |
JP5172577B2 (ja) * | 2008-09-30 | 2013-03-27 | 新日本無線株式会社 | 半導体装置の製造方法 |
JP2011165862A (ja) * | 2010-02-09 | 2011-08-25 | Sony Corp | 半導体装置、チップ・オン・チップの実装構造、半導体装置の製造方法及びチップ・オン・チップの実装構造の形成方法 |
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