JP5733417B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP5733417B2 JP5733417B2 JP2013544320A JP2013544320A JP5733417B2 JP 5733417 B2 JP5733417 B2 JP 5733417B2 JP 2013544320 A JP2013544320 A JP 2013544320A JP 2013544320 A JP2013544320 A JP 2013544320A JP 5733417 B2 JP5733417 B2 JP 5733417B2
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Description
y=−0.0047r4+0.0528r3−0.2211r2+0.9923r+5.0474 ・・・(2)
本発明にかかる半導体装置の構成について説明する。図1は、本発明にかかる半導体装置の構成を示す概略断面図である。図1に示す本発明にかかる半導体装置は、プロトン照射に由来して形成されたドナー層3からなるBB層を備えたpinダイオード10である。詳細には、ドナー層3は、シリコン半導体基板(n-型半導体基板)1からなるn型ドリフト層2の中央付近の深さに設けられている。ドナー層3を形成するにあたって、シリコン半導体基板1からなるn型ドリフト層2に、まず本発明にかかるプロトン照射により結晶欠陥を形成する。後述する実施例1ではプロトンのドーズ量を1×1012(atoms/cm2)、加速エネルギーを8MeVとした(以下、本実施例条件でのプロトン照射条件とする)。そして、プロトン照射後、熱処理することにより結晶欠陥をドナー化し、このドナー化により形成されるドナー層3をFS層とすることにより、本発明にかかるpinダイオード10とする。
次に、本実施例条件でのアニール、アニール無しおよび500℃以上の高温条件でのアニールにおいて、DLTS信号ピーク強度とアニール温度との関係、およびドナー化ピーク濃度とアニール温度との関係について説明する。図3は、実施例1にかかる半導体装置のプロトン照射後のDLTSスペクトル波形を示す特性図である。図4は、実施例1にかかる半導体装置のプロトン照射後のアニール温度とDLTS信号ピーク強度との関係を示す特性図である。図5は、実施例1にかかる半導体装置のプロトン照射後のアニール温度とドナー化ピーク濃度との関係を示す特性図である。
(a)VOH複合欠陥のDLTS信号強度(すなわちトラップ準位密度)が最も高いこと、
(b)VOH複合欠陥およびVO複合欠陥は、VV+VP複合欠陥よりもDLTS信号強度(トラップ準位密度)が高いこと、好ましくはそれぞれVV+VP複合欠陥の2倍以上であること、
(c)VOH複合欠陥、VO複合欠陥、VV+VP複合欠陥のDLTS信号強度の比は、VO複合欠陥をパラメータとしてみた場合、VOH:VO:VV+VPが2:1:1と2:2:1およびこれらの間の比(例えば2:1.2:1、2:1.5:1、2:1.8:1)にあること、
以上の3点の特徴を有することが好ましい。
次に、本発明にかかる半導体装置の製造方法について詳細に説明する。ここでは、図1に示した耐圧1200Vクラスのpinダイオードを製造する場合を例に説明する。シリコン半導体基板として、比抵抗が90Ωcm(リン濃度5.0×1013atoms/cm3)のFZ−n型シリコン半導体基板1(以降、ウェハ1)を用意する。このウェハ1の両主面から、窒素および酸素雰囲気下で、1250℃の温度で100時間の熱処理を行ってリンを80μm程度の深さに熱拡散させる。これによりウェハ1の内部に形成されたリン拡散層の表面不純物濃度は、例えば1.0×1020atoms/cm3程度である。この熱処理によって、ウェハ1の両面からウェハ内に大量の酸素が導入され、ウェハ1における酸素濃度は、固溶限界濃度(約1×1018atoms/cm3)となる。次に、ウェハ1の一方の主面を研削してリン拡散層を除去した後、ウェハ1の両主面に鏡面加工を施す。
次に、DLTS信号ピーク強度とプロトンドーズ量との関係について説明する。図11は、実施例2にかかる半導体装置のプロトン照射後のDLTSスペクトル波形を示す特性図である。図11では、プロトンのドーズ量が、1×1011/cm2および1×1012/cm2の場合について各欠陥のDLTS信号ピーク強度を比較している。図11に示すピークは、図3,9と同様に温度が低い方のピークから順に、VO複合欠陥、VOH複合欠陥、VV+VP複合欠陥を示している。実施例2では、プロトン照射後のアニールの温度は350℃である。実施例2のプロトンドーズ量以外の構成は、実施例1と同様である。図11に示す結果より、ドーズ量が低い1×1011/cm2の場合、ドーズ量が1×1012/cm2の場合と比べてVOH複合欠陥のDLTS信号ピーク強度が1/5以下に低下していることが確認された。このようにVOH複合欠陥のDLTS信号強度(欠陥密度、トラップ密度)が相対的に低くなると、FS層のピーク濃度が低くなるため、好ましくない。
図14は、本発明にかかる半導体装置の別の一例の構成を示す説明図である。図14に示す本発明にかかる半導体装置は、n-ドリフト層21の内部にn型ブロードバッファ(BB)領域を設けたBB層構造のIGBTである。図14には、上側にブロードバッファ(BB)型IGBTの断面構造を示し、下側にブロードバッファ(BB)型IGBTのネットドーピング濃度分布を示す。図14下側のネットドーピング濃度分布において、横軸はエミッタ電極24と、n-ドリフト層21となるn-型半導体基板のおもて面との界面からの深さであり、縦軸は極性が異なるn型ドナーおよびp型アクセプタの正味のドーピングであるネットドーピング濃度である。
2 n型ドリフト層
3 ドナー層
4 アノード領域
5 カソード領域
6 ガードリング
7 BB層
8 アノード電極
9 カソード電極
10 pinダイオード
11 フィールドプレート
Claims (24)
- 第1導電型不純物を有する半導体基板からなる第1導電型ドリフト層と、
前記第1導電型ドリフト層の一方の主面側に設けられた第2導電型半導体領域と、
プロトン照射により前記第1導電型ドリフト層の内部に形成された結晶欠陥がドナー化されてなる、前記第1導電型ドリフト層の深さ方向に異なる深さで設けられた複数のドナー層と、
を備え、
前記ドナー層は、不純物濃度が極大となる第1箇所と、前記第1箇所から前記第1導電型ドリフト層の両主面側に向かって低下する濃度勾配をもつ第2箇所とからなる不純物濃度分布を有し、
前記結晶欠陥は、空孔、酸素原子および水素原子に起因する第1複合欠陥と、複空孔、空孔および前記第1導電型不純物に起因する第2複合欠陥と、空孔および酸素原子に起因する第3複合欠陥とを含み、
深準位過渡分光法により測定された前記第1複合欠陥の信号強度が、深準位過渡分光法により測定された前記第2複合欠陥の信号強度よりも高く、
オフ時に前記第1導電型ドリフト層と前記第2導電型半導体領域とのpn接合から広がる空乏層の端部の、前記pn接合からの距離を示す距離指標を下記(1)式とし、前記第1導電型ドリフト層の厚さをW0としたときに、
複数の前記ドナー層のうち、前記空乏層が最初に到達する前記ドナー層の濃度がピークとなる位置の、前記第1導電型ドリフト層の他方の主面からの距離Xは、W0−1.5L≦X≦W0−0.8Lを満たすことを特徴とする半導体装置。
- 深準位過渡分光法により測定された前記第1複合欠陥の信号強度が、深準位過渡分光法により測定された前記第2複合欠陥の信号強度の2倍よりも高いことを特徴とする請求項1に記載の半導体装置。
- 深準位過渡分光法により測定された前記第3複合欠陥の信号強度が、深準位過渡分光法により測定された前記第2複合欠陥の信号強度よりも高く、かつ深準位過渡分光法により測定された前記第1複合欠陥の信号強度よりも低いことを特徴とする請求項1に記載の半導体装置。
- 深準位過渡分光法により測定された前記第1複合欠陥の信号強度が、深準位過渡分光法により測定された前記第3複合欠陥の信号強度の2倍よりも高いことを特徴とする請求項3に記載の半導体装置。
- 前記第1複合欠陥のトラップ準位密度が、前記第2複合欠陥のトラップ準位密度よりも高いことを特徴とする請求項1に記載の半導体装置。
- 前記第1複合欠陥のトラップ準位密度が、前記第2複合欠陥のトラップ準位密度の2倍よりも高いことを特徴とする請求項5に記載の半導体装置。
- 前記第3複合欠陥のトラップ準位密度が、前記第2複合欠陥のトラップ準位密度よりも高く、かつ前記第1複合欠陥のトラップ準位密度よりも低いことを特徴とする請求項5に記載の半導体装置。
- 前記第1複合欠陥のトラップ準位密度が、前記第3複合欠陥のトラップ準位密度の2倍よりも高いことを特徴とする請求項7に記載の半導体装置。
- 前記第1導電型ドリフト層を挟んで対向する、前記第1導電型ドリフト層よりも低抵抗な第1導電型半導体領域および前記第2導電型半導体領域を備えたpinダイオードであることを特徴とする請求項1〜8のいずれか一つに記載の半導体装置。
- 前記第1導電型ドリフト層の一方の主面側に金属−酸化膜−半導体からなる絶縁ゲート構造を備えた絶縁ゲート型バイポーラトランジスタであることを特徴とする請求項1〜8のいずれか一つに記載の半導体装置。
- 前記距離Xは、W0−1.4L≦X≦W0−0.9Lを満たすことを特徴とする請求項1〜10のいずれか一つに記載の半導体装置。
- 前記距離Xは、W0−1.3L≦X≦W0−1.0Lを満たすことを特徴とする請求項11に記載の半導体装置。
- 第1導電型不純物を有する半導体基板からなる第1導電型ドリフト層と、前記第1導電型ドリフト層の一方の主面側に設けられた第2導電型半導体領域と、プロトン照射により前記第1導電型ドリフト層の内部に形成された結晶欠陥がドナー化されてなる、前記第1導電型ドリフト層の深さ方向に異なる深さで設けられた複数のドナー層と、を備え、前記ドナー層は、不純物濃度が極大となる第1箇所と、前記第1箇所から前記第1導電型ドリフト層の両表面側に向かって低下する濃度勾配をもつ第2箇所とからなる不純物濃度分布を有する半導体装置の製造方法であって、
前記第1導電型ドリフト層となる第1導電型半導体基板にプロトン照射を行い、前記第1導電型半導体基板の内部に結晶欠陥を形成する工程と、
300℃以上450℃以下の温度で1分間以上300分間以下の熱処理により、前記結晶欠陥をドナー化する工程と、
を含み、
オフ時に前記第1導電型ドリフト層と前記第2導電型半導体領域とのpn接合から広がる空乏層の端部の、前記pn接合からの距離を示す距離指標を下記(2)式とし、前記第1導電型ドリフト層の厚さをW0としたときに、
複数の前記ドナー層のうち、前記空乏層が最初に到達する前記ドナー層の濃度がピークとなる位置の、前記第1導電型ドリフト層の他方の主面からの距離Xが前記第1導電型ドリフト層の他方の主面からW0−1.5L≦X≦W0−0.8Lを満たす深さとなる加速エネルギーで前記プロトン照射を行うことを特徴とする半導体装置の製造方法。
- 前記熱処理の温度が350℃よりも高いことを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記プロトン照射のプロトンのドーズ量が7.0×10 11 atoms/cm 2 以上5.0×10 13 atoms/cm 2 以下であり、
前記熱処理の温度が400℃以下であることを特徴とする請求項14に記載の半導体装置の製造方法。 - 前記プロトン照射のプロトンのドーズ量が7.0×10 11 atoms/cm 2 以上2.5×10 13 atoms/cm 2 以下であることを特徴とする請求項15に記載の半導体装置の製造方法。
- 前記プロトン照射のプロトンのドーズ量が1.0×10 12 atoms/cm 2 以上1.0×10 13 atoms/cm 2 以下であることを特徴とする請求項16に記載の半導体装置の製造方法。
- 前記プロトン照射のプロトンのドーズ量が5.0×10 11 atoms/cm 2 以上5.0×10 14 atoms/cm 2 以下であり、前記熱処理の温度が380℃以上450℃以下であることを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記プロトン照射のプロトンのドーズ量が7.0×10 11 atoms/cm 2 以上3.0×10 14 atoms/cm 2 以下であることを特徴とする請求項18に記載の半導体装置の製造方法。
- 前記プロトン照射のプロトンのドーズ量が1.0×10 12 atoms/cm 2 以上3.0×10 14 atoms/cm 2 以下であることを特徴とする請求項19に記載の半導体装置の製造方法。
- 前記プロトン照射のプロトンのドーズ量が3.0×10 12 atoms/cm 2 以上3.0×10 14 atoms/cm 2 以下であることを特徴とする請求項20に記載の半導体装置の製造方法。
- 前記プロトン照射のプロトンのドーズ量が1.0×10 13 atoms/cm 2 以上1.0×10 14 atoms/cm 2 以下であることを特徴とする請求項21に記載の半導体装置の製造方法。
- 前記熱処理の温度が390℃以上420℃以下であることを特徴とする請求項18〜22のいずれか一つに記載の半導体装置の製造方法。
- 前記プロトン照射により飛程Rpの前記ドナー層を形成するときのプロトンの加速エネルギーEは、前記プロトンの飛程Rpの対数log(Rp)をr、前記プロトンの加速エネルギーEの対数log(E)をyとして、下記式(3)を満たすことを特徴とする請求項13〜23のいずれか一つに記載の半導体装置の製造方法。
y=−0.0047r 4 +0.0528r 3 −0.2211r 2 +0.9923r+5.0474 ・・・(3)
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