JP5605705B2 - 縦型電界効果トランジスタ - Google Patents
縦型電界効果トランジスタ Download PDFInfo
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- JP5605705B2 JP5605705B2 JP2010510140A JP2010510140A JP5605705B2 JP 5605705 B2 JP5605705 B2 JP 5605705B2 JP 2010510140 A JP2010510140 A JP 2010510140A JP 2010510140 A JP2010510140 A JP 2010510140A JP 5605705 B2 JP5605705 B2 JP 5605705B2
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- electrode
- effect transistor
- field effect
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- semiconductor
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- H—ELECTRICITY
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/491—Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
図1Aは、実施の形態1における縦型電界効果トランジスタの断面図、図1Bは、図1AにおけるA1−A1線に沿った断面で示した平面図である。なお、図1Aは、図1BにおけるA2−A2線に沿った断面を示す。
図2Aは、実施の形態2における縦型電界効果トランジスタの断面図、図2Bは、図2AにおけるB1−B1線に沿った断面で示した平面図である。なお、図2Aは、図2BにおけるB2−B2線に沿った断面を示す。また、図1Aに示した実施の形態1における縦型電界効果トランジスタと同一の要素については、同一の参照符号を付して、説明の繰り返しを省略する。
図3Aは、実施の形態3における縦型電界効果トランジスタの断面図、図3Bは、図3AにおけるC1−C1線に沿った断面で示した平面図である。なお、図3Aは、図3BにおけるC2−C2線に沿った断面を示す。また、図1Aに示した実施の形態1における縦型電界効果トランジスタと同一の要素については、同一の参照符号を付して、説明の繰り返しを省略する。
図4Aは、実施の形態4における縦型電界効果トランジスタの斜視図、図4Bは、図4AにおけるD−D線に沿った断面図である。本実施の形態は、図2A、図2Bに示した実施の形態2における縦型電界効果トランジスタの構成を、更に具体的にしたものである。実施の形態2の基本構成における、ソース電極1からドレイン電極2に亘って延在する複数の半導体チャンネル部3、ゲート絶縁部として機能する誘電体6、分散ゲート電極7a等を含む構造が、凹凸表面を有する絶縁基板10を用いて形成される。
図7は、実施の形態5における縦型電界効果トランジスタの断面図である。本実施の形態は、実施の形態4と同様に、凹凸表面を有する絶縁基板を用いた構成の例であり、全体的な構造は、図4Aに斜視図で示した実施の形態4におけるものと同様である。図7は、図4AのD−D線に沿った位置に対応する断面構造を示す。但し、動作の原理は、図1A、図1Bに示した実施の形態1と同様であり、ゲート絶縁部として電解質が用いられている。なお、図4A、図4Bに示した実施の形態4における縦型電界効果トランジスタと同一の要素については、同一の参照符号を付して、説明の繰り返しを簡略化する。
図8は、実施の形態6における縦型電界効果トランジスタの断面図である。全体的な構造は、図4Aに斜視図で示した実施の形態4におけるものと同様である。図8は、図4AのD−D線に沿った位置に対応する断面構造を示す。また、図4A、図4Bに示した実施の形態4における縦型電界効果トランジスタと同一の要素については、同一の参照符号を付して、説明の繰り返しを簡略化する。
図9は、実施の形態7における縦型電界効果トランジスタアレイ装置の一部を示す斜視図である。本実施の形態は、上述の各実施の形態のいずれかに示したような構造を有する縦型FET素子20を多数配列して、トランジスタアレイ装置を構成したものである。このようなアレイ構造は、例えば、有機ELディスプレイにおける有機EL素子の駆動に用いることができる。但し、図9には有機EL素子の図示は省略し、配線も概念的に示すのみであって、実際の構造とは異なる。
2 ドレイン電極
3、8 半導体チャンネル部
4 電解質
5 ゲート電極
6 誘電体
7 主ゲート電極
7a 分散ゲート電極
7b ゲート連結部
10 絶縁基板
10a 凸部
10b 凹部
10c 連結部
11 導電層
12 絶縁層
13 半導体層
14a 底部電極層
14b 底部連結電極部
15a 頂部電極層
15b 頂部連結電極部
16 Au膜
17 電解質層
18 導電性基板
18a 凸部
18b 凹部
19 絶縁層
20 縦型FET素子
21 電源ライン
22 データライン
23 ドレイン電極
30 基板
31 ソース電極
32 ドレイン電極
33 半導体
34 ゲート電極
35 キャリア
Claims (9)
- 単一の電界効果トランジスタ素子構造を形成する要素として、
樹脂製の基板であって、その表面に複数の凸部及び前記凸部間の凹部からなる凹凸表面が一体的に形成された絶縁基板と、
前記絶縁基板の前記凹凸表面上に設けられた導電層により形成されたゲート電極と、
前記導電層の表面上に設けられた絶縁層により形成されたゲート絶縁部と、
少なくとも前記凸部の頂部領域及び側壁面領域に亘って連続して前記絶縁層の表面上に設けられた半導体層により形成された複数の半導体チャンネル部と、
前記凹部の各々に前記半導体層と接触させて設けられ互いに接続されて一体の電極として機能する複数の底部電極層により形成されたソース電極/ドレイン電極と、
前記凸部の各々における頂部領域に前記半導体層と接触させて設けられ互いに接続されて一体の電極として機能する複数の頂部電極層により形成されたドレイン電極/ソース電極とを備え、
前記ゲート電極にゲート電圧を印加したときに、前記ゲート絶縁部を介して作用する電界により前記複数の半導体チャンネル部の各々に一括して電気伝導経路が形成されることを特徴とする縦型電界効果トランジスタ。 - 前記ゲート絶縁部が誘電体と電解質の組み合わせにより構成され、前記ゲート電極にゲート電圧を印加したときに、前記電解質を介して作用する電界により前記複数の半導体チャンネル部の各々に一括して電気伝導経路が形成される請求項1に記載の縦型電界効果トランジスタ。
- 前記半導体層は、自己組織化による分子材料成長により形成されたものである請求項1に記載の縦型電界効果トランジスタ。
- 前記絶縁基板が可撓性を有する材質により形成された請求項1に記載の縦型電界効果トランジスタ。
- 前記半導体層が前記凸部の側壁面領域から連続して前記凹部の表面上の少なくとも一部にも形成された請求項1に記載の縦型電界効果トランジスタ。
- 前記頂部電極層および前記底部電極層が前記半導体層の上面に形成された請求項1に記載の縦型電界効果トランジスタ。
- 前記基板の面上に互いに平行に配列された複数本の筋状突起部とそれらを一方の端部で連結する連結部とからなる櫛型***領域が設けられて、前記筋状突起部の各々が前記凸部を形成し、前記筋状突起部の相互間の複数の間隙の各々が前記凹部を形成し、
前記櫛型***領域の櫛の歯の先端に対向する領域に、複数の前記凹部毎に形成された複数の前記底部電極層を連結する底部連結電極部が形成され、
前記櫛型***領域の前記連結部の領域に、前記複数の頂部電極層を連結する頂部連結電極部が形成された請求項1に記載の縦型電界効果トランジスタ。 - 前記基板の面方向における前記筋状突起部の幅をW、前記筋状突起部同士の間隔をSとすると、S/W≦10の条件を満たす請求項7に記載の縦型電界効果トランジスタ。
- 前記基板の面方向における前記筋状突起部の幅をW、前記筋状突起部の前記凹部表面からの高さをHとすると、H/W≧0.3の条件を満たす請求項7に記載の縦型電界効果トランジスタ。
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