JP5584146B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5584146B2 JP5584146B2 JP2011009528A JP2011009528A JP5584146B2 JP 5584146 B2 JP5584146 B2 JP 5584146B2 JP 2011009528 A JP2011009528 A JP 2011009528A JP 2011009528 A JP2011009528 A JP 2011009528A JP 5584146 B2 JP5584146 B2 JP 5584146B2
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Description
(付記1) 前記導電体は、前記絶縁膜上に形成されたバリアメタル層と、前記バリアメタル層上に形成されたシード層と、前記シード層上に形成されたメッキ層からなる積層導電体である請求項4に記載の半導体装置。
前記絶縁膜の形成は、前記半導体素子のフィールド酸化膜の形成と同時におこなう請求項4に記載の半導体装置の製造方法。
11 半導体基板
12 半導体素子
13 ノッチ
14、15 ダイシングライン
16、61、71 貫通電極
21 P+ベース層
22 N+拡散層
23 ゲート絶縁膜
24 ゲート電極
25 絶縁膜
26 ソース電極(第1電極)
27 N+拡散層
28 ドレイン電極(第2電極)
29 パッド
30 絶縁膜
31 導電体
32 TiW/Al積層膜
33 パッシベーション膜
34 NiAuメッキ層
40 マスク材
41 トレンチ(凹部)
42 仮止材
43 支持材
44 テープ
45 ダイシングリング
46 ダイシングシート
50 テスター
51、52、53 プローブ
Claims (4)
- 第1の面と、前記第1の面に対向する第2の面を有する半導体基板と、
前記半導体基板のダイシングラインで囲まれた矩形状格子に形成されるとともに、前記第1の面に形成された第1電極と、前記第2の面に形成された第2電極とを有し、前記第1電極と前記第2電極の間に電流が流れる半導体素子と、
前記半導体基板の前記ダイシングラインで囲まれていない領域であって、前記半導体基板の外周に沿ってリング状に形成されるとともに、一端が前記第1の面上に延在し、他端が前記第2電極と電気的に接続された貫通電極と、
を具備することを特徴とする半導体装置。 - 前記貫通電極は、前記ダイシングラインで囲まれていない領域に分散して形成されていることを特徴とする請求項1に記載の半導体装置。
- 第1の面と前記第1の面に対向する第2の面を有する半導体基板のダイシングラインで囲まれた矩形状格子に、前記第1の面と前記第2の面の間に電流が流れる半導体素子を形成する工程と、
前記半導体基板の前記ダイシングラインで囲まれていない領域であって、前記第1の面に前記半導体基板の外周に沿ってリング状に凹部を形成する工程と、
前記凹部の内面および前記半導体基板の第1の面に、絶縁膜を形成する工程と、
前記絶縁膜を介して、前記凹部を埋め込むとともに前記半導体基板の第1の面に導電体を形成する工程と、
前記半導体基板の前記第2の面側から前記導電体が露出するまで前記半導体基板を除去する工程と、
前記導電体が露出した前記半導体基板の前記第2の面に、前記導電体および前記半導体素子を電気的に接続する電極を形成する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記導電体の形成は、前記半導体素子の形成と同時におこなうことを特徴とする請求項3に記載の半導体装置の製造方法。
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