JP5568824B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5568824B2 JP5568824B2 JP2010172175A JP2010172175A JP5568824B2 JP 5568824 B2 JP5568824 B2 JP 5568824B2 JP 2010172175 A JP2010172175 A JP 2010172175A JP 2010172175 A JP2010172175 A JP 2010172175A JP 5568824 B2 JP5568824 B2 JP 5568824B2
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- JP
- Japan
- Prior art keywords
- substrate
- semiconductor layer
- etching
- wafer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 149
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims description 78
- 238000005530 etching Methods 0.000 claims description 51
- 238000000034 method Methods 0.000 claims description 38
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 8
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 5
- 229910002601 GaN Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 67
- 239000002184 metal Substances 0.000 description 23
- 229910052751 metal Inorganic materials 0.000 description 23
- 239000011347 resin Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000009616 inductively coupled plasma Methods 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Description
<半導体層形成工程>
<半導体素子形成工程>
<溝形成工程>
<基板研磨工程>
<メタルマスク形成工程>
<第1のエッチング工程>
<第2のエッチング工程>
<裏面側配線形成工程>
<取外し工程>
Claims (3)
- 主面及び裏面を有する基板と、前記主面上に設けられた半導体層とを有するウェハを切断予定ラインに沿って切断する工程を含む半導体装置の製造方法であって、
前記ウェハの前記主面側の半導体素子領域と前記切断予定ラインとの間の前記半導体層の領域をエッチングすることにより前記半導体層に溝を形成する溝形成工程と、
前記基板の前記主面と支持基板とが対向するように、前記ウェハを前記支持基板に貼付する工程と、
前記裏面から前記切断予定ラインを含む領域をエッチングして前記ウェハを切断するエッチング工程と
を備えることを特徴とする、半導体装置の製造方法。 - 前記基板の前記主面に半導体素子構造を形成する半導体素子形成工程を、前記溝形成工程の前に更に備えることを特徴とする、請求項1に記載の半導体装置の製造方法。
- 前記基板がシリコンカーバイド基板であり、
前記半導体層が窒化ガリウムを含むことを特徴とする、請求項1または2に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010172175A JP5568824B2 (ja) | 2010-07-30 | 2010-07-30 | 半導体装置の製造方法 |
US13/192,913 US8563404B2 (en) | 2010-07-30 | 2011-07-28 | Process for dividing wafer into individual chips and semiconductor chips |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010172175A JP5568824B2 (ja) | 2010-07-30 | 2010-07-30 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012033721A JP2012033721A (ja) | 2012-02-16 |
JP5568824B2 true JP5568824B2 (ja) | 2014-08-13 |
Family
ID=45525815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010172175A Active JP5568824B2 (ja) | 2010-07-30 | 2010-07-30 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8563404B2 (ja) |
JP (1) | JP5568824B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8440505B2 (en) * | 2009-01-29 | 2013-05-14 | International Business Machines Corporation | Semiconductor chips including passivation layer trench structure |
US9368404B2 (en) | 2012-09-28 | 2016-06-14 | Plasma-Therm Llc | Method for dicing a substrate with back metal |
TWI611582B (zh) * | 2013-04-10 | 2018-01-11 | 半導體能源研究所股份有限公司 | 半導體裝置及其製造方法 |
JP6384934B2 (ja) * | 2017-06-20 | 2018-09-05 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
JP7070848B2 (ja) * | 2018-07-26 | 2022-05-18 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06275713A (ja) * | 1993-03-19 | 1994-09-30 | Hitachi Ltd | 半導体ウエハおよび半導体チップならびにダイシング方法 |
JPH06338563A (ja) * | 1993-05-31 | 1994-12-06 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP2000173952A (ja) | 1998-12-03 | 2000-06-23 | Fujitsu Quantum Device Kk | 半導体装置及びその製造方法 |
JP4284911B2 (ja) * | 2002-01-09 | 2009-06-24 | ソニー株式会社 | 素子の転写方法 |
JP4088120B2 (ja) * | 2002-08-12 | 2008-05-21 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2004193382A (ja) * | 2002-12-12 | 2004-07-08 | Toshiba Corp | 半導体ウェーハ及びその製造方法、半導体チップ |
JP2005302982A (ja) * | 2004-04-12 | 2005-10-27 | Nitto Denko Corp | 半導体チップの製造方法 |
TWI324800B (en) * | 2005-12-28 | 2010-05-11 | Sanyo Electric Co | Method for manufacturing semiconductor device |
JP2008098456A (ja) * | 2006-10-13 | 2008-04-24 | Eudyna Devices Inc | 半導体装置の製造方法 |
US7955955B2 (en) * | 2007-05-10 | 2011-06-07 | International Business Machines Corporation | Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures |
US7871902B2 (en) * | 2008-02-13 | 2011-01-18 | Infineon Technologies Ag | Crack stop trenches |
-
2010
- 2010-07-30 JP JP2010172175A patent/JP5568824B2/ja active Active
-
2011
- 2011-07-28 US US13/192,913 patent/US8563404B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2012033721A (ja) | 2012-02-16 |
US8563404B2 (en) | 2013-10-22 |
US20120025207A1 (en) | 2012-02-02 |
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