JP5387700B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5387700B2 JP5387700B2 JP2012006581A JP2012006581A JP5387700B2 JP 5387700 B2 JP5387700 B2 JP 5387700B2 JP 2012006581 A JP2012006581 A JP 2012006581A JP 2012006581 A JP2012006581 A JP 2012006581A JP 5387700 B2 JP5387700 B2 JP 5387700B2
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Description
上記ゲート絶縁膜41は、例えば2nm〜3nm程度の厚さの高誘電率(High‐k)絶縁膜である酸化ハフニウム(HfO2)膜で形成されている。本実施例ではHfO2を使っているが、HfSiO、酸化タンタル(Ta2O5)、酸化アルミニウムハフニウム(HfAlOx)などのHigh‐k材料を用いたり、もしくは単純に半導体基板11表面、すなわち、シリコン表面を酸化することでゲート絶縁膜41としても構わない。また、あらかじめ半導体基板11表面上に高誘電率(High−k)絶縁膜を形成しておいてそのまま利用しても構わない。
また、上記ゲート電極43、63は、例えば、金属化合物層もしくは金属層を用いる。ここでは、一例として窒化チタン(TiN)を用いている。また、上記金属層としてはタングステン(W)、チタン(Ti)、窒化チタン(TiN)、ハフニウム(Hf)、ハフニウムシリサイド(HfSi)、ルテニウム(Ru)、イリジウム(Ir)、コバルト(Co)などを選択することができる。本実施例では単層の膜を使っているが、抵抗を下げるためや、しきい値電圧を調整するために複数の金属膜を積層しても構わない。
また、上記第2応力印加膜22は、例えば膜厚が40nm程度の圧縮応力を有する窒化シリコン膜で形成する。本実施例では1.2GPaの圧縮応力をもつ膜を形成しているが、応力についてはこの値に限定されるものではない。また膜厚についても本実施例の膜厚に限定されるものではない。
その後、上記イオン注入マスクを除去する。
次いで、n型トランジスタの形成領域12を覆うイオン注入マスク(図示せず)を形成した後、イオン注入法によって、p型トランジスタの形成領域13の半導体基板11中にn型不純物を導入して、n型ウェル領域16を形成する。
その後、上記イオン注入マスクを除去する。さらに、上記保護膜80を除去する。
なお、上記p型ウェル領域15、n型ウェル領域16は、どちらを先に形成してもよい。
上記ダミーゲート絶縁膜81は、例えば1nm〜3nm程度の酸化膜で形成する。その形成方法は、例えば熱酸化プロセスを用いる。
上記ダミーゲート形成膜82は、例えば100nm〜150nm程度の厚さのポリシリコン膜で形成する。その形成方法は、例えばCVD法などを用いる。本実施例ではダミーゲート絶縁膜を後の工程で除去するが、この時点で、例えばゲート絶縁膜を形成する場合もある。例えばゲート絶縁膜には、酸化ハフニウム(HfO2)等の高誘電率(High‐k)絶縁膜を用いることができる。また、上記ダミーゲート形成膜82には、アモルファスシリコン膜を用いることもできる。
上記ハードマスク層83は、例えば、30nm〜100nm程度の厚さの窒化シリコン膜を用いる。その成膜方法は、例えばCVD法による。
なお、上記ドライエッチングではハードマスク層83をほとんどエッチングしないような選択比で行われることがこの好ましい。
また、p型トランジスタの形成領域13において、上記ダミーゲート85の両側のp型トランジスタの形成領域13の半導体基板11にエクステンション領域51、52を形成する。
次いで、n型トランジスタの形成領域12を覆うイオン注入マスク(図示せず)を形成した後、イオン注入法によって、ダミーゲート85の両側におけるp型トランジスタの形成領域13の半導体基板11中にp型不純物を導入して、上記エクステンション領域51、52を形成する。このイオン注入では、n型不純物に例えばホウ素(B)、インジウム(In)等を用いる。また、上記p型不純物のイオン注入マスクには例えばレジスト膜を用いる。
その後、上記イオン注入マスクを除去する。
また、上記各エクステンション領域31、32、51、52の不純物注入をする前に、ダミーゲート84、85の各側壁を窒化シリコン膜や酸化シリコン膜などの側壁保護膜で保護しておいても良い。
同様に、上記ダミーゲート85の両側における半導体基板11に上記エクステンション領域51、52をそれぞれに介してソース・ドレイン領域55、56を形成する。
上記ソース・ドレイン領域35、36の形成には、p型トランジスタの形成領域上にイオン注入マスク(図示せず)を形成した後、例えばn型不純物を上記半導体基板11にイオン注入して形成する。
次いで、上記イオン注入マスクを除去する。
次いで、上記イオン注入マスクを除去する。
その後、活性化アニールを行って、上記エクステンション領域31、32、51、52およびソース・ドレイン領域35、36、55、56に注入された不純物を活性化する。この活性化アニールは、例えば1000℃〜1100℃程度の急速熱処理(RTA)による。
なお、第2応力印加膜22は、水素(H2)ガス(1000cm3/min〜5000cm3/min)、窒素(N2)ガス(500cm3/min〜2500cm3/min)、アルゴン(Ar)ガス(1000cm3/min〜5000cm3/min)、アンモニア(NH3)ガス(50cm3/min〜200cm3/min)、トリメチルシランガス(10cm3/min〜50cm3/min)を供給し、基板温度が400℃〜600℃、圧力が0.13kPa〜0.67kPa、RFパワーが50W〜500Wの条件で化学反応させて形成される。
本実施例では、1.2GPaの圧縮応力をもつ膜を形成しているが、応力についてはこの値に限定されるものではない。また膜厚についても本実施例の膜厚に限定されるものではない。
その後、光リソグラフィー技術およびドライエッチング技術を用いて、p型トランジスタの形成領域13上のみに上記第2応力印加膜22を残すよう加工する。
なお、第1応力印加膜21は、窒素(N2)ガス(500cm3/min〜2000cm3/min)、アンモニア(NH3)ガス(500cm3/min〜1500cm3/min)、モノシラン(SiH4)ガス(50cm3/min〜300cm3/min)を供給し、基板温度が200℃〜400℃、圧力が0.67kPa〜2.0kPa、RFパワーが50W〜500Wの条件で化学反応させる。さらに成膜後、ヘリウム(He)ガス(10L/min〜20L/min)を供給し、温度400℃〜600℃、圧力0.67kPa〜2.0kPa、紫外線(UV)ランプパワーが1kW〜10kWの条件で紫外線(UV)照射処理を行い形成する。
本実施例では1.2GPaの引張応力をもつ膜を形成しているが、応力についてはこの値に限定されるものではない。また膜厚についても本実施例の膜厚に限定されるものではない。
その後、光リソグラフィー技術およびドライエッチング技術を用いて、n型トランジスタの形成領域12上のみに上記第1応力印加膜21を残すよう加工する。なお、上記第1、第2応力印加膜21、22の形成順序はどちらが先に形成されてもよい。
上記ゲート絶縁膜41は、例えば2nm〜3nm程度の厚さの高誘電率(High‐k)絶縁膜である酸化ハフニウム(HfO2)膜で形成されている。本実施例ではHfO2を使っているが、HfSiO、酸化タンタル(Ta2O5)、酸化アルミニウムハフニウム(HfAlOx)などのHigh‐k材料を用いることもでき、また単純に半導体基板11表面、すなわち、シリコン表面を酸化することや、予め半導体基板11表面に形成しておいた高誘電率膜をゲート絶縁膜41としても構わない。
また、上記ゲート電極43、63は、例えば、金属化合物層もしくは金属層を用いる。ここでは、一例として窒化チタン(TiN)を用いている。また、上記金属層としてはタングステン(W)、チタン(Ti)、窒化チタン(TiN)、ハフニウム(Hf)、ハフニウムシリサイド(HfSi)、ルテニウム(Ru)、イリジウム(Ir)、コバルト(Co)などを選択することができる。本実施例では単層の膜を使っているが、抵抗を下げるためや、しきい値電圧を調整するために複数の金属膜を積層しても構わない。
また、上記第4応力印加膜24は、例えば膜厚が40nm程度の圧縮応力を有する窒化シリコン膜で形成する。本実施例では1.2GPaの圧縮応力をもつ膜を形成しているが、応力についてはこの値に限定されるものではない。また膜厚についても本実施例の膜厚に限定されるものではない。
Claims (11)
- 半導体基板上にダミーゲートを形成した後、該ダミーゲートの側壁に側壁絶縁膜を形成し、該ダミーゲートの両側の前記半導体基板にソース・ドレイン領域を形成する工程と、
前記ダミーゲートおよび前記ソース・ドレイン領域の上に応力印加膜を形成する工程と、
前記応力印加膜の上に層間絶縁膜を形成する工程と、
前記ダミーゲートの上の領域に形成された前記応力印加膜と前記ダミーゲートを除去して溝を形成する工程と、
前記溝内の前記半導体基板上にゲート絶縁膜を介してゲート電極を形成する工程と、を備え、
前記溝を形成する工程は、前記層間絶縁膜と前記ダミーゲートの上の領域に形成された前記応力印加膜とをCMP法によって除去する工程を含む
半導体装置の製造方法。 - 前記ダミーゲートを、前記半導体基板上にダミーゲート絶縁膜とダミーゲート形成膜を順に積層して形成した後、該ダミーゲート形成膜をパターニングして形成し、
前記ダミーゲートを除去するときに前記ダミーゲートの下部に形成されている前記ダミーゲート絶縁膜を除去する
請求項1記載の半導体装置の製造方法。 - 半導体基板上のn型トランジスタの形成領域とp型トランジスタの形成領域とにダミーゲートを形成した後、各ダミーゲートの側壁に側壁絶縁膜を形成し、各ダミーゲートの両側の前記半導体基板にソース・ドレイン領域をそれぞれに形成する工程と、
前記n型トランジスタの形成領域の前記ダミーゲートおよび前記ソース・ドレイン領域の上に第1応力印加膜を形成する工程と、
前記p型トランジスタの形成領域の前記ダミーゲートおよび前記ソース・ドレイン領域の上に第2応力印加膜を形成する工程と、
前記第1応力印加膜および前記第2応力印加膜の上に層間絶縁膜を形成する工程と、
前記n型トランジスタの前記ダミーゲートの上の領域に形成された前記第1応力印加膜、前記p型トランジスタの前記ダミーゲートの上の領域に形成された前記第2応力印加膜、および前記各ダミーゲートを除去して溝を形成する工程と、
前記各溝内の前記半導体基板上にゲート絶縁膜を介してゲート電極を形成する工程と、を備え、
前記溝を形成する工程は、前記層間絶縁膜と前記各ダミーゲートの上の領域に形成された前記第1応力印加膜および前記第2応力印加膜とをCMP法によって除去する工程を含む
半導体装置の製造方法。 - 前記ダミーゲートを、前記半導体基板上にダミーゲート絶縁膜とダミーゲート形成膜を順に積層して形成した後、該ダミーゲート形成膜をパターニングして形成し、
前記ダミーゲートを除去するときに前記ダミーゲートの下部に形成されている前記ダミーゲート絶縁膜を除去する
請求項3記載の半導体装置の製造方法。 - 前記ゲート電極を形成した後、前記n型トランジスタ上、もしくはn型トランジスタおよびp型トランジスタ上に第3応力印加膜を形成する
請求項3または請求項4記載の半導体装置の製造方法。 - 前記ゲート電極を形成した後、前記n型トランジスタ上に第3応力印加膜を形成し、前記p型トランジスタ上に第4応力印加膜を形成する
請求項3または請求項4記載の半導体装置の製造方法。 - 前記p型トランジスタのソース・ドレイン領域を応力印加源で形成する
請求項3〜6のいずれか1項に記載の半導体装置の製造方法。 - 前記応力印加源を、
前記半導体基板のソース・ドレイン領域を形成する領域に溝を形成した後、
前記溝にシリコンゲルマニウム層をエピタキシャル成長させて形成する
請求項7記載の半導体装置の製造方法。 - 前記ゲート電極は、金属からなる
請求項1〜8のいずれか1項に記載の半導体装置の製造方法。 - 前記金属は、窒化チタン(TiN)である
請求項9記載の半導体装置の製造方法。 - 前記ゲート絶縁膜は、高誘電率絶縁膜である
請求項1〜10のいずれか1項に記載の半導体装置の製造方法。
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