WO2008038346A1 - Dispositif semiconducteur et son procédé de fabrication - Google Patents

Dispositif semiconducteur et son procédé de fabrication Download PDF

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Publication number
WO2008038346A1
WO2008038346A1 PCT/JP2006/319146 JP2006319146W WO2008038346A1 WO 2008038346 A1 WO2008038346 A1 WO 2008038346A1 JP 2006319146 W JP2006319146 W JP 2006319146W WO 2008038346 A1 WO2008038346 A1 WO 2008038346A1
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Prior art keywords
ladder
semiconductor device
gate electrode
stress
gate
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PCT/JP2006/319146
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English (en)
Japanese (ja)
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Atsushi Yamada
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Fujitsu Limited
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Priority to PCT/JP2006/319146 priority Critical patent/WO2008038346A1/fr
Priority to JP2008536226A priority patent/JP5018780B2/ja
Publication of WO2008038346A1 publication Critical patent/WO2008038346A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a field effect transistor capable of independently controlling biaxial strain in a plane and applying an appropriate strain to a channel region. And a manufacturing method thereof.
  • Si-MOSFET silicon insulated gate field effect transistor
  • a strain introducing technique for improving carrier mobility is used.
  • tensile strain is introduced in the channel region in the gate length direction
  • pMOSFETs compressive strain is introduced in the gate length direction.
  • shallow 'trench' isolation (STI) 102, gate insulating film 103, polysilicon gate 105 and mono-silicide silicide (CoSi) 106, extension 104, sidewall spacer 107, source 'Drain impurity diffusion region 108 is formed by a general CMOS process. Thereafter, a Si nitride film 111 having a high tensile stress is deposited on the entire surface, and the high tensile stress Si nitride film 111 on the pMOSFET is selectively etched to leave the high tensile stress Si nitride film 111 only on the nMOSFET.
  • a nitride film 112 is deposited on the entire surface, and the high compressive stress Si nitride film 112 on the nMOSFET is selectively etched, leaving the high compressive stress Si nitride film 112 only on the pMOSFET.
  • the tensile stress film 111 is formed on the nMOSFET, and the compressive stress film 112 is formed on the pMOSFET.
  • the stress film 111 introduces tensile strain in the gate length direction and compressive strain in the height direction in the channel region of the nMOSFET.
  • the stress film 112 introduces compressive strain in the gate length direction and tensile strain in the height direction in the pMOSFET.
  • a tensile stress film with an intrinsic stress of 1.6 GPa using a tensile stress film with an intrinsic stress of 1.6 GPa, a tensile strain of about 0.3% in the gate length direction and a compressive strain of about 0.3% in the height direction were obtained. It is done.
  • a compressive stress film with an intrinsic stress of 2 GPa can be used to obtain a compressive strain of about 0.4% in the gate length direction and a tensile strain of about 0.5% in the height direction.
  • FIG. 2 shows another known method of obtaining the distortion effect.
  • SiGe silicon germanium
  • SiC silicon carbon
  • a method for introducing strain is studied using a virtual MOSFET structure.
  • a gate pattern 205 is formed by lithography on a Si (100) substrate, and a recess structure is formed by dry etching in the source and drain regions using the gate pattern 205 as a mask. At this time, the etching side surface is tapered.
  • the natural oxide film in the recess region is removed with dilute hydrofluoric acid, and SiC is selectively grown for the nMOSFET.
  • SiC is selectively grown for the nMOSFET.
  • tensile strain in the gate length direction and compressive strain in the height direction are introduced into the channel region of the nMOSFET, respectively.
  • SiGe is selectively grown in the recess. This introduces compressive strain in the gate length direction and tensile strain in the height direction into the channel region of the pMOSFET.
  • the strain in the gate length direction and the height direction can be controlled, but the strain in the gate width direction cannot be controlled.
  • in-plane biaxial strain control will be indispensable in order to further improve carrier mobility.
  • FIG. 3 shows a known method using biaxial strain (for example, see Non-Patent Document 4).
  • This method uses a relaxed virtual substrate using SiGe.
  • the SiGe buffer layer 302 is epitaxially grown on the Si substrate 301 by the CVD method.
  • the SiGe buffer layer 302 relaxes the lattice strain of SiGe by changing the Ge ratio stepwise from 0 to 20% and increasing the film thickness to 1.5 / zm or more.
  • a 600 nm relaxed Si Ge layer 303 and a 75 nm p + Si Ge layer 304 are grown. Then 23 ⁇
  • a thin strained Si layer 305 of m is grown.
  • the above epitaxial growth is performed at 700-750 ° C using dichlorosilane (SiH C1) and GeH.
  • SiH C1 dichlorosilane
  • GeH germane
  • MOS device 310 To manufacture MOS device 310. Note that the strained Si layer 305 is thinned to about 12 nm due to thermal oxidation in the process. This completes the device with biaxial tensile strain introduced in the in-plane direction. As the strain amount at this time, a tensile strain of about 1% is obtained in the biaxial direction.
  • Non-Patent Document 1 S. Pidin et al., IEDM2004 Technical Digest, pp. 213— 2 16
  • Non-Patent Document 2 S. Pidin et al., 2004 Symposium on VLSI Technology Digest, pp. 54-55
  • Non-Patent Document 3 Kah— Wee Ang et al., Appl. Phys. Lett., 86, 093102 (20 05)
  • Non-Patent Document 4 K. Rim et al., IEEE Trans. Electron Devices, 47, 1406 (2000)
  • the present invention provides a semiconductor device capable of independently controlling the strain in the channel length direction and the channel width direction without greatly changing the basic structure of the Si-MOSFET and applying an appropriate strain to the channel region. And it makes it a subject to provide the manufacturing method. Means for solving the problem
  • the semiconductor device includes:
  • the ladder has a compressive stress
  • the gate electrode has a compressive stress or a bow I tension stress that is smaller than the ladder's compressive stress.
  • a tensile stress is inherent in the ladder, and a tensile stress or a compressive stress that is smaller than the tensile stress of the ladder is inherent in the gate electrode.
  • the channel region forms an n-type channel
  • the work function of the ladder is larger than the work function of the gate electrode
  • the channel region forms a p-type channel
  • the work function of the ladder is smaller than the work function of the gate electrode
  • one-dimensional quantum confinement (quantum wire) can be realized by controlling strain in the channel width direction independently and performing band control in the channel region.
  • FIG. 1 is a diagram showing an example of a known strain introduction structure.
  • FIG. 2 is a diagram showing another example of a known strain introduction structure.
  • FIG. 3 is a diagram showing another example of a known strain introduction structure.
  • FIG. 4 is a schematic view showing a gate structure of a semiconductor device according to an embodiment of the present invention.
  • FIG. 5 is a schematic plan view showing a gate structure of the semiconductor device of the embodiment.
  • FIG. 6 is a schematic cross-sectional view in the channel width direction along the line AA ′ in FIG. 5, showing the stress applied in the channel width direction.
  • FIG. 7 is a schematic cross-sectional view in the channel length direction along the line BB ′ in FIG. 5, showing the stress applied to the nMOSFET.
  • FIG. 8 is a schematic cross-sectional view in the channel length direction along the line BB ′ of FIG. 5, showing the stress applied to the pMOSFET.
  • FIG. 9 shows a modification of the semiconductor device of the embodiment, in which a strain applying layer selectively grown in the source / drain region of the nMOSFET is used in place of the stress film covering the gate electrode or the stress film.
  • FIG. 10 shows a modification of the semiconductor device according to the embodiment, in which a strain application layer selectively grown in the source / drain regions of the pMOSFET is used instead of or together with the stress film covering the gate electrode.
  • FIG. 11A is a diagram for explaining the confinement effect in the channel region immediately below the ladder.
  • FIG. 11B is a diagram showing a band change due to the work function of the ladder (G1) and the metal gate (G2) in the nMOSFET in the configuration of FIG. 11A.
  • FIG. 11C is a diagram showing a band change due to the work function of the ladder (G1) and the metal gate (G2) in the pnMOSFET in the configuration of FIG. 11A.
  • FIG. 11D is a diagram showing a band change when the ladder is formed of an insulating film that applies compressive stress as a modification of FIG. 11A.
  • FIG. 12 is a view showing an example in which a ladder is made of a metal that applies compressive stress as a modification of FIG.
  • FIG. 13A A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.
  • FIG 13B A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.
  • FIG. 13C is a manufacturing process diagram of the semiconductor device according to one embodiment of the present invention.
  • FIG 13E A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.
  • FIG 13G A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.
  • FIG. 131 A manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing a gate structure of the semiconductor device 10 according to one embodiment of the present invention. is there.
  • the semiconductor device 10 is located on a semiconductor substrate 11 via a gate insulating film 13 and has a gate electrode 16 to which a gate voltage is applied, and a ladder 15 inserted between the gate insulating film 13 and the gate electrode 16.
  • the ladder 15 is arranged in the channel width direction (y-axis direction in FIG. 4), and each stripe constituting the ladder extends in a direction parallel to the current flow (X-axis direction).
  • the ladder structure 15 constituting the first part of the gate and the gate electrode 16 constituting the second part of the gate constitute a gate structure 19.
  • a source / drain impurity diffusion region (hereinafter simply referred to as “source / drain”) 14 is formed in the semiconductor substrate 11 with the gate electrode 16 interposed therebetween.
  • a side wall spacer 17 is provided on the side wall of the gate electrode 16, and a stress film 20 is formed so as to cover the gate electrode 16 and the side wall spacer 17.
  • the stress film 20 mainly controls strain in the channel length direction (X-axis direction).
  • the ladder 15 mainly serves to control strain in the channel width direction (y-axis direction).
  • the stress film 20 and the ladder 15 can control the biaxial strain independently of each other.
  • FIG. 5 is a schematic plan view of the semiconductor device 10 of the embodiment. At least a part of the gate electrode 16 extends between the source region 14s and the drain region 14d.
  • a channel region (not shown in FIG. 5) is formed in the surface region of the semiconductor substrate between the source region 14s and the drain region 14d.
  • the ladder 15 is arranged in a direction (y-axis direction or channel width direction) orthogonal to the current flow. There is no limit to the number of stripes that make up ladder 15, but there must be at least one space between the stripes.
  • FIG. 6 is a schematic cross-sectional view along the line AA ′ in FIG.
  • the ladder (hereinafter referred to as “G1” as appropriate) 15 is made of a material that applies tensile stress (ie, inherently contains tensile stress), and is a gate electrode (hereinafter referred to as “G2” as appropriate).
  • G1 tensile stress
  • G2 gate electrode
  • 16 is made of a material that gives compressive stress (ie, compressive stress is inherent).
  • the ladder 15 is an electrode formed by vapor deposition of gold (Au), and a plurality of stripes are arranged in the y-axis (channel width) direction through a space 18 of lOOnm or less.
  • the metal gate 16 is TiN formed by sputtering.
  • the ladder region (Gl) 15 that applies tensile stress and the metal gate 16 that applies compressive stress can generate strain in the y-axis direction in the channel region. For example, when Au with an intrinsic stress of 0.5 GPa and TiN with an intrinsic stress of 2 GPa are used, a strain of about 0.5% can be applied.
  • each ladder 15 in the channel region is referred to as a sub-channel region.
  • the ladder 15 When the tensile stress of the ladder 15 is sufficiently large, the ladder 15 alone can apply sufficient strain in the channel width direction (y-axis direction).
  • the stress applied to the metal gate 16 may be a tensile stress sufficiently smaller than that of the ladder 15, no stress, or a state of applying compressive stress!
  • the stress application state of the ladder 15 is no stress or gives a compressive stress sufficiently smaller than that of the metal gate 16. Even in the state of applying a tensile stress, it may be a deviation.
  • the materials of the ladder 15 and the metal gate 16 are different. However, even if the same material is used, different stresses are applied by changing the film formation method and the film formation conditions, as will be described later. It can have characteristics.
  • FIG. 7 and FIG. 8 are schematic cross-sectional views along the line BB ′ of FIG.
  • Fig. 7 shows the strain introduction of nMOSFET
  • Fig. 8 shows the strain introduction of pMOSFET.
  • a silicon nitride film 20T which is a stress film for applying a tensile stress
  • a silicon nitride film 20C which is a stress film that applies compressive stress
  • These stress films function as a strain-introducing layer.
  • tensile strain occurs in the X-axis direction and compressive strain in the z-axis direction.
  • compressive strain in the X-axis direction z-axis causess tensile strain in the direction.
  • strain is also generated in the y-axis direction. In-plane strain in the two axes (X-axis and y-axis) and the height direction Strain is generated.
  • Methods other than the stress film 20 may be used for applying strain in the channel length (x-axis) direction and height (z-axis) direction.
  • a strain applying layer may be provided in the source / drain region of the MOSFET instead of the stress film 20 or together with the stress film 20.
  • a Si C strained layer 21T with a small lattice constant of SU is selectively grown in the source and drain regions of the nMOSFET, and the SiGe strain with a large lattice constant of SU is also used for the pMOSFET.
  • the application layer 21C is selectively grown.
  • the strain applying layers 21T and 21C function as strain introducing layers that cause strain in the channel length direction in the channel region.
  • the gate structure 19 covered with the sidewall spacer 17 is formed on the gate insulating film 13 on the Si (100) substrate 11.
  • the gate structure 19 includes the ladder (G1) 15 and the gate electrode (metal gate: G2) 16 arranged in the channel width direction.
  • this gate structure 19 as a mask, recesses are formed in the source / drain regions by dry etching, impurities are implanted, the surface is cleaned with dilute hydrofluoric acid or the like, and then a strain applying layer 21 is grown.
  • the SiC layer 21T is selectively formed at 600 ° C by chemical vapor deposition (CVD).
  • Si C is S
  • SiGe layer 21C at 600 ° C by D method. This forms Si Ge in the source and drain regions.
  • Si Ge is about 1% larger than the lattice constant of Si
  • nMOSFET using a SiC layer 21T with an intrinsic stress of 1.6 GPa, a tensile strain of about 0.3% in the gate length direction and a compressive strain of about 0.2% in the height direction can be obtained.
  • pMOSF ET using an intrinsic stress—2GPa SiGe layer 21C, a compressive strain of about 0.6% in the gate length direction and a tensile strain of about 0.4% in the height direction can be obtained.
  • in-plane biaxial strain can be reduced in the channel region. It can be generated separately. That is, the ladder 15 controls the strain in the channel width direction, and the stress film 20 and the Z or strain applying layer 21 function as a strain introduction layer in the channel length direction. Can be controlled.
  • biaxial tensile strain is applied to the subchannel region (see FIG. 6) immediately below the ladder 15 in the channel region in the x and y axis directions.
  • tensile strain is applied in the X-axis direction and compressive strain is applied in the y-axis direction, so it is regarded as uniaxial tensile strain.
  • FIG. 11A to FIG. 11C are diagrams for explaining the reason why the carrier mobility is improved in the channel region by the above-described configuration.
  • the conduction band of Si is known to be larger than that of uniaxial due to biaxial tensile strain. That is, as shown in FIG. 11A, the conduction band (Ec) in the conduction band of the subchannel region (see FIG. 6) just below the ladder 15 is lower than the region just below the space 18. Therefore, electrons flow dominantly in the subchannel region, and biaxial tensile strain is generated in the nMOSFET, which makes it possible to confine electrons in the subchannel region.
  • the valence band energy of Si increases the energy of the valence band due to uniaxial compressive strain. That is, as shown in FIG. 11A, the energy of the conduction band is higher in the valence band of the subchannel region than in the region immediately below the space 18. Therefore, the positive holes flow dominantly in the subchannel region, and in the pMOSFET, holes can be confined in the subchannel region where uniaxial compressive strain is generated.
  • the in-plane biaxial strain can be controlled independently.
  • nMOSFET when 0.3% tensile strain is applied in the x-axis (channel length) direction and 0.5% tensile strain is applied in the y-axis (channel width) direction, mobility is improved from the piezoresistance coefficient.
  • the effect of improving mobility by about 1.9 times is obtained compared to the case of one axis.
  • FIG. 11B and FIG. 11C are diagrams for explaining the confinement of carriers in the subchannels immediately below the ladder 15.
  • the ladder (G1) 15 and the metal gate (G2) 16 are formed of metals having different work functions.
  • Fig. 11B shows the band change according to the work function difference in nMOS
  • Fig. 11C shows the band change according to the work function difference in pMOS.
  • the ladder (G1) 15 uses a metal having a work function larger than that of the metal gate (G2) 16.
  • the conduction band of Si directly under the ladder (G1) is compared with that under the metal gate (G2) 16 due to the difference in work function. Since the energy increases, it becomes stronger than the confinement force of electrons in the channel region under the metal gate (G2) 16.
  • the ladder (G1) 15 uses a metal having a work function smaller than that of the metal gate (G2) 16.
  • the metal gate (G2) 16 For example, if aluminum (A1) is used for ladder (G1) 15 and TiN is used for metal gate (G2) 16, the valence valence band of Si just below ladder (G1) 15 due to the difference in work function (gate) Since the energy is lower than that under G2) 16, the effect is stronger than the confinement of holes in the channel region under metal gate (G2) 16.
  • FIG. 11D is a diagram showing carrier confinement when the ladder 15 is formed of an insulator such as a silicon nitride film.
  • the electric field exerted directly below the insulator ladder 25 is weaker than Si just below the metal gate 26, so that the bending of the band is reduced. Thereby, the confinement of carriers in the channel region becomes stronger.
  • Band bending is shown in Fig. 1. As indicated by ID, control is possible by the film thickness of the insulating film (ladder 15).
  • FIG. 12 shows a modification of FIG.
  • the ladder 25 is formed of a metal that applies compressive stress
  • the metal gate 26 is formed of a metal that applies tensile stress.
  • the width of the ladder or space is reduced in the gate structure into which the ladder is introduced, the strain applied to the channel region increases and the change in the band increases. This results in stronger carrier confinement. If the ladder width or space width is reduced to about 10 nm or less, carriers are confined in a very narrow region, and a quantum effect occurs. Thereby, a quantum wire FET can also be realized.
  • FIG. 13A to FIG. 13K are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention.
  • the Si (100) substrate 31 is used, and the 110> direction is used as the channel direction.
  • Dummy gate removal is performed on this substrate 31 by a conventional damascene metal gate manufacturing process.
  • a well region (not shown) is formed in a predetermined region of the Si substrate 31, and an element isolation region (not shown) such as STI is formed.
  • a silicon oxide film 32, a polysilicon film 32, and a silicon nitride film 34 are sequentially formed.
  • the Si oxide film 32 is formed by, for example, a thermal oxidation method, and the polysilicon film 33 and the silicon nitride film 34 are respectively formed by a CVD method.
  • the dummy gate 35 is formed by patterning the silicon nitride film 34 and the polysilicon film 33 by a normal lithography method and etching method. Dummy game Using the substrate 35 as a mask, impurities are implanted into the substrate 31 to form extensions 36.
  • sidewall spacers 37 are formed, impurities are implanted at a high concentration using the dummy gate 35 and the sidewall spacers 37 as masks, and heat treatment is performed. Source / drain regions 39 are formed. Thereafter, a silicon nitride film 38 for an etching stopper is deposited on the entire surface by the CVD method.
  • a silicon oxide film 40 is deposited on the entire surface by the CVD method. Subsequently, using the silicon nitride film 38 as a stopper, the Si oxide film 40 is polished and planarized by the CMP method.
  • the silicon nitride film 38 (34) and the polysilicon film 33 on the dummy gate are removed with, for example, hot phosphoric acid and a hydrazine solution. Further, the silicon oxide film 32 as a sacrificial gate insulating film is removed with a dilute hydrofluoric acid solution to form an opening 41.
  • a gate insulating film 53 is formed on the surface of the silicon substrate 31 in the opening 41 by a thermal oxidation method.
  • a ladder (G 1) 55 is formed in the opening 41.
  • the ladder 55 is patterned by, for example, depositing TiN and performing lift-off or dry etching.
  • the ladder interval (space width) is preferably less than lOOnm in order to effectively apply strain.
  • the number of ladder spaces is an arbitrary number of 1 or more.
  • TiN for Ladder 55 is adjusted to be a stress film that gives no stress or tensile stress.
  • a piezoelectric element is used to apply longitudinal vibration to the substrate at a predetermined excitation frequency (for example, 100 Hz), and the amplitude is adjusted by the applied voltage. By doing so, the internal stress can be adjusted in a wide range from no stress to tensile stress (for details, refer to JP-A-2004-68058).
  • a metal film 56 for example, titanium nitride (TiN) 56 is deposited on the entire surface so as to cover the ladder (G 1) 55 by a sputtering method.
  • TiN formed by sputtering has a large amount of compressive stress!
  • the TiN ladder film 55 and the TiN metal gate 56 remain in the opening by polishing the TiN sputtering film 56 by the CMP method.
  • Ladder 55 and gate electrode The metal structure 56 constitutes a gate structure 59.
  • tensile strain in the channel width direction is generated by the tensile stress of the TiN ladder 55 and the compressive stress of the TiN metal gate 56 by sputtering.
  • the Si oxide film 40 is removed, for example, with a buffered hydrofluoric acid solution.
  • a Si nitride film 60 to be a stress film is formed by a CVD method and dry etching.
  • a tensile stress film is selectively formed on the nMOSFET, and a compressive stress film is selectively formed on the pMOSFET.
  • the main process is completed, and thereafter, a normal wiring process and the like are performed, and the semiconductor device 10 is completed.
  • the ladder 55 when the ladder 55 is formed of an insulator instead of TiN, it can be manufactured in the same process.
  • the ladder 25 is made of a material that applies compressive stress
  • the dummy gate is removed and the gate insulating film 53 is formed in the same process as in FIGS. 13A to 13F.
  • TiN is deposited by sputtering, and a ladder 55 is formed by dry etching.
  • TiN produced by sputtering has a strong compressive stress.
  • nMOSFET and pMOSFET When metals with different work functions are used for nMOSFET and pMOSFET as shown in Fig. 11B, the dummy gate is removed by the steps from Fig. 13A to Fig. 13F to form the gate insulating film 53, and then to Fig. 13G.
  • the ladder 55 is formed in a corresponding process.
  • both nMO S and pMOS use TiN as the ladder, and the force that makes the work function of the metal gate different from each other.
  • the work function of the ladder differs between nMOS and pMOS, and the metal gate is made of the same material. May be formed.
  • Au is deposited on the nMOSFET, and the ladder 55 is selectively deposited by lift-off. At this time, tensile stress is inherent in the deposited Au.
  • aluminum (A1) is deposited on the pMOSFET, and a ladder 55 having a different work function is formed by lift-off. At this time, weak compressive stress is inherent in A1 by vapor deposition.
  • TiN is deposited by sputtering and flattened by CMP to form a metal gate (electrode body) 56.
  • the weak compressive stress of the A1 gate grid 55 is not a problem because the stress of the TiN metal gate 56 is large.
  • the semiconductor device 10 with a controlled work function is formed. This technique increases carrier confinement and further improves performance.
  • band control is performed by applying an appropriate strain in directions of two or more axes, and one-dimensional quantum confinement (quantum wire) is realized. .
  • quantum wire quantum wire
  • a quantum wire MOSFET can be realized while maintaining the basic flow of the conventional Si process, so that simplification of the process and improvement in the degree of freedom in design can be expected. .
  • the channel region cannot be etched unlike the conventional quantum wire, it is possible to suppress scattering due to surface roughness, which leads to further high-speed FET operation.

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  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne un dispositif semiconducteur qui comprend un substrat de silicium (11), une électrode grille (16) située à l'opposé d'un isolateur grille (13) sur le substrat de silicium, et des échelles (15) qui se situent entre l'isolateur grille et l'électrode grille ; ces éléments ont une tension différente de celle de l'électrode grille et sont structurés en réseau perpendiculairement à la direction d'un courant qui passe à travers un canal situé immédiatement au-dessous de l'électrode grille.
PCT/JP2006/319146 2006-09-27 2006-09-27 Dispositif semiconducteur et son procédé de fabrication WO2008038346A1 (fr)

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PCT/JP2006/319146 WO2008038346A1 (fr) 2006-09-27 2006-09-27 Dispositif semiconducteur et son procédé de fabrication
JP2008536226A JP5018780B2 (ja) 2006-09-27 2006-09-27 半導体装置およびその製造方法

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011010407A1 (fr) * 2009-07-23 2011-01-27 パナソニック株式会社 Dispositif à semi-conducteurs et son procédé de fabrication
JP2012124503A (ja) * 2007-03-20 2012-06-28 Sony Corp 半導体装置の製造方法
WO2012176503A1 (fr) * 2011-06-23 2012-12-27 三菱電機株式会社 Dispositif semi-conducteur et procédé de fabrication d'un dispositif semi-conducteur
CN105140125A (zh) * 2015-08-28 2015-12-09 陕西学前师范学院 应变Ge倒梯形栅NMOS器件及制备方法
US9449974B2 (en) 2007-03-20 2016-09-20 Sony Corporation Semiconductor device and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07202178A (ja) * 1993-12-28 1995-08-04 Toshiba Corp 半導体装置およびその製造方法
JPH1126765A (ja) * 1997-07-09 1999-01-29 Nec Corp 電界効果型トランジスタ及びその製造方法
JP2006253318A (ja) * 2005-03-09 2006-09-21 Fujitsu Ltd ｐチャネルＭＯＳトランジスタおよびその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3523093B2 (ja) * 1997-11-28 2004-04-26 株式会社東芝 半導体装置およびその製造方法
JP2002093921A (ja) * 2000-09-11 2002-03-29 Hitachi Ltd 半導体装置の製造方法
JP2006120718A (ja) * 2004-10-19 2006-05-11 Toshiba Corp 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07202178A (ja) * 1993-12-28 1995-08-04 Toshiba Corp 半導体装置およびその製造方法
JPH1126765A (ja) * 1997-07-09 1999-01-29 Nec Corp 電界効果型トランジスタ及びその製造方法
JP2006253318A (ja) * 2005-03-09 2006-09-21 Fujitsu Ltd ｐチャネルＭＯＳトランジスタおよびその製造方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012124503A (ja) * 2007-03-20 2012-06-28 Sony Corp 半導体装置の製造方法
US9449974B2 (en) 2007-03-20 2016-09-20 Sony Corporation Semiconductor device and method of manufacturing the same
US9881920B2 (en) 2007-03-20 2018-01-30 Sony Corporation Semiconductor device and method of manufacturing the same
US10269801B2 (en) 2007-03-20 2019-04-23 Sony Corporation Semiconductor device and method of manufacturing the same
US10559567B2 (en) 2007-03-20 2020-02-11 Sony Corporation Semiconductor device and method of manufacturing the same
US11011518B2 (en) 2007-03-20 2021-05-18 Sony Corporation Semiconductor device and method of manufacturing the same
US11664376B2 (en) 2007-03-20 2023-05-30 Sony Group Corporation Semiconductor device and method of manufacturing the same
WO2011010407A1 (fr) * 2009-07-23 2011-01-27 パナソニック株式会社 Dispositif à semi-conducteurs et son procédé de fabrication
WO2012176503A1 (fr) * 2011-06-23 2012-12-27 三菱電機株式会社 Dispositif semi-conducteur et procédé de fabrication d'un dispositif semi-conducteur
US9093361B2 (en) 2011-06-23 2015-07-28 Mitsubishi Electric Corporation Semiconductor device
CN105140125A (zh) * 2015-08-28 2015-12-09 陕西学前师范学院 应变Ge倒梯形栅NMOS器件及制备方法

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