JP5367075B2 - Pll周波数シンセサイザ - Google Patents
Pll周波数シンセサイザ Download PDFInfo
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- JP5367075B2 JP5367075B2 JP2011514316A JP2011514316A JP5367075B2 JP 5367075 B2 JP5367075 B2 JP 5367075B2 JP 2011514316 A JP2011514316 A JP 2011514316A JP 2011514316 A JP2011514316 A JP 2011514316A JP 5367075 B2 JP5367075 B2 JP 5367075B2
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- 230000010355 oscillation Effects 0.000 claims description 34
- 238000001514 detection method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
110 デジタル制御発振器
111 インダクタ素子
112 負性抵抗素子
113,114 バラクタアレイ
115 付加バラクタ
120 分周器
130 フリップフロップ
140 位相比較器
150 ループフィルタ
160,170 トラッキングバラクタ制御部
180 周波数特性調整部
Claims (6)
- 複数の可変容量素子からなる第1の容量素子群と複数の可変容量素子からなる第2の容量素子群とを含む発振部と、
前記発振部の出力信号の位相と基準信号の位相との差分に対応する位相誤差信号を生成し、前記位相誤差信号の整数部によって前記第1の容量素子群の容量値を制御するとともに前記位相誤差信号の小数部によって前記第2の容量素子群の容量値を制御することにより、前記発振部の出力周波数を制御する発振周波数制御手段と、
を具備するPLL周波数シンセサイザであって、
前記小数部の値と前記小数部の値に最も近い整数値との差分と、所定の閾値との比較結果に基づいて、調整信号を生成する調整信号生成手段と、
前記発振部に設けられ、前記調整信号に基づいて前記位相誤差信号の桁上がり又は桁下がりの発生確率の低い範囲に前記発振部の発振周波数特性をシフトする周波数特性シフト手段と、
を具備するPLL周波数シンセサイザ。 - 前記周波数特性シフト手段は、可変容量素子からなり、
前記可変容量素子の容量値は、前記調整信号に基づいて変化する、
請求項1に記載のPLL周波数シンセサイザ。 - 前記可変容量素子の容量値は、前記第1の容量素子群及び前記第2の容量素子群を構成する可変容量素子の容量値の整数倍を除く値に設定される、
請求項2に記載のPLL周波数シンセサイザ。 - 前記周波数特性シフト手段は、複数の容量素子からなり、
前記複数の容量素子の容量値は互いに異なり、
前記複数の容量素子の少なくとも1つが、前記調整信号に基づいてオンする、
請求項1に記載のPLL周波数シンセサイザ。 - 前記調整信号生成手段は、前記発振周波数制御手段に含まれるデルタシグマ変調器の次数、又は前記発振部の出力周波数に基づいて、前記所定の閾値を変更する、
請求項1に記載のPLL周波数シンセサイザ。 - 前記周波数特性シフト手段は、可変インダクタ素子からなり、
前記可変インダクタ素子のインダクタンス値は、前記調整信号に基づいて変化する、
請求項1に記載のPLL周波数シンセサイザ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011514316A JP5367075B2 (ja) | 2009-05-22 | 2010-05-11 | Pll周波数シンセサイザ |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009124600 | 2009-05-22 | ||
JP2009124600 | 2009-05-22 | ||
PCT/JP2010/003197 WO2010134287A1 (ja) | 2009-05-22 | 2010-05-11 | Pll周波数シンセサイザ |
JP2011514316A JP5367075B2 (ja) | 2009-05-22 | 2010-05-11 | Pll周波数シンセサイザ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2010134287A1 JPWO2010134287A1 (ja) | 2012-11-08 |
JP5367075B2 true JP5367075B2 (ja) | 2013-12-11 |
Family
ID=43125980
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011514316A Expired - Fee Related JP5367075B2 (ja) | 2009-05-22 | 2010-05-11 | Pll周波数シンセサイザ |
Country Status (3)
Country | Link |
---|---|
US (1) | US8525608B2 (ja) |
JP (1) | JP5367075B2 (ja) |
WO (1) | WO2010134287A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8953730B2 (en) | 2012-04-20 | 2015-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Auto frequency calibration for a phase locked loop and method of use |
JP6171522B2 (ja) * | 2013-04-16 | 2017-08-02 | 富士通株式会社 | デジタル制御発振器及び出力周波数制御方法 |
US20150116012A1 (en) * | 2013-10-30 | 2015-04-30 | Hasnain Lakdawala | Digital Voltage Ramp Generator |
US9641113B2 (en) | 2014-02-28 | 2017-05-02 | General Electric Company | System and method for controlling a power generation system based on PLL errors |
US11277096B2 (en) | 2020-02-25 | 2022-03-15 | Stmicroelectronics International N.V. | Digitally controlled LC oscillator |
US11018680B1 (en) * | 2020-07-15 | 2021-05-25 | Keysight Technologies, Inc. | Phase lock loops (PLLS) and methods of initializing PLLS |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040066240A1 (en) * | 2001-04-25 | 2004-04-08 | Staszewski Robert B. | Frequency synthesizer with digitally-controlled oscillator |
US7352297B1 (en) * | 2007-02-09 | 2008-04-01 | International Business Machines Corporation | Method and apparatus for efficient implementation of digital filter with thermometer-code-like output |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6429693B1 (en) | 2000-06-30 | 2002-08-06 | Texas Instruments Incorporated | Digital fractional phase detector |
US7006589B2 (en) | 2001-04-25 | 2006-02-28 | Texas Instruments Incorporated | Frequency synthesizer with phase restart |
JP2004015387A (ja) | 2002-06-06 | 2004-01-15 | Matsushita Electric Ind Co Ltd | 電圧制御型発振器及び周波数シンセサイザ |
US7528665B2 (en) | 2005-08-02 | 2009-05-05 | Rf Magic, Inc. | Multiple frequency source system and method of operation |
JP2009010599A (ja) * | 2007-06-27 | 2009-01-15 | Panasonic Corp | デジタル制御発振回路、周波数シンセサイザ、それを用いた無線通信機器及びその制御方法 |
-
2010
- 2010-05-11 JP JP2011514316A patent/JP5367075B2/ja not_active Expired - Fee Related
- 2010-05-11 US US13/319,221 patent/US8525608B2/en not_active Expired - Fee Related
- 2010-05-11 WO PCT/JP2010/003197 patent/WO2010134287A1/ja active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040066240A1 (en) * | 2001-04-25 | 2004-04-08 | Staszewski Robert B. | Frequency synthesizer with digitally-controlled oscillator |
US7352297B1 (en) * | 2007-02-09 | 2008-04-01 | International Business Machines Corporation | Method and apparatus for efficient implementation of digital filter with thermometer-code-like output |
Also Published As
Publication number | Publication date |
---|---|
WO2010134287A1 (ja) | 2010-11-25 |
JPWO2010134287A1 (ja) | 2012-11-08 |
US20120119839A1 (en) | 2012-05-17 |
US8525608B2 (en) | 2013-09-03 |
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