JP5341426B2 - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
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- JP5341426B2 JP5341426B2 JP2008208064A JP2008208064A JP5341426B2 JP 5341426 B2 JP5341426 B2 JP 5341426B2 JP 2008208064 A JP2008208064 A JP 2008208064A JP 2008208064 A JP2008208064 A JP 2008208064A JP 5341426 B2 JP5341426 B2 JP 5341426B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 133
- 238000001514 detection method Methods 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 238000011084 recovery Methods 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims description 82
- 230000003071 parasitic effect Effects 0.000 description 85
- 238000010586 diagram Methods 0.000 description 22
- 239000012535 impurity Substances 0.000 description 18
- 230000002411 adverse Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 2
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
図1は本実施形態にかかる半導体集積回路の、nチャネルMOSトランジスタと、このnチャネルMOSトランジスタでのラッチアップの発生を検出するラッチアップ検出回路とが形成されている部分の部分拡大断面図である。
次に、本発明の半導体集積回路の第2の実施形態として、本発明の半導体集積回路をCMOS集積回路に適用した場合について説明する。図4は、本発明の第2の実施形態であるCMOS集積回路の、nチャネルMOSトランジスタとpチャネルMOSトランジスタ、ならびに、nチャネルMOSトランジスタでのラッチアップの発生を検出するラッチアップ検出回路とが形成されている部分の拡大断面構成図である。
次に、本発明の半導体集積回路の第3の実施形態として、本発明の半導体集積回路でのラッチアップからの回復を行う構成について図面を用いて説明する。
次に、本発明の半導体集積回路の第4の実施形態として、本発明の半導体集積回路でのラッチアップからの回復を行う別の構成について図面を用いて説明する。
2 N型拡散(N−well)層
3 P型拡散(p−well)層(P型領域)
4 ドレイン
5 ソース
6 ゲート
7 nチャネルMOSトランジスタ
8 バックゲート
9 ドレイン
10 ソース
11 ゲート
12 nMOSトランジスタ構造体
15 抵抗体(電流検出手段)
Claims (11)
- 半導体基板のP型領域上に形成されたnチャネルMOSトランジスタと、
前記nチャネルMOSトランジスタでのラッチアップの発生を検出するラッチアップ検出回路とを備え、
前記ラッチアップ検出回路が、前記nチャネルMOSトランジスタとソースおよびバックゲートとが共通に接続されたnMOSトランジスタ構造体と、前記nMOSトランジスタ構造体のドレインに流れる電流を検出する電流検出手段とを有し、
前記nMOSトランジスタ構造体のゲートが、前記nMOSトランジスタ構造体のソースおよびバックゲートと接続されていることを特徴とする半導体集積回路。 - 前記電流検出手段が、一端が前記nMOSトランジスタ構造体のドレインに接続され、他端が半導体集積回路の正電源電圧に接続された抵抗体である請求項1に記載の半導体集積回路。
- 前記電流検出手段が、前記nMOSトランジスタ構造体のドレインに接続された、電流検出回路である請求項1に記載の半導体集積回路。
- 前記半導体基板のP型領域が、P型基板層である請求項1から3のいずれかに記載の半導体集積回路。
- 前記半導体基板のP型領域が、P型基板層内のN型拡散層に形成されたP型拡散層である請求項1から3のいずれかに記載の半導体集積回路。
- 互いに接続された、前記nMOSトランジスタ構造体のゲート、ソース、バックゲートに、負電圧が印加される請求項1から5のいずれかに記載の半導体集積回路。
- 前記nチャネルMOSトランジスタのドレインが、半導体集積回路の入力端子または出力端子に接続される請求項1から6のいずれかに記載の半導体集積回路。
- 半導体基板のP型領域上に形成されたnチャネルMOSトランジスタと、
前記nチャネルMOSトランジスタでのラッチアップの発生を検出するラッチアップ検出回路と、
前記nチャネルMOSトランジスタに負電位を供給する負電圧発生回路と、
前記ラッチアップ検出回路でラッチアップの発生が検出されたときに、前記負電圧発生回路からの負電位の供給を停止させ、その後負電位の供給を再開させる制御ブロックとを備え、
前記ラッチアップ検出回路が、前記nチャネルMOSトランジスタとソースおよびバックゲートとが共通に接続されたnMOSトランジスタ構造体と、前記nMOSトランジスタ構造体のドレインに流れる電流を検出する電流検出手段とを有し、
前記nMOSトランジスタ構造体のゲートが、前記nMOSトランジスタ構造体のソースおよびバックゲートと接続されたことを特徴とする半導体集積回路。 - 前記nチャネルMOSトランジスタのソースおよびバックゲートと、前記nMOSトランジスタ構造体のソースおよびバックゲートに、前記負電圧発生回路が供給する負電位が印加される請求項8に記載の半導体集積回路。
- 前記制御ブロックが、前記負電圧発生回路からの負電位の供給を停止させた後、所定時間が経過したときに負電位の供給を再開させる請求項8または9に記載の半導体集積回路。
- 前記制御ブロックが、前記ラッチアップ検出回路がラッチアップからの回復を検出したときに、前記負電圧発生回路からの負電位の供給を再開させる請求項8または9に記載の半導体集積回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008208064A JP5341426B2 (ja) | 2008-08-12 | 2008-08-12 | 半導体集積回路 |
US12/539,251 US8116050B2 (en) | 2008-08-12 | 2009-08-11 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
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JP2008208064A JP5341426B2 (ja) | 2008-08-12 | 2008-08-12 | 半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
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JP2010045182A JP2010045182A (ja) | 2010-02-25 |
JP5341426B2 true JP5341426B2 (ja) | 2013-11-13 |
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JP2008208064A Expired - Fee Related JP5341426B2 (ja) | 2008-08-12 | 2008-08-12 | 半導体集積回路 |
Country Status (2)
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US (1) | US8116050B2 (ja) |
JP (1) | JP5341426B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2369622B1 (fr) | 2010-03-24 | 2015-10-14 | STMicroelectronics Rousset SAS | Procédé et dispositif de contremesure contre une attaque par injection d'erreur dans un microcircuit électronique |
US8373497B2 (en) * | 2011-01-11 | 2013-02-12 | Infineon Technologies Ag | System and method for preventing bipolar parasitic activation in a semiconductor circuit |
US9025266B2 (en) | 2013-06-14 | 2015-05-05 | Rohm Co., Ltd. | Semiconductor integrated circuit device, magnetic disk storage device, and electronic apparatus |
US11146257B2 (en) * | 2019-12-04 | 2021-10-12 | Denso International America, Inc. | Latching DC switch circuit with overcurrent protection using field effect transistors |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ATE67617T1 (de) * | 1985-08-26 | 1991-10-15 | Siemens Ag | Integrierte schaltung in komplementaerer schaltungstechnik mit einem substratvorspannungs- generator. |
US5140177A (en) * | 1988-12-02 | 1992-08-18 | Mitsubishi Denki Kabushiki Kaisha | Complementary circuit device returnable to normal operation from latch-up phenomenon |
JPH03108368A (ja) * | 1989-09-21 | 1991-05-08 | Mitsubishi Electric Corp | 相補型回路 |
JPH04167557A (ja) * | 1990-10-31 | 1992-06-15 | Fujitsu Ltd | 半導体集積回路 |
US5212616A (en) * | 1991-10-23 | 1993-05-18 | International Business Machines Corporation | Voltage regulation and latch-up protection circuits |
US5543650A (en) * | 1995-01-12 | 1996-08-06 | International Business Machines Corporation | Electrostatic discharge protection circuit employing a mosfet device |
JPH08255872A (ja) * | 1995-03-16 | 1996-10-01 | Mitsubishi Electric Corp | 半導体集積回路の設計方法及び半導体集積回路装置及びプリント配線板アッセンブリ及びラッチアップ復旧方法 |
JP2907082B2 (ja) | 1995-10-23 | 1999-06-21 | 日本電気株式会社 | Cmos集積回路 |
US6359316B1 (en) * | 1997-09-19 | 2002-03-19 | Cypress Semiconductor Corp. | Method and apparatus to prevent latch-up in CMOS devices |
US7145191B1 (en) * | 2000-03-31 | 2006-12-05 | National Semiconductor Corporation | P-channel field-effect transistor with reduced junction capacitance |
US7221027B2 (en) * | 2004-05-18 | 2007-05-22 | Winbond Electronics Corporation | Latchup prevention method for integrated circuits and device using the same |
JP4578878B2 (ja) * | 2004-07-27 | 2010-11-10 | パナソニック株式会社 | 半導体集積回路 |
US7348793B2 (en) * | 2006-01-19 | 2008-03-25 | International Business Machines Corporation | Method and apparatus for detection and prevention of bulk CMOS latchup |
DE602007005289D1 (de) * | 2006-01-24 | 2010-04-29 | St Microelectronics Sa | Schutzschaltung für eine integrierte Schaltung gegen parasitäre latch-up Phänomene |
JP5041760B2 (ja) * | 2006-08-08 | 2012-10-03 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
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2008
- 2008-08-12 JP JP2008208064A patent/JP5341426B2/ja not_active Expired - Fee Related
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2009
- 2009-08-11 US US12/539,251 patent/US8116050B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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US8116050B2 (en) | 2012-02-14 |
JP2010045182A (ja) | 2010-02-25 |
US20100039163A1 (en) | 2010-02-18 |
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