JP5297992B2 - 外部記憶装置 - Google Patents
外部記憶装置 Download PDFInfo
- Publication number
- JP5297992B2 JP5297992B2 JP2009284348A JP2009284348A JP5297992B2 JP 5297992 B2 JP5297992 B2 JP 5297992B2 JP 2009284348 A JP2009284348 A JP 2009284348A JP 2009284348 A JP2009284348 A JP 2009284348A JP 5297992 B2 JP5297992 B2 JP 5297992B2
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- Japan
- Prior art keywords
- storage device
- external storage
- semiconductor chip
- wiring board
- inductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000003860 storage Methods 0.000 title claims abstract description 204
- 239000004065 semiconductor Substances 0.000 claims abstract description 162
- 239000011347 resin Substances 0.000 claims abstract description 76
- 229920005989 resin Polymers 0.000 claims abstract description 76
- 238000007789 sealing Methods 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 230000001681 protective effect Effects 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 74
- 238000003780 insertion Methods 0.000 description 18
- 230000037431 insertion Effects 0.000 description 18
- 238000000034 method Methods 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 11
- 239000004020 conductor Substances 0.000 description 10
- 238000012986 modification Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/0949—Pad close to a hole, not surrounding the hole
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0228—Cutting, sawing, milling or shearing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
- H05K2203/1316—Moulded encapsulation of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
前記配線基板の第1面に配置された少なくとも一つの半導体チップと、
前記少なくとも一つの半導体チップのいずれかに設けられた記憶素子と、
前記少なくとも一つの半導体チップのいずれかに設けられ、前記記憶素子が記憶している情報を外部に通信するインダクタと、
前記少なくとも一つの半導体チップのいずれかに設けられ、前記インダクタを駆動するドライバ回路と、
前記配線基板に設けられた接触型の外部端子と、
前記配線基板の前記第1面に形成され、前記少なくとも一つの半導体チップを封止し、かつ前記外部端子を被覆していない封止樹脂層と、
を備え、
前記インダクタは、前記半導体チップのうち前記配線基板と対向しない面に形成されている外部記憶装置が提供される。
前記配線基板の第1面に封止樹脂層を、前記少なくとも一つの半導体チップを封止し、かつ前記外部端子を被覆しないように形成する工程と、
を備え、
前記少なくとも一つの半導体チップのいずれかには記憶素子が設けられており、
前記少なくとも一つの半導体チップのいずれかには、前記記憶素子が記憶している情報を外部に通信するインダクタが設けられており、
前記少なくとも一つの半導体チップのいずれかには前記インダクタのドライバ回路が設けられている外部記憶装置の製造方法が提供される。
20 配線基板
21 段差
22 貫通ビア
24 貫通孔
26 導体膜
27 スルーホール
28 スルーホール
29 スルーホール
30 封止樹脂層
32 ガイド部
33 側面
34 ガイド部
36 凹部
37 溝
38 溝
40 外部端子
50 保護樹脂層
52 開口
60 保護樹脂層
62 開口
70 配線
72 配線
80 筐体
82 開口
84 開口
110 半導体チップ
112 ドライバ回路
114 インダクタ
120 半導体チップ
122 記憶素子
130 半導体チップ
140 支持部材
150 受動部品
210 ボンディングワイヤ
211 ボンディングワイヤ
212 ボンディングワイヤ
220 バンプ
400 ダイシングブレード
402 ダイシングブレード
404 ダイシングブレード
410 ダイシングブレード
420 ダイシングブレード
500 読取装置
502 差込穴
504 凸部
510 読取部
512 レシーバ回路
514 インダクタ
530 接続端子
600 上型
602 凸部
610 下型
Claims (14)
- 配線基板と、
前記配線基板の第1面に配置された少なくとも一つの半導体チップと、
前記少なくとも一つの半導体チップのいずれかに設けられた記憶素子と、
前記少なくとも一つの半導体チップのいずれかに設けられ、前記記憶素子が記憶している情報を外部に通信するインダクタと、
前記少なくとも一つの半導体チップのいずれかに設けられ、前記インダクタを駆動するドライバ回路と、
前記配線基板に設けられた接触型の外部端子と、
前記配線基板の前記第1面に形成され、前記少なくとも一つの半導体チップを封止し、かつ前記外部端子を被覆していない封止樹脂層と、
を備え、
前記インダクタは、前記半導体チップのうち前記配線基板と対向しない面に形成されており、
前記封止樹脂層は、平面視で前記インダクタと重なる領域に凹部を有している外部記憶装置。 - 配線基板と、
前記配線基板の第1面に配置された少なくとも一つの半導体チップと、
前記少なくとも一つの半導体チップのいずれかに設けられた記憶素子と、
前記少なくとも一つの半導体チップのいずれかに設けられ、前記記憶素子が記憶している情報を外部に通信するインダクタと、
前記少なくとも一つの半導体チップのいずれかに設けられ、前記インダクタを駆動するドライバ回路と、
前記配線基板に設けられた接触型の外部端子と、
前記配線基板の前記第1面に形成され、前記少なくとも一つの半導体チップを封止し、かつ前記外部端子を被覆していない封止樹脂層と、
前記配線基板及び前記封止樹脂層を内側に含む筐体と、
前記筐体のうち前記配線基板の前記第1面と対向する領域に設けられ、前記外部端子及び前記インダクタと重なる開口部と、
を備え、
前記インダクタは、前記半導体チップのうち前記配線基板と対向しない面に形成されている外部記憶装置。 - 請求項1又は2に記載の外部記憶装置において、
前記外部端子は、少なくとも前記ドライバ回路に電力を供給する電源端子である外部記憶装置。 - 請求項1〜3のいずれか一項に記載の外部記憶装置において、
前記インダクタの直径は1mm以下である外部記憶装置。 - 請求項1〜4のいずれか一つに記載の外部記憶装置において、
カード型である外部記憶装置。 - 請求項1〜5のいずれか一つに記載の外部記憶装置において、
前記封止樹脂層を用いて設けられた凹凸であるガイド部をさらに備える外部記憶装置。 - 請求項6に記載の外部記憶装置において、
前記外部記憶装置の平面形状は略長方形又は略正方形であり、
前記ガイド部は、前記外部記憶装置の互いに対向している2つの側面に形成されている外部記憶装置。 - 請求項1〜7のいずれか一つに記載の外部記憶装置において、
前記少なくとも一つの半導体チップとして、第1の半導体チップと第2の半導体チップを有しており、
前記第1の半導体チップは前記インダクタ及び前記ドライバ回路を有しており、
前記第2の半導体チップは前記記憶素子を有しており、
前記第1の半導体チップと前記第2の半導体チップは前記配線基板を介して互いに接続している外部記憶装置。 - 請求項8に記載の外部記憶装置において、
前記第1の半導体チップと前記配線基板の前記第1面との間に位置する支持部材を備え、
前記第1の半導体チップは、前記インダクタ及び前記ドライバ回路を有する能動面を前期第1面とは逆側に向けて配置されている外部記憶装置。 - 請求項1〜9のいずれか一つに記載の外部記憶装置において、
前記記憶素子は不揮発性である外部記憶装置。 - 請求項1〜10のいずれか一つに記載の外部記憶装置において、
前記外部端子は前記配線基板の前記第1面に設けられている外部記憶装置。 - 請求項1〜10のいずれか一つに記載の外部記憶装置において、
前記外部端子は前記配線基板の前記第1面とは逆側の面である第2面に形成されている外部記憶装置。 - 請求項1〜12のいずれか一つに記載の外部記憶装置において、
前記配線基板に形成されている位置合わせ用の貫通孔を備えている外部記憶装置。 - 請求項13に記載の外部記憶装置において、
前記配線基板の前記第1面を被覆する第1保護絶縁層と、
前記配線基板の前記第1面とは逆側の面である第2面を被覆する第2保護絶縁層と、
前記第1保護絶縁層に設けられ、前記貫通孔を露出する第1開口と、
前記第2保護絶縁層に設けられ、前記貫通孔を露出する第2開口と、
を備える外部記憶装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009284348A JP5297992B2 (ja) | 2009-12-15 | 2009-12-15 | 外部記憶装置 |
US12/926,710 US8705238B2 (en) | 2009-12-15 | 2010-12-06 | External storage device and method of manufacturing external storage device |
CN201410409959.0A CN104253101B (zh) | 2009-12-15 | 2010-12-15 | 外部存储装置 |
CN201010597887.9A CN102130103B (zh) | 2009-12-15 | 2010-12-15 | 外部存储装置和制造外部存储装置的方法 |
US14/203,037 US9666659B2 (en) | 2009-12-15 | 2014-03-10 | External storage device and method of manufacturing external storage device |
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Application Number | Priority Date | Filing Date | Title |
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JP2009284348A JP5297992B2 (ja) | 2009-12-15 | 2009-12-15 | 外部記憶装置 |
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JP2013104757A Division JP2013175233A (ja) | 2013-05-17 | 2013-05-17 | 外部記憶装置 |
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JP2011128719A JP2011128719A (ja) | 2011-06-30 |
JP5297992B2 true JP5297992B2 (ja) | 2013-09-25 |
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US (2) | US8705238B2 (ja) |
JP (1) | JP5297992B2 (ja) |
CN (2) | CN104253101B (ja) |
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-
2009
- 2009-12-15 JP JP2009284348A patent/JP5297992B2/ja not_active Expired - Fee Related
-
2010
- 2010-12-06 US US12/926,710 patent/US8705238B2/en active Active
- 2010-12-15 CN CN201410409959.0A patent/CN104253101B/zh not_active Expired - Fee Related
- 2010-12-15 CN CN201010597887.9A patent/CN102130103B/zh not_active Expired - Fee Related
-
2014
- 2014-03-10 US US14/203,037 patent/US9666659B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US9666659B2 (en) | 2017-05-30 |
US20110141681A1 (en) | 2011-06-16 |
CN102130103B (zh) | 2014-10-01 |
CN104253101A (zh) | 2014-12-31 |
CN102130103A (zh) | 2011-07-20 |
US20140191363A1 (en) | 2014-07-10 |
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JP2011128719A (ja) | 2011-06-30 |
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