JP5292452B2 - 発光装置、モジュール、及び電子機器 - Google Patents
発光装置、モジュール、及び電子機器 Download PDFInfo
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- JP5292452B2 JP5292452B2 JP2011272981A JP2011272981A JP5292452B2 JP 5292452 B2 JP5292452 B2 JP 5292452B2 JP 2011272981 A JP2011272981 A JP 2011272981A JP 2011272981 A JP2011272981 A JP 2011272981A JP 5292452 B2 JP5292452 B2 JP 5292452B2
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Description
一方、アクティブマトリクス型の場合は、各画素にTFTを有し、各画素内で信号を保持出来るようになっている。
において、1501は、画素に信号を書き込む時のスイッチング素子として機能するTFT(以下、スイッチング用TFTという)である。図15(B)では、スイッチング用TFTはダブルゲート構造となっているが、シングルゲート構造あるいはトリプルゲート構造やそれ以上のゲート本数を持つマルチゲート構造をとっても良い。また、TFTの極性は回路の構成形態によっていずれかの極性を用いれば良い。1502はEL素子1503に供給する電流を制御するための素子(電流制御素子)として機能するTFT(以下、EL駆動用TFTという)である。図15(B)では、EL素子1503の陽極1509と電流供給線1507との間に配置されている。別の構成方法として、EL素子1503の陰極1510と陰極電極1508の間に配置したりすることも可能である。また、TFTの極性は回路の構成形態によっていずれかの極性を用いれば良い。ただし、トランジスタの動作としてソース接地が良いこと、EL素子1503の製造上の制約などから、EL駆動用TFTにはpチャネル型を用い、EL素子1503の陽極1509と電流供給線1507との間にEL駆動用TFTを配置する方式が一般的であり、多く採用されている。1504は、ソース信号線1506から入力される信号(電圧)を保持するための保持容量である。図15(B)での保持容量1504の一方の端子は、電流供給線1507に接続されているが、専用の配線を用いることもある。スイッチング用TFT1501のゲート端子は、ゲート信号線1505に、ソース端子は、ソース信号線1506に接続されている。また、EL駆動用TFT1502のドレイン端子はEL素子1503の陽極1509に、ソース端子は電流供給線1507に接続されている。
図1(B)中、101はスイッチング用TFT、102はEL駆動用TFT、103はEL画素、104は保持容量、105はソース信号線、106はi行目に走査されるゲート信号線、108は陰極配線、109はEL画素の陽極、110はEL画素の陰極、111は隣り合う1行前の行のゲート信号線である。スイッチングTFT101,201は、前述したように、EL素子の構造に応じて極性を決定すれば良い。
スイッチング用TFTは、pチャネル型であるので、ゲート信号線の電位がスイッチング用TFTのソース領域の電位よりも十分に低い(つまりスイッチング用TFTのゲート・ソース間電圧の絶対値がしきい値電圧を上回る)ときに、スイッチング用TFTは導通状態となる。その時のゲート信号線の電位は、ソース信号線の電圧が画素に書き込まれるようにするため、ソース信号線での最も低い電位よりも十分低くしておく必要がある。まず、i−1行目では、期間Bにおいて、ゲート信号線が選択される。i行目では、期間Cにおいて選択され、i+1行目では、期間Dにおいて選択され、i+2行目では、期間Eにおいて選択される。このように、各行において、ゲート信号線が選択されて、次の行へシフトしていく。
従って、期間Bにおいても、EL駆動用TFTのゲート電極の電位は下がったが、同時に、EL駆動用TFTのソース電極の電位も下がるため、EL駆動用TFTのゲート・ソース間電圧は、期間Aと期間Bとでは、同じである。よって、期間Bにおいては、i行目の画素のEL素子には、電流は流れない。また、たとえ、EL駆動用TFTが導通状態にあったとしても、期間Bでは、EL駆動用TFTのソース電極の電位は下がり、EL素子の陰極配線の電位よりも低くなることが想定されるため、EL素子には、順バイアスの電圧はかからなくなるため、電流は流れなくなる。そして、期間Bの最後において、i−1行目のゲート信号線の電圧が元に戻る。その結果、i行目の画素のEL駆動用TFTのゲート電極の電位も元に戻る。
よって、i+1行目の画素のEL駆動用TFTのゲート電極の電位は、ソース信号線の電位と同じになる。期間Dでは、ソース信号線は、H信号の状態にあるとしている。よって、i+1行目の画素のEL駆動用TFTのゲート電極の電位も、ソース信号線と同電位となり、高くなる。その時、保持容量の片方の電極、つまり、i行目のゲート信号線の電位は、すでに高い状態に戻っている。よって、保持容量には、i行目のゲート信号線とi+1行目の画素のEL駆動用TFTのゲート電極との間の電圧が加わることになり、EL駆動用TFTのゲート・ソース間電圧の絶対値は小さくなる。従って、i+1行目の画素のEL駆動用TFTは非導通状態になり、i+1行目のEL素子に電流が流れず、発光しない。
よって、i+2行目の画素のEL駆動用TFTのゲート電極の電位は、ソース信号線の電位と同じになる。期間Eでは、ソース信号線は、L信号の状態にあるとしている。よって、i+2行目の画素のEL駆動用TFTのゲート電極の電位も、ソース信号線と同電位となり、低くなる。その時、保持容量の片方の電極、つまり、i+1行目のゲート信号線の電位は、すでに高い状態に戻っている。よって、保持容量には、i+1行目のゲート信号線とi+2行目の画素のEL駆動用TFTのゲート電極との間の電圧が加わることになり、EL駆動用TFTのゲート・ソース間電圧の絶対値は大きくなる。従って、i+2行目の画素のEL駆動用TFTは導通状態になり、i+2行目のEL素子に電流が流れ、発光する。i+2行目のEL素子を流れる電流は、i+1行目のゲート信号線を通して供給される。
そして、アドレス期間Ta3が終了し、次のアドレス期間Ta1が開始すると、通常の動作に戻していく。これにより、サステイン期間Ts3の長さを制御することが出来る。このように、一つ前の行のゲート信号線の電位を上げておき、非表示期間を設ける期間を、クリア期間(Tcn n:サブフレーム期間に付された番号)と呼ぶことにする。
例えば、プラズマCVD法でSiH4、NH3、N2Oから作製される酸化窒化シリコン膜5002aを10〜200[nm](好ましくは50〜100[nm])形成し、同様にSiH4、N2Oから作製される酸化窒化水素化シリコン膜5002bを50〜200[nm](好ましくは100〜150[nm])の厚さに積層形成する。本実施例では下地膜5002を2層構造として示したが、前記絶縁膜の単層膜または2層以上積層させた構造として形成しても良い。
このようにして作製される酸化シリコン膜は、その後400〜500[℃]の熱アニールによりゲート絶縁膜として良好な特性を得ることが出来る。
(図8(A))
ドーピングの方法はイオンドープ法若しくはイオン注入法で行えば良い。イオンドープ法の条件はドーズ量を1×1013〜5×1014[atoms/cm2]とし、加速電圧を60〜100[keV]として行う。n型を付与する不純物元素として15族に属する元素、典型的にはリン(P)または砒素(As)を用いるが、ここではリン(P)を用いる。この場合、導電層5011〜5015がn型を付与する不純物元素に対するマスクとなり、自己整合的に第1の不純物領域5017〜5025が形成される。第1の不純物領域5017〜5025には1×1020〜1×1021[atoms/cm3]の濃度範囲でn型を付与する不純物元素を添加する。(図8(B))
基板側(試料ステージ)には50[W]のRF(13.56[MHz])電力を投入し、第1のエッチング処理に比べ低い自己バイアス電圧を印加する。このような条件によりW膜を異方性エッチングし、かつ、それより遅いエッチング速度で第1の導電層であるTaを異方性エッチングして第2の形状の導電層5026〜5031(第1の導電層5026a〜5031aと第2の導電層5026b〜5031b)を形成する。ゲート絶縁膜5007は、第2の形状の導電層5026〜5031で覆われない領域はさらに20〜50[nm]程度エッチングされ、薄くなった領域が形成される。(図8(C))
、エポキシ樹脂、シリコン樹脂、PVB(ポリビニルブチラル)またはEVA(エチレンビニルアセテート)を用いることができる。この充填材4023の内部に乾燥剤を設けておくと、吸湿効果を保持できるので好ましい。また充填材4023の内部に、酸素を捕捉する効果を有する酸化防止剤等を配置することで、EL層の劣化を抑えても良い。
と同じ番号のものは同じ部分を指しているので説明は省略する。
を用いることができる。この充填材4023の内部に乾燥剤を設けておくと、吸湿効果を保持できるので好ましい。また充填材4023の内部に、酸素を捕捉する効果を有する酸化防止剤等を配置することで、EL層の劣化を抑えても良い。
(T.Tsutsui, C.Adachi, S.Saito, Photochemical Processes in Organized Molecular Systems, ed.K.Honda,(Elsevier Sci.Pub., Tokyo,1991)p.437.)
上記の論文により報告されたEL材料(クマリン色素)の分子式を以下に示す。
上記の論文により報告されたEL材料(Pt錯体)の分子式を以下に示す。
(T.Tsutsui, M.J.Yang, M.Yahiro, K.Nakamura, T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38(12B)(1999)L1502.)
上記の論文により報告されたEL材料(Ir錯体)の分子式を以下に示す。
であり、本体3331、記録媒体(DVD等)3332、操作スイッチ3333、表示部(a)3334、表示部(b)3335等を含む。表示部(a)3334は主として画像情報を表示し、表示部(b)3335は主として文字情報を表示するが、本発明の電子装置はこれら表示部(a)3334、表示部(b)3335に用いることが出来る。なお、記録媒体を備えた画像再生装置には家庭用ゲーム機器なども含まれる。
Claims (6)
- 第1及び第2のトランジスタと、第1乃至第6の導電層と、発光素子と、を有し、
前記第1のトランジスタのゲート電極は、前記第1の導電層に電気的に接続され、
前記第1のトランジスタのソース又はドレインの一方は、前記第2の導電層を介して前記第3の導電層に電気的に接続され、
前記第1のトランジスタのソース又はドレインの他方は、前記第4の導電層を介して前記第2のトランジスタのゲート電極に電気的に接続され、
前記第2のトランジスタのソース又はドレインの一方は、前記第5の導電層を介して前記発光素子の陽極に電気的に接続され、
前記第2のトランジスタのソース又はドレインの他方は、前記第6の導電層に電気的に接続され、
前記第1の導電層と前記第6の導電層とは、第1の方向に延びて設けられ、
前記第3の導電層は、前記第1の方向と交差する第2の方向に延びて設けられ、
前記第1のトランジスタのゲート電極、前記第2のトランジスタのゲート電極及び前記第3の導電層は、第1の導電膜をエッチング加工することによって形成されたものであり、
前記第1の導電層、前記第2の導電層、前記第4の導電層、前記第5の導電層及び前記第6の導電層は、第2の導電膜をエッチング加工することによって形成されたものであり、
前記第1のトランジスタのゲート電極、前記第2のトランジスタのゲート電極及び前記第3の導電層は、前記第1の導電層、前記第2の導電層、前記第4の導電層、前記第5の導電層及び前記第6の導電層よりも先に形成されたものであることを特徴とする発光装置。 - 第1及び第2のトランジスタと、第1乃至第6の導電層と、発光素子と、を有し、
前記第1のトランジスタのゲート電極は、前記第1の導電層に電気的に接続され、
前記第1のトランジスタのソース又はドレインの一方は、前記第2の導電層を介して前記第3の導電層に電気的に接続され、
前記第1のトランジスタのソース又はドレインの他方は、前記第4の導電層を介して前記第2のトランジスタのゲート電極に電気的に接続され、
前記第2のトランジスタのソース又はドレインの一方は、前記第5の導電層を介して前記発光素子の陰極に電気的に接続され、
前記第2のトランジスタのソース又はドレインの他方は、前記第6の導電層に電気的に接続され、
前記第1の導電層と前記第6の導電層とは、第1の方向に延びて設けられ、
前記第3の導電層は、前記第1の方向と交差する第2の方向に延びて設けられ、
前記第1のトランジスタのゲート電極、前記第2のトランジスタのゲート電極及び前記第3の導電層は、第1の導電膜をエッチング加工することによって形成されたものであり、
前記第1の導電層、前記第2の導電層、前記第4の導電層、前記第5の導電層及び前記第6の導電層は、第2の導電膜をエッチング加工することによって形成されたものであり、
前記第1のトランジスタのゲート電極、前記第2のトランジスタのゲート電極及び前記第3の導電層は、前記第1の導電層、前記第2の導電層、前記第4の導電層、前記第5の導電層及び前記第6の導電層よりも先に形成されたものであることを特徴とする発光装置。 - 請求項1又は請求項2に記載の前記発光装置を有するモジュール。
- 請求項1又は請求項2に記載の前記発光装置と、フレキシブルプリントサーキットと、を有するモジュール。
- 請求項1又は請求項2に記載の前記発光装置を有する電子機器。
- 請求項1又は請求項2に記載の前記発光装置と、音声入力部と、音声出力部と、アンテナと、を有する電子機器。
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TW507258B (en) * | 2000-02-29 | 2002-10-21 | Semiconductor Systems Corp | Display device and method for fabricating the same |
JP2001318627A (ja) * | 2000-02-29 | 2001-11-16 | Semiconductor Energy Lab Co Ltd | 発光装置 |
JP2001324958A (ja) | 2000-03-10 | 2001-11-22 | Semiconductor Energy Lab Co Ltd | 電子装置およびその駆動方法 |
US7129918B2 (en) * | 2000-03-10 | 2006-10-31 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and method of driving electronic device |
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TW521226B (en) * | 2000-03-27 | 2003-02-21 | Semiconductor Energy Lab | Electro-optical device |
JP3953715B2 (ja) * | 2000-07-31 | 2007-08-08 | 富士通株式会社 | 半導体装置及びその製造方法 |
TW466888B (en) * | 2000-09-29 | 2001-12-01 | Ind Tech Res Inst | Pixel device structure and process of organic light emitting diode display |
US6835954B2 (en) | 2001-12-29 | 2004-12-28 | Lg.Philips Lcd Co., Ltd. | Active matrix organic electroluminescent display device |
KR100484591B1 (ko) | 2001-12-29 | 2005-04-20 | 엘지.필립스 엘시디 주식회사 | 능동행렬 유기전기발광소자 및 그의 제조 방법 |
TWI255432B (en) * | 2002-06-03 | 2006-05-21 | Lg Philips Lcd Co Ltd | Active matrix organic electroluminescent display device and fabricating method thereof |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2013127632A (ja) * | 2000-03-27 | 2013-06-27 | Semiconductor Energy Lab Co Ltd | 発光装置 |
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