JP5238182B2 - 積層配線基板の製造方法 - Google Patents
積層配線基板の製造方法 Download PDFInfo
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- JP5238182B2 JP5238182B2 JP2007110046A JP2007110046A JP5238182B2 JP 5238182 B2 JP5238182 B2 JP 5238182B2 JP 2007110046 A JP2007110046 A JP 2007110046A JP 2007110046 A JP2007110046 A JP 2007110046A JP 5238182 B2 JP5238182 B2 JP 5238182B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 239000000758 substrate Substances 0.000 claims description 227
- 239000000463 material Substances 0.000 claims description 151
- 239000004065 semiconductor Substances 0.000 claims description 134
- 239000010410 layer Substances 0.000 claims description 121
- 238000000034 method Methods 0.000 claims description 52
- 239000012790 adhesive layer Substances 0.000 claims description 41
- 239000011347 resin Substances 0.000 claims description 33
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- 230000010354 integration Effects 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229920001721 polyimide Polymers 0.000 description 19
- 239000011889 copper foil Substances 0.000 description 11
- 239000009719 polyimide resin Substances 0.000 description 9
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- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
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- 230000001070 adhesive effect Effects 0.000 description 7
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- 229910000679 solder Inorganic materials 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
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- 239000002243 precursor Substances 0.000 description 6
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
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- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- BVKZGUZCCUSVTD-UHFFFAOYSA-N carbonic acid Chemical compound OC(O)=O BVKZGUZCCUSVTD-UHFFFAOYSA-N 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000002985 plastic film Substances 0.000 description 2
- 229920006255 plastic film Polymers 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
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- 125000006850 spacer group Chemical group 0.000 description 2
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- 229920001187 thermosetting polymer Polymers 0.000 description 2
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- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- 238000007766 curtain coating Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920006259 thermoplastic polyimide Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本発明に係る積層配線基板の製造方法において、前記(E)の工程で使用される導電性ペーストは、前記貫通電極と前記再配線層との押し付け接続の際、前記貫通電極と前記再配線層との接続抵抗を低くし、前記半導体素子への損傷を軽減するために、前記導電性ペーストに含まれるバインダ樹脂の粘度が調整されることを特徴とする。
に示す工程では、例えばポリイミド樹脂フィルムからなるフレキシブルな第1絶縁基板1aの一方の面(上面)に銅箔製の配線材料層1Bが設けられた片面銅張板(CCL)を用意する。前記第1絶縁基板1a及び配線材料層1Bにはそれぞれ厚さ25μm及び9μmのものを使用した。
1a、1d、2a、4a 絶縁基板
1b、1f、2b、4b、4c、 配線層
1c、1g、2c、 貫通電極
2、2x 第2基板材
3、30、31 半導体素子
3a 半導体基板
3b 電極パツト
3c 保護絶縁膜
3d、3f 有機絶縁膜(第1絶縁層)
3e 再配線層
3h 裏面有機絶縁膜(第2絶縁層)
4、4x 第3基板材
5 接着層材5
1e、5a、5b、 接着層
Claims (2)
- (A)半導体基板の一方の面に形成された電極パッド及び前記電極パッドに対するコンタクト孔を有する保護絶縁膜と、前記保護絶縁膜上に形成され前記電極パッドに接続された再配線層及び前記再配線層形成用の第1絶縁膜と、前記半導体基板の他方の面に形成された第2絶縁膜とを備え、前記第1絶縁膜及び前記第2絶縁膜が、同一種類の有機樹脂材料を用いて形成されていると共に、前記半導体基板の両表面の引張応力が均衡するように前記第1絶縁膜及び前記第2絶縁膜の厚さが相互に調整された半導体素子を提供する工程と、
(B)第1基板材を作成するために、絶縁基板の一方の面に配線層をパターンニング形成して配線基板を形成する工程と、
(C)前記絶縁基板の他方の面に接着層及び樹脂フィルムを順次重ねて貼り合わせる工程と、
(D)前記半導体素子の再配線層及び前記配線層の一部に対応する位置関係にあって前記絶縁基板、前記接着層及び前記樹脂フィルムを前記絶縁基板の他方の面側から貫通する貫通孔を形成する工程と、
(E)前記貫通孔に導電性ペーストを充填した後に前記樹脂フィルムを剥離して、一端面が前記配線層に接続され他端面が前記絶縁基板の他方の面から突出した状態で露出された貫通電極を形成する工程と、
(F)前記貫通電極の前記他端面を前記半導体素子の再配線層に位置合わせして押し付け接続し、前記半導体素子を前記接着層に仮止め接着して前記第1基板材と一体化する工程と、
(G)前記第1基板材に対面させる第2基板材を提供する工程と、
(H)前記第1基板材と一体化された前記半導体素子を前記第2基板材上に位置合わせして重ね合わせる工程と、
(I)前記第1基板材と前記第2基板材とを重ね合わせ方向に一括加熱プレスし、前記接着層により前記半導体素子を囲み前記第1及び第2基板材を相互接着する工程と、
を備え、
前記(F)の一体化する工程で前記貫通電極の前記他端面を前記半導体素子の再配線層に位置合わせして押し付け接続するときに、前記貫通電極と前記再配線層の低抵抗接続及び前記半導体素子の損傷回避が得られるように押圧力を調整するために、前記(C)の工程における前記樹脂フィルムの厚みを選定して、前記(D)の工程における前記貫通電極の突出高さを調整することを特徴とする積層配線基板の製造方法。 - 前記(E)の工程で使用される導電性ペーストは、
前記貫通電極と前記再配線層との押し付け接続の際、前記貫通電極と前記再配線層との接続抵抗を低くし、前記半導体素子への損傷を軽減するために、前記導電性ペーストに含まれるバインダ樹脂の粘度が調整されることを特徴とする請求項1に記載の積層配線基板の製造方法。
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WO2010103695A1 (ja) * | 2009-03-09 | 2010-09-16 | 株式会社村田製作所 | 部品内蔵モジュールの製造方法及び部品内蔵モジュール |
KR101004216B1 (ko) | 2009-08-31 | 2010-12-24 | 주식회사 심텍 | 초슬림 회로 기판이 접합된 칩 내장형 인쇄회로기판 제조방법 |
WO2011108308A1 (ja) | 2010-03-04 | 2011-09-09 | 日本電気株式会社 | 半導体素子内蔵配線基板 |
JP2013041926A (ja) * | 2011-08-12 | 2013-02-28 | Fujikura Ltd | 部品内蔵基板の製造方法 |
JP5352748B1 (ja) * | 2012-10-26 | 2013-11-27 | Jx日鉱日石金属株式会社 | キャリア付銅箔、それを用いた銅張積層板、プリント配線板、プリント回路板、及び、プリント配線板の製造方法 |
JP7224138B2 (ja) * | 2018-10-23 | 2023-02-17 | 株式会社ダイセル | 半導体装置製造方法 |
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JP3619395B2 (ja) * | 1999-07-30 | 2005-02-09 | 京セラ株式会社 | 半導体素子内蔵配線基板およびその製造方法 |
JP4394266B2 (ja) * | 2000-09-18 | 2010-01-06 | カシオ計算機株式会社 | 半導体装置および半導体装置の製造方法 |
JP3882540B2 (ja) * | 2001-07-04 | 2007-02-21 | 株式会社デンソー | プリント基板の製造方法およびその製造方法によって形成されるプリント基板 |
JP4254183B2 (ja) * | 2002-09-17 | 2009-04-15 | 株式会社デンソー | プリント配線基板およびプリント配線基板管理システム |
KR100784454B1 (ko) * | 2003-11-07 | 2007-12-11 | 신꼬오덴기 고교 가부시키가이샤 | 전자 장치 및 그 제조 방법 |
JP2005191156A (ja) * | 2003-12-25 | 2005-07-14 | Mitsubishi Electric Corp | 電気部品内蔵配線板およびその製造方法 |
JP2006253328A (ja) * | 2005-03-09 | 2006-09-21 | Fujikura Ltd | 多層配線基板の製造方法 |
JP4725178B2 (ja) * | 2005-04-28 | 2011-07-13 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
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