JP5208936B2 - チップ製造および設計における改良のための方法および装置 - Google Patents
チップ製造および設計における改良のための方法および装置 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title description 5
- 238000002161 passivation Methods 0.000 claims description 42
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 230000008569 process Effects 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 6
- 239000012768 molten material Substances 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000010410 layer Substances 0.000 description 53
- 239000000523 sample Substances 0.000 description 11
- 238000012360 testing method Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000004873 anchoring Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 235000012489 doughnuts Nutrition 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
Claims (6)
- 1つ以上のホールを備えた上部金属表面を有する半導体チップに対しボンドパッドを固定する方法において、
上部金属表面の上にパッシベーション層を形成するパッシベーション層形成工程と、
パッシベーション層にホールを有するようにパッシベーション層をパターン形成する工程であって、同ホールは上側金属層のホールに対応し、上側金属層のホール以下のサイズであるパターン形成工程と、
パッシベーション層の上にボンドパッドを形成するボンドパッド形成工程と、を備え、
ボンドパッド形成工程は、ボンドパッドを形成するとき、ボンドパッドからの材料の一部をパッシベーション層および上側金属層のホールへ導入することによって、ボンドパッドをパッシベーション層に対し固定する材料導入工程を含む方法。 - 材料導入工程は、溶融した材料がホールへ入りパッシベーション層の下側に沿って流動するように、溶融した材料をパッシベーション層に適用し、前記材料をパッシベーション層の表面の下へ流動させ、上側金属層に取り付けずにパッシベーション層に取り付けることによって、固定手段を形成する工程をさらに備える請求項1に記載の方法。
- パッシベーション層形成工程は、前記金属層のホールより小さいホールを有するパッシベーション層を形成する工程を含む請求項1または2に記載の方法。
- パターン形成工程において、パッシベーション層に直線で囲まれた形のホールを形成する工程をさらに備える請求項1乃至3のいずれか一項に記載の方法。
- パターン形成工程において、パッシベーション層に円形のホールを形成する工程をさらに備える請求項1乃至3のいずれか一項に記載の方法。
- 1つ以上のホールを備える上部金属表面を有する半導体チップであって、
上側金属層のホールに対応し、上側金属層のホール以下のサイズである1つ以上のホールを有する、上部金属表面の上のパッシベーション層と、
パッシベーション層の上に形成されたボンドパッドと、を備え、
ボンドパッドは、ボンドパッドが形成されるとき、パッシベーション層および上側金属層のホールへ入り、ボンドパッドを固定する半導体チップ。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/IB2006/054088 WO2008015500A1 (en) | 2006-08-01 | 2006-08-01 | Method and apparatus for improvements in chip manufacture and design |
Publications (2)
Publication Number | Publication Date |
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JP2009545871A JP2009545871A (ja) | 2009-12-24 |
JP5208936B2 true JP5208936B2 (ja) | 2013-06-12 |
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Application Number | Title | Priority Date | Filing Date |
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JP2009522346A Active JP5208936B2 (ja) | 2006-08-01 | 2006-08-01 | チップ製造および設計における改良のための方法および装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7955973B2 (ja) |
JP (1) | JP5208936B2 (ja) |
TW (1) | TW200816337A (ja) |
WO (1) | WO2008015500A1 (ja) |
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JP2010093161A (ja) * | 2008-10-10 | 2010-04-22 | Panasonic Corp | 半導体装置 |
KR20120080923A (ko) * | 2011-01-10 | 2012-07-18 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
US8314026B2 (en) | 2011-02-17 | 2012-11-20 | Freescale Semiconductor, Inc. | Anchored conductive via and method for forming |
US9536833B2 (en) | 2013-02-01 | 2017-01-03 | Mediatek Inc. | Semiconductor device allowing metal layer routing formed directly under metal pad |
US9455226B2 (en) | 2013-02-01 | 2016-09-27 | Mediatek Inc. | Semiconductor device allowing metal layer routing formed directly under metal pad |
WO2014150393A2 (en) | 2013-03-15 | 2014-09-25 | Lazur Andrew J | Method for producing high strength ceramic matrix composites |
US9780051B2 (en) * | 2013-12-18 | 2017-10-03 | Nxp Usa, Inc. | Methods for forming semiconductor devices with stepped bond pads |
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EP3131118B1 (en) * | 2015-08-12 | 2019-04-17 | MediaTek Inc. | Semiconductor device allowing metal layer routing formed directly under metal pad |
JP6806252B2 (ja) * | 2017-07-13 | 2021-01-06 | 富士電機株式会社 | 半導体装置 |
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JP4267481B2 (ja) * | 2004-02-20 | 2009-05-27 | パナソニック株式会社 | 半導体装置 |
US7115985B2 (en) * | 2004-09-30 | 2006-10-03 | Agere Systems, Inc. | Reinforced bond pad for a semiconductor device |
US7741716B1 (en) * | 2005-11-08 | 2010-06-22 | Altera Corporation | Integrated circuit bond pad structures |
-
2006
- 2006-08-01 JP JP2009522346A patent/JP5208936B2/ja active Active
- 2006-08-01 US US12/375,854 patent/US7955973B2/en active Active
- 2006-08-01 WO PCT/IB2006/054088 patent/WO2008015500A1/en active Application Filing
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US7955973B2 (en) | 2011-06-07 |
WO2008015500A1 (en) | 2008-02-07 |
JP2009545871A (ja) | 2009-12-24 |
US20100019395A1 (en) | 2010-01-28 |
TW200816337A (en) | 2008-04-01 |
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