JP5207336B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5207336B2 JP5207336B2 JP2006155658A JP2006155658A JP5207336B2 JP 5207336 B2 JP5207336 B2 JP 5207336B2 JP 2006155658 A JP2006155658 A JP 2006155658A JP 2006155658 A JP2006155658 A JP 2006155658A JP 5207336 B2 JP5207336 B2 JP 5207336B2
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Description
1 SDRAMチップ(第1半導体チップ)
2 フラッシュメモリチップ(第2半導体チップ)
3 スペーサ
4 マイコンチップ(第3半導体チップ)
5 モジュール基板(配線基板)
6 封止樹脂
100 第5辺
102 第6辺
120 第7辺
121 第8辺
101、103 第3電極パッド
110、111 ボンディングワイヤ
200 第3辺
202 第4辺
220 第1辺
221 第2辺
201、203 第2電極パッド
210、211 ボンディングワイヤ
401、403、405、407 第1電極パッド
410、411、412、413 ボンディングワイヤ
501、504、506、509 第1ボンディングリード
502A、507A 第2ボンディングリード
502B、507B 第3ボンディングリード
Claims (9)
- 上面、前記上面に形成された複数の第1ボンディングリード、前記上面に形成された複数の第2ボンディングリード、および前記上面とは反対側の下面を有する配線基板と、
平面形状が矩形状から成る第1主面、前記第1主面に形成された複数の第1電極パッド、および前記第1主面とは反対側の第1裏面を有し、前記第1裏面が前記配線基板の前記上面と対向するように、前記配線基板の前記上面上に搭載された第1半導体チップと、
平面形状が矩形状から成る表面、および前記表面とは反対側の裏面を有し、前記裏面が前記第1半導体チップの前記第1主面と対向するように、前記第1半導体チップの前記第1主面上に搭載されたスペーサと、
平面形状が矩形状から成る第2主面、前記第2主面に形成された複数の第2電極パッド、および前記第2主面とは反対側の第2裏面を有し、前記第2裏面が前記スペーサの前記表面と対向するように、前記スペーサの前記表面上に搭載された第2半導体チップと、
前記複数の第1ボンディングリードと前記複数の第1電極パッドとをそれぞれ電気的に接続する複数の第1ボンディングワイヤと、
前記複数の第2ボンディングリードと前記複数の第2電極パッドとをそれぞれ電気的に接続する複数の第2ボンディングワイヤと、を含み、
前記配線基板の平面形状は、一対の第1辺と、前記第1辺と交差する一対の第2辺とを有する矩形状から成り、
前記複数の第1ボンディングリードは、前記第1辺に沿って形成され、
前記複数の第2ボンディングリードは、前記第2辺に沿って形成され、
前記第1半導体チップの平面形状は、一対の第3辺と、前記第3辺と交差する一対の第4辺とを有する矩形状から成り、
前記複数の第1電極パッドは、前記第3辺に沿って形成され、かつ、前記第4辺に沿って形成されていなく、
前記第1半導体チップは、前記第3辺が前記配線基板の前記第1辺と並ぶように、前記配線基板の前記上面上に搭載され、
前記スペーサの平面形状は、一対の第5辺と、前記第5辺とは交差する一対の第6辺とを有する矩形状から成り、
前記スペーサは、前記第5辺が前記配線基板の前記第1辺と並び、かつ前記複数の第1電極パッドが露出するように前記第5辺が前記第1半導体チップの前記第3辺よりも内側に位置し、かつ前記第6辺が前記第1半導体チップの前記第4辺よりも外側に位置するように、前記第1半導体チップの前記第1主面上に搭載され、
前記第2半導体チップの平面形状は、一対の第7辺と、前記第7辺とは交差する一対の第8辺とを有する矩形状から成り、
前記複数の第2電極パッドは、前記第8辺に沿って形成され、
前記第2半導体チップは、前記第7辺が前記配線基板の前記第1辺と並び、かつ前記第7辺が前記第1半導体チップの前記第3辺よりも内側に位置し、かつ前記第8辺が前記スペーサの前記第6辺よりも外側に位置するように、前記スペーサの前記表面上に搭載されていることを特徴とする半導体装置。 - 前記複数の第2電極パッドは、前記第2半導体チップの前記第2主面において、前記第7辺および前記第8辺のそれぞれに沿って形成されていることを特徴とする請求項1記載の半導体装置。
- 前記第1半導体チップ、前記スペーサおよび前記第2半導体チップは、封止樹脂で封止されており、
前記配線基板の前記下面には、複数のボール電極が形成されていることを特徴とする請求項2記載の半導体装置。 - 上面、前記上面に形成された複数の第1ボンディングリード、前記上面に形成された複数の第2ボンディングリード、および前記上面とは反対側の下面を有する配線基板と、
平面形状が矩形状から成る第1主面、前記第1主面に形成された複数の第1電極パッド、および前記第1主面とは反対側の第1裏面を有し、前記第1裏面が前記配線基板の前記上面と対向するように、前記配線基板の前記上面上に搭載された第1半導体チップと、
平面形状が矩形状から成る表面、および前記表面とは反対側の裏面を有し、前記裏面が前記第1半導体チップの前記第1主面と対向するように、前記第1半導体チップの前記第1主面上に搭載されたスペーサと、
平面形状が矩形状から成る第2主面、前記第2主面に形成された複数の第2電極パッド、および前記第2主面とは反対側の第2裏面を有し、前記第2裏面が前記スペーサの前記表面と対向するように、前記スペーサの前記表面上に搭載された第2半導体チップと、
前記複数の第1ボンディングリードと前記複数の第1電極パッドとをそれぞれ電気的に接続する複数の第1ボンディングワイヤと、
前記複数の第2ボンディングリードと前記複数の第2電極パッドとをそれぞれ電気的に接続する複数の第2ボンディングワイヤと、を含み、
前記配線基板の平面形状は、一対の第1辺と、前記第1辺と交差する一対の第2辺とを有する矩形状から成り、
前記複数の第1ボンディングリードは、前記第1辺に沿って形成され、
前記複数の第2ボンディングリードは、前記第2辺に沿って形成され、
前記第1半導体チップの平面形状は、一対の第3辺と、前記第3辺と交差する一対の第4辺とを有する矩形状から成り、
前記複数の第1電極パッドは、前記第3辺に沿って形成され、かつ、前記第4辺に沿って形成されていなく、
前記第1半導体チップは、前記第3辺が前記配線基板の前記第1辺と並ぶように、前記配線基板の前記上面上に搭載され、
前記スペーサの平面形状は、一対の第5辺と、前記第5辺とは交差する一対の第6辺とを有する矩形状から成り、
前記スペーサは、前記第5辺が前記配線基板の前記第1辺と並び、かつ前記複数の第1電極パッドが露出するように前記第5辺が前記第1半導体チップの前記第3辺よりも内側に位置し、かつ前記第6辺が前記第1半導体チップの前記第4辺よりも外側に位置するように、前記第1半導体チップの前記第1主面上に搭載され、
前記第2半導体チップの平面形状は、一対の第7辺と、前記第7辺とは交差する一対の第8辺とを有する矩形状から成り、
前記複数の第2電極パッドは、前記第8辺に沿って形成され、
前記第2半導体チップは、前記第7辺が前記配線基板の前記第1辺と並び、かつ前記第7辺が前記スペーサの前記第5辺よりも外側に位置し、かつ前記第8辺が前記スペーサの前記第6辺よりも外側に位置するように、前記スペーサの前記表面上に搭載されていることを特徴とする半導体装置。 - 前記複数の第2電極パッドは、前記第2半導体チップの前記第2主面において、前記第7辺および前記第8辺のそれぞれに沿って形成されていることを特徴とする請求項4記載の半導体装置。
- 前記第1半導体チップ、前記スペーサおよび前記第2半導体チップは、封止樹脂で封止されており、
前記配線基板の前記下面には、複数のボール電極が形成されていることを特徴とする請求項5記載の半導体装置。 - 上面、前記上面に形成された複数の第1ボンディングリード、前記上面に形成された複数の第2ボンディングリード、および前記上面とは反対側の下面を有する配線基板と、
平面形状が矩形状から成る第1主面、前記第1主面に形成された複数の第1電極パッド、および前記第1主面とは反対側の第1裏面を有し、前記第1裏面が前記配線基板の前記上面と対向するように、前記配線基板の前記上面上に搭載された第1半導体チップと、
平面形状が矩形状から成る表面、および前記表面とは反対側の裏面を有し、前記裏面が前記第1半導体チップの前記第1主面と対向するように、前記第1半導体チップの前記第1主面上に搭載されたスペーサと、
平面形状が矩形状から成る第2主面、前記第2主面に形成された複数の第2電極パッド、および前記第2主面とは反対側の第2裏面を有し、前記第2裏面が前記スペーサの前記表面と対向するように、前記スペーサの前記表面上に搭載された第2半導体チップと、
前記複数の第1ボンディングリードと前記複数の第1電極パッドとをそれぞれ電気的に接続する複数の第1ボンディングワイヤと、
前記複数の第2ボンディングリードと前記複数の第2電極パッドとをそれぞれ電気的に接続する複数の第2ボンディングワイヤと、を含み、
前記配線基板の平面形状は、一対の第1辺と、前記第1辺と交差する一対の第2辺とを有する矩形状から成り、
前記複数の第1ボンディングリードは、前記第1辺に沿って形成され、
前記複数の第2ボンディングリードは、前記第2辺に沿って形成され、
前記第1半導体チップの平面形状は、一対の第3辺と、前記第3辺と交差する一対の第4辺とを有する矩形状から成り、
前記複数の第1電極パッドは、前記第3辺に沿って形成され、かつ、前記第4辺に沿って形成されていなく、
前記第1半導体チップは、前記第3辺が前記配線基板の前記第1辺と並ぶように、前記配線基板の前記上面上に搭載され、
前記スペーサの平面形状は、一対の第5辺と、前記第5辺とは交差する一対の第6辺とを有する矩形状から成り、
前記スペーサは、前記第5辺が前記配線基板の前記第1辺と並び、かつ前記複数の第1電極パッドが露出するように前記第5辺が前記第1半導体チップの前記第3辺よりも内側に位置し、かつ前記第6辺が前記第1半導体チップの前記第4辺よりも外側に位置するように、前記第1半導体チップの前記第1主面上に搭載され、
前記第2半導体チップの平面形状は、一対の第7辺と、前記第7辺とは交差する一対の第8辺とを有する矩形状から成り、
前記複数の第2電極パッドは、前記第8辺に沿って形成され、
前記第2半導体チップは、前記第7辺が前記配線基板の前記第1辺と並び、かつ前記第7辺が前記第1半導体チップの前記第3辺よりも内側に位置し、かつ前記第7辺が前記スペーサの前記第5辺よりも外側に位置し、かつ前記第8辺が前記スペーサの前記第6辺よりも外側に位置するように、前記スペーサの前記表面上に搭載されていることを特徴とする半導体装置。 - 前記複数の第2電極パッドは、前記第2半導体チップの前記第2主面において、前記第7辺および前記第8辺のそれぞれに沿って形成されていることを特徴とする請求項7記載の半導体装置。
- 前記第1半導体チップ、前記スペーサおよび前記第2半導体チップは、封止樹脂で封止されており、
前記配線基板の前記下面には、複数のボール電極が形成されていることを特徴とする請求項8記載の半導体装置。
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