JP5162804B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5162804B2
JP5162804B2 JP2001277188A JP2001277188A JP5162804B2 JP 5162804 B2 JP5162804 B2 JP 5162804B2 JP 2001277188 A JP2001277188 A JP 2001277188A JP 2001277188 A JP2001277188 A JP 2001277188A JP 5162804 B2 JP5162804 B2 JP 5162804B2
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impurity diffusion
edge
field plate
active portion
diffusion region
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JP2003086815A (en
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学 武井
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、電力変換装置などに使用されるパワー半導体装置に関し、特にプレーナー型のフィールドプレート付きガードリング耐圧構造を有する半導体装置に関する。
【０００２】
【従来の技術】
図４は、従来のプレーナー型のフィールドプレート付きガードリング耐圧構造を有する半導体装置の概略を示す断面図である。図４に示すように、従来のガードリング耐圧構造では、ｎ-ドリフト層１１、ｐ+活性部不純物拡散領域１２および複数のｐ+ガードリング不純物拡散領域１３の上に、初期酸化膜１４および層間絶縁膜１５を介してフィールドプレート１６，１７ａ，１７ｂ，１７ｃ，１７ｄ，１７ｅが選択的に形成される。
【０００３】
活性部不純物拡散領域１２上のフィールドプレート１６は、初期酸化膜１４および層間絶縁膜１５を貫通して活性部不純物拡散領域１２に電気的に接続している。このフィールドプレート１６のエッジ側端部１８は、電圧印加時における空乏層中の等電位線の曲率半径を大きくして電界を緩和するため、活性部不純物拡散領域１２のエッジ側端部１９からはみ出している。各ガードリング不純物拡散領域１３上のフィールドプレート１７ａ，１７ｂ，１７ｃ，１７ｄ，１７ｅは初期酸化膜１４および層間絶縁膜１５を貫通してそれぞれのガードリング不純物拡散領域１３に電気的に接続している。
【０００４】
【発明が解決しようとする課題】
しかしながら、図４に示す構成のフィールドプレート付きガードリング耐圧構造ではつぎのような問題点がある。図５は、活性部不純物拡散領域１２上のフィールドプレート１６が活性部不純物拡散領域１２からはみ出している半導体装置（耐圧６５１Ｖ）の活性部とエッジとの境界近傍領域における等電位線の様子を模式的に示す図である。図６は、フィールドプレートがない半導体装置（耐圧７０３Ｖ）の活性部とエッジとの境界近傍領域における等電位線の様子を模式的に示す図である。図５および図６において、図４と同じ構成については同一の符号を付す。
【０００５】
フィールドプレート１６がある場合には活性部とそのすぐ隣のガードリング不純物拡散領域１３との間の領域は発生耐圧のボトルネックとなり、図５に示す破線領域の等電位線の曲率は、図６に示す破線領域の等電位線の曲率よりも大きくなり、耐圧が低下してしまう。したがって、フィールドプレート１６があると平面接合に極めて近い理想耐圧を発生するのは困難である。
【０００６】
それに対して、フィールドプレートのないガードリング構造の場合には、隣り合うガードリング不純物拡散領域の間隔を詰めることにより、上述した耐圧ボトルネックを解消することができる。しかし、この構造では、保護膜中の電荷集中を防止する作用を有するフィールドプレートがないため、耐圧構造の一部領域に表面電荷が蓄積し、その部分の耐圧が低下してしまうので、信頼性に劣るという問題点がある。
【０００７】
本発明は、上記問題点に鑑みてなされたものであって、平面接合に近い理想耐圧を発生する信頼性の高い耐圧構造を備えた半導体装置を提供することを目的とする。
【０００８】
【課題を解決するための手段】
上記目的を達成するため、本発明にかかる半導体装置は、プレーナー型のフィールドプレート付きガードリング耐圧構造を有し、その耐圧構造の活性部とエッジとの境界近傍領域において、酸化膜と、その酸化膜の上に設けられたＢＰＳＧよりなる層間絶縁膜を貫通して活性部不純物拡散領域に電気的に接続している第１のフィールドプレートと、層間絶縁膜を貫通して複数のガードリング不純物拡散領域の各々に電気的に接続している複数の第２のフィールドプレートとを有し、活性部内のフィールドプレートのエッジ側端部が活性部不純物拡散領域からはみ出ず、かつエッジ内のフィールドプレートの活性部側端部がガードリング不純物拡散領域からはみ出ない構成とすることを特徴とする。
【０００９】
この発明によれば、活性部とエッジとの境界近傍領域において、活性部内のフィールドプレートが活性部不純物拡散領域からエッジ側にはみ出ず、かつエッジ内のフィールドプレートがガードリング不純物拡散領域から活性部側にはみ出ないため、それら隣り合う活性部不純物拡散領域とガードリング不純物拡散領域との間隔を詰めることができ、それによって等電位線の曲率半径が大きくなり、耐圧のボトルネックが解消される。また、フィールドプレートがあるため、長期信頼性が確保される。
【００１０】
【発明の実施の形態】
以下に、本発明の実施の形態について図面を参照しつつ詳細に説明する。図１は、本発明にかかるプレーナー型のフィールドプレート付きガードリング耐圧構造を有する半導体装置の一例の概略を示す断面図である。この半導体装置では、活性部とエッジとの境界近傍領域において、最もエッジ寄りに位置するｐ+活性部不純物拡散領域２２はｎ-ドリフト層２１の活性部側の表面部分に形成されている。また、複数のｐ+ガードリング不純物拡散領域２３ａ，２３ｂ，２３ｃ，２３ｄ，２３ｅは、ドリフト層２１のエッジ側の表面部分の活性部とたとえばＡｌでできたチャネルストッパー３０との間に形成されている。
【００１１】
活性部不純物拡散領域２２上に選択的に形成されたたとえばＡｌでできたフィールドプレート（第１のフィールドプレート）２６は、初期酸化膜２４およびたとえばＢＰＳＧよりなる層間絶縁膜２５を貫通して活性部不純物拡散領域２２に電気的に接続している。この第１のフィールドプレート２６のエッジ側端部２８は活性部不純物拡散領域２２のエッジ側端部２９よりも活性部中央寄りに位置している。つまり、活性部不純物拡散領域２２上の第１のフィールドプレート２６は活性部不純物拡散領域２２のエッジ側端部２９からエッジ側にはみ出していない。
【００１２】
各ガードリング不純物拡散領域２３ａ，２３ｂ，２３ｃ，２３ｄ，２３ｅ上に選択的に形成されたフィールドプレート２７ａ，２７ｂ，２７ｃ，２７ｄ，２７ｅは初期酸化膜２４および層間絶縁膜２５を貫通してそれぞれのガードリング不純物拡散領域２３ａ，２３ｂ，２３ｃ，２３ｄ，２３ｅに電気的に接続している。最も活性部寄りに位置するガードリング不純物拡散領域２３ａ上のフィールドプレート（第２のフィールドプレート）２７ａの活性部側端部３１は、そのガードリング不純物拡散領域２３ａの活性部側端部３２よりもエッジ中央寄りに位置している。つまり、エッジ内の最も活性部寄りに位置するフィールドプレート２７ａは、最も活性部寄りに位置するガードリング不純物拡散領域２３ａの活性部側端部３２から活性部側にはみ出していない。
【００１３】
ここで、最もエッジ寄りに位置する活性部不純物拡散領域２２と、最も活性部寄りに位置するガードリング不純物拡散領域２３ａとの間のイオン注入窓の間隔は、従来のプレーナー型のフィールドプレート付きガードリング耐圧構造における間隔よりも狭く、特に限定しないが、たとえば１０μｍである。また、このガードリング不純物拡散領域２３ａ上のフィールドプレート２７ａは、その幅がたとえば３５μｍであり、隣り合う活性部側のフィールドプレート２６との間隔がたとえば４０μｍであり、エッジ内の、活性部側から２番目に位置するフィールドプレート２７ｂとの間隔がたとえば２０μｍである。
【００１４】
図２は、本発明にかかる半導体装置の第１の具体例の要部を示す断面図である。図２に示す構成の半導体装置はダイオードであり、活性部においてアノード電極４６がフィールドプレートとして活性部とエッジとの境界近傍領域に延びている。アノード電極４６のエッジ側端部４８は、アノード電極４６の下に位置するｐ型の活性部不純物拡散領域４２のエッジ側端部４９よりも活性部中央寄りに位置している。また、最も活性部に近いｐ型のガードリング不純物拡散領域４３上に位置するフィールドプレート４７の活性部側端部５１は、そのガードリング不純物拡散領域４３の活性部側端部５２よりもエッジ中央寄りに位置している。そして、活性部不純物拡散領域４２とガードリング不純物拡散領域４３との間のイオン注入窓の間隔は、従来のプレーナー型のフィールドプレート付きガードリング耐圧構造における間隔よりも狭い。なお、図２において符号４１はｎ-ドリフト層であり、符号４４は初期酸化膜であり、符号４５はＢＰＳＧよりなる層間絶縁膜である。
【００１５】
図３は、本発明にかかる半導体装置の第２の具体例の要部を示す断面図である。図３に示す構成の半導体装置は絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）またはＭＯＳＦＥＴであり、活性部においてゲートリング６６がフィールドプレートとして活性部とエッジとの境界近傍領域に設けられている。ゲートリング６６のエッジ側端部６８は、ゲートリング６６の下に位置するｐ型の活性部不純物拡散領域６２のエッジ側端部６９よりも活性部中央寄りに位置している。また、最も活性部に近いｐ型のガードリング不純物拡散領域６３上に位置するフィールドプレート６７の活性部側端部７１は、そのガードリング不純物拡散領域６３の活性部側端部７２よりもエッジ中央寄りに位置している。
【００１６】
そして、活性部不純物拡散領域６２とガードリング不純物拡散領域６３との間のイオン注入窓の間隔は、従来のプレーナー型のフィールドプレート付きガードリング耐圧構造における間隔よりも狭い。なお、図３において符号６１はｎ-ドリフト層であり、符号６４は初期酸化膜であり、符号６５はＢＰＳＧよりなる層間絶縁膜である。また、符号７３はｐ型のウェル、符号７４はｎ+ソース領域、符号７５はゲート絶縁層を介してのポリシリコン層、符号７６はＡｌでできた電極である。
【００１７】
上述した実施の形態によれば、活性部とエッジとの境界近傍領域において、活性部内のフィールドプレート２６のエッジ側端部２８が活性部不純物拡散領域２２からはみ出さず、かつエッジ内の、最も活性部寄りに位置するフィールドプレート２７ａの活性部側端部３１がその下のガードリング不純物拡散領域２３ａからはみ出さないため、それら隣り合う活性部不純物拡散領域２２とガードリング不純物拡散領域２３ａとの間隔を詰めることができ、それによって等電位線の曲率半径が大きくなり、耐圧のボトルネックを解消することができる。したがって、平面耐圧に近い高耐圧を発生させることができる。また、耐圧構造部の全体にわたってフィールドプレート２６，２７ａ，２７ｂ，２７ｃ，２７ｄ，２７ｅがあるため、表面電荷の蓄積が抑えられるので、長期にわたって高い信頼性が確保される。
【００１８】
以上において本発明は、上述した実施の形態に限らず、種々変更可能である。たとえば、上述した実施の形態において記載した寸法は一例であり、本発明はこれに限定されるものではない。また、エッジ内の、活性部側から２番目以降のフィールドプレート２７ｂ，２７ｃ，２７ｄ，２７ｅは、対応するガードリング不純物拡散領域２３ｂ，２３ｃ，２３ｄ，２３ｅからはみ出していてもよいし、はみ出していなくてもよい。また、本発明はｎ型とｐ型を反転させても成り立つ。
【００１９】
【発明の効果】
本発明によれば、活性部とエッジとの境界近傍領域において、隣り合う活性部不純物拡散領域とガードリング不純物拡散領域との間隔を詰めて等電位線の曲率半径を大きくし、耐圧のボトルネックを解消することによって、平面耐圧に近い高耐圧を発生させることができる。また、フィールドプレートがあるため長期にわたって高い信頼性が得られる。
【図面の簡単な説明】
【図１】本発明にかかるプレーナー型のフィールドプレート付きガードリング耐圧構造を有する半導体装置の一例の概略を示す断面図である。
【図２】本発明にかかる半導体装置の第１の具体例を示す要部断面図である。
【図３】本発明にかかる半導体装置の第２の具体例を示す要部断面図である。
【図４】従来のプレーナー型のフィールドプレート付きガードリング耐圧構造を有する半導体装置の要部を示す断面図である。
【図５】フィールドプレートを有する半導体装置の活性部とエッジとの境界近傍領域における等電位線の様子を模式的に示す図である。
【図６】フィールドプレートのない半導体装置の活性部とエッジとの境界近傍領域における等電位線の様子を模式的に示す図である。
【符号の説明】
２２，４２，６２ 活性部不純物拡散領域
２３ａ，４３，６３ ガードリング不純物拡散領域
２６ 第１のフィールドプレート
２７ａ，４７，６７ 第２のフィールドプレート
２８，４８，６８ 第１のフィールドプレートのエッジ側端部
２９，４９，６９ 活性部不純物拡散領域のエッジ側端部
３１，５１，７１ 第２のフィールドプレートの活性部側端部
３２，５２，７２ ガードリング不純物拡散領域の活性部側端部
４６ アノード電極（第１のフィールドプレート）
６６ ゲートリング（第１のフィールドプレート）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device used for a power conversion device and the like, and more particularly, to a semiconductor device having a guard type withstand voltage structure with a planar type field plate.
[0002]
[Prior art]
FIG. 4 is a cross-sectional view schematically showing a conventional semiconductor device having a guard type withstand voltage structure with a planar type field plate. As shown in FIG. 4, in the conventional guard ring breakdown voltage structure, initial oxide film 14 and interlayer are formed on n − drift layer 11, p + active portion impurity diffusion region 12 and a plurality of p + guard ring impurity diffusion regions 13. Field plates 16, 17a, 17b, 17c, 17d, and 17e are selectively formed through the insulating film 15.
[0003]
The field plate 16 on the active part impurity diffusion region 12 penetrates through the initial oxide film 14 and the interlayer insulating film 15 and is electrically connected to the active part impurity diffusion region 12. The edge 18 on the edge side of the field plate 16 protrudes from the edge 19 on the edge side of the active impurity diffusion region 12 in order to relax the electric field by increasing the radius of curvature of the equipotential lines in the depletion layer when a voltage is applied. ing. Field plates 17a, 17b, 17c, 17d, and 17e on each guard ring impurity diffusion region 13 penetrate through initial oxide film 14 and interlayer insulating film 15 and are electrically connected to each guard ring impurity diffusion region 13. .
[0004]
[Problems to be solved by the invention]
However, the guard ring withstand voltage structure with the field plate configured as shown in FIG. 4 has the following problems. FIG. 5 schematically shows the state of equipotential lines in the region near the boundary between the active portion and the edge of the semiconductor device (withstand voltage 651 V) in which the field plate 16 on the active portion impurity diffusion region 12 protrudes from the active portion impurity diffusion region 12. FIG. FIG. 6 is a diagram schematically showing equipotential lines in a region near the boundary between the active portion and the edge of a semiconductor device (withstand voltage 703 V) having no field plate. 5 and 6, the same components as those in FIG. 4 are denoted by the same reference numerals.
[0005]
When the field plate 16 is present, the region between the active portion and the guard ring impurity diffusion region 13 immediately adjacent thereto becomes a bottleneck of the generated breakdown voltage, and the curvature of the equipotential line in the broken line region shown in FIG. It becomes larger than the curvature of the equipotential line in the broken line area shown in FIG. Therefore, with the field plate 16, it is difficult to generate an ideal withstand voltage that is very close to planar bonding.
[0006]
On the other hand, in the case of a guard ring structure without a field plate, the above-described pressure bottleneck can be eliminated by reducing the distance between adjacent guard ring impurity diffusion regions. However, in this structure, since there is no field plate that has the function of preventing charge concentration in the protective film, surface charges are accumulated in a partial region of the breakdown voltage structure, and the breakdown voltage of that part is lowered. There is a problem that it is inferior.
[0007]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having a highly reliable breakdown voltage structure that generates an ideal breakdown voltage close to that of a planar junction.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention has a planar guard plate with a field plate withstand voltage structure, and an oxide film and its oxidation in a region near the boundary between the active portion and the edge of the withstand voltage structure. A first field plate passing through an interlayer insulating film made of BPSG provided on the film and electrically connected to the active portion impurity diffusion region; and a plurality of guard ring impurity diffusions passing through the interlayer insulating film A plurality of second field plates electrically connected to each of the regions, the edge side edge of the field plate in the active part does not protrude from the active part impurity diffusion region, and the field plate in the edge active portion end to said structure and to Rukoto not protrude from the guard ring impurity diffusion regions.
[0009]
According to the present invention, in the region near the boundary between the active portion and the edge, the field plate in the active portion does not protrude from the active portion impurity diffusion region to the edge side, and the field plate in the edge extends from the guard ring impurity diffusion region to the active portion. Therefore, the gap between the adjacent active portion impurity diffusion region and guard ring impurity diffusion region can be reduced, thereby increasing the radius of curvature of the equipotential line and eliminating the withstand voltage bottleneck. Moreover, since there is a field plate, long-term reliability is ensured.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device having a guard-ring withstand voltage structure with a planar field plate according to the present invention. In this semiconductor device, the p + active portion impurity diffusion region 22 located closest to the edge in the region near the boundary between the active portion and the edge is formed on the surface portion of the n − drift layer 21 on the active portion side. Further, the plurality of p + guard ring impurity diffusion regions 23a, 23b, 23c, 23d, and 23e are formed between the active portion of the surface portion on the edge side of the drift layer 21 and the channel stopper 30 made of, for example, Al. Yes.
[0011]
A field plate (first field plate) 26 made of, for example, Al selectively formed on the active part impurity diffusion region 22 penetrates the initial oxide film 24 and the interlayer insulating film 25 made of, for example, BPSG, to form the active part. The impurity diffusion region 22 is electrically connected. The edge side end portion 28 of the first field plate 26 is located closer to the center of the active portion than the edge side end portion 29 of the active portion impurity diffusion region 22. That is, the first field plate 26 on the active part impurity diffusion region 22 does not protrude from the edge side end portion 29 of the active part impurity diffusion region 22 to the edge side.
[0012]
Field plates 27a, 27b, 27c, 27d, and 27e selectively formed on each guard ring impurity diffusion region 23a, 23b, 23c, 23d, and 23e penetrate through the initial oxide film 24 and the interlayer insulating film 25, respectively. The guard ring impurity diffusion regions 23a, 23b, 23c, 23d, and 23e are electrically connected. The active portion side end 31 of the field plate (second field plate) 27a on the guard ring impurity diffusion region 23a located closest to the active portion is more than the active portion side end 32 of the guard ring impurity diffusion region 23a. Located near the center of the edge. That is, the field plate 27a located closest to the active part in the edge does not protrude from the active part side end 32 of the guard ring impurity diffusion region 23a located closest to the active part to the active part side.
[0013]
Here, the interval of the ion implantation window between the active portion impurity diffusion region 22 located closest to the edge and the guard ring impurity diffusion region 23a located closest to the active portion is the same as that of a conventional guard with a planar type field plate. Although it is narrower than the space | interval in a ring pressure | voltage resistant structure and it does not specifically limit, For example, it is 10 micrometers. The field plate 27a on the guard ring impurity diffusion region 23a has a width of, for example, 35 .mu.m and a distance from the adjacent field plate 26 on the active part side of, for example, 40 .mu.m. The distance from the second field plate 27b is, for example, 20 μm.
[0014]
FIG. 2 is a cross-sectional view showing the main part of the first specific example of the semiconductor device according to the present invention. The semiconductor device having the configuration shown in FIG. 2 is a diode, and the anode electrode 46 extends as a field plate in the active portion in the vicinity of the boundary between the active portion and the edge. The edge side end portion 48 of the anode electrode 46 is located closer to the center of the active portion than the edge side end portion 49 of the p-type active portion impurity diffusion region 42 located below the anode electrode 46. Further, the active portion side end portion 51 of the field plate 47 located on the p-type guard ring impurity diffusion region 43 closest to the active portion is at the center of the edge relative to the active portion side end portion 52 of the guard ring impurity diffusion region 43. It is located near. The interval between the ion implantation windows between the active portion impurity diffusion region 42 and the guard ring impurity diffusion region 43 is narrower than the interval in the conventional planar guard plate with guard plate withstand voltage structure. In FIG. 2, reference numeral 41 denotes an n − drift layer, reference numeral 44 denotes an initial oxide film, and reference numeral 45 denotes an interlayer insulating film made of BPSG.
[0015]
FIG. 3 is a cross-sectional view showing the main part of a second specific example of the semiconductor device according to the present invention. The semiconductor device having the configuration shown in FIG. 3 is an insulated gate bipolar transistor (IGBT) or MOSFET, and a gate ring 66 is provided as a field plate in the vicinity of the boundary between the active portion and the edge in the active portion. The edge side end portion 68 of the gate ring 66 is located closer to the center of the active portion than the edge side end portion 69 of the p-type active portion impurity diffusion region 62 located under the gate ring 66. Further, the active portion side end 71 of the field plate 67 located on the p-type guard ring impurity diffusion region 63 closest to the active portion is located at the edge center with respect to the active portion side end 72 of the guard ring impurity diffusion region 63. It is located near.
[0016]
The interval between the ion implantation windows between the active portion impurity diffusion region 62 and the guard ring impurity diffusion region 63 is narrower than the interval in the conventional guard type with guard plate with field plate. In FIG. 3, reference numeral 61 denotes an n − drift layer, reference numeral 64 denotes an initial oxide film, and reference numeral 65 denotes an interlayer insulating film made of BPSG. Reference numeral 73 denotes a p-type well, reference numeral 74 denotes an n + source region, reference numeral 75 denotes a polysilicon layer through a gate insulating layer, and reference numeral 76 denotes an electrode made of Al.
[0017]
According to the above-described embodiment, the edge side end portion 28 of the field plate 26 in the active portion does not protrude from the active portion impurity diffusion region 22 in the region near the boundary between the active portion and the edge, and the most in the edge. Since the active portion side end portion 31 of the field plate 27a located near the active portion does not protrude from the guard ring impurity diffusion region 23a below the field plate 27a, the adjacent active portion impurity diffusion region 22 and guard ring impurity diffusion region 23a The interval can be reduced, thereby increasing the radius of curvature of the equipotential line and eliminating the pressure bottleneck. Therefore, a high breakdown voltage close to the planar breakdown voltage can be generated. In addition, since the field plates 26, 27a, 27b, 27c, 27d, and 27e are provided throughout the breakdown voltage structure, the accumulation of surface charges can be suppressed, so that high reliability is ensured over a long period of time.
[0018]
As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions described in the above-described embodiments are examples, and the present invention is not limited to these. Further, the second and subsequent field plates 27b, 27c, 27d, 27e in the edge from the active part side may or may not protrude from the corresponding guard ring impurity diffusion regions 23b, 23c, 23d, 23e. May be. The present invention can also be realized by inverting the n-type and the p-type.
[0019]
【Effect of the invention】
According to the present invention, in the region near the boundary between the active portion and the edge, the distance between the adjacent active portion impurity diffusion region and the guard ring impurity diffusion region is reduced to increase the curvature radius of the equipotential line, and the withstand voltage bottleneck. By eliminating the above, a high breakdown voltage close to the planar breakdown voltage can be generated. Moreover, since there is a field plate, high reliability can be obtained over a long period of time.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an outline of an example of a semiconductor device having a guard ring withstand voltage structure with a planar field plate according to the present invention.
FIG. 2 is a cross-sectional view of relevant parts showing a first specific example of a semiconductor device according to the present invention;
FIG. 3 is a cross-sectional view of a principal part showing a second specific example of a semiconductor device according to the present invention.
FIG. 4 is a cross-sectional view showing a main part of a conventional semiconductor device having a guard type withstand voltage structure with a planar plate with a field plate.
FIG. 5 is a diagram schematically showing equipotential lines in a region near the boundary between an active portion and an edge of a semiconductor device having a field plate.
FIG. 6 is a diagram schematically showing the state of equipotential lines in a region near the boundary between an active portion and an edge of a semiconductor device without a field plate.
[Explanation of symbols]
22, 42, 62 Active part impurity diffusion region 23a, 43, 63 Guard ring impurity diffusion region 26 First field plate 27a, 47, 67 Second field plate 28, 48, 68 Edge side edge of first field plate Portions 29, 49, 69 Edge-side end portions 31, 51, 71 of the active portion impurity diffusion region Active portion-side ends 32, 52, 72 of the second field plate Active portion-side end portion 46 of the guard ring impurity diffusion region Anode Electrode (first field plate)
66 Gate ring (first field plate)

Claims (4)

プレーナー型のフィールドプレート付きガードリング耐圧構造を有する半導体装置の活性部とエッジとの境界近傍領域において、
酸化膜と、該酸化膜の上に設けられたＢＰＳＧよりなる層間絶縁膜を貫通して活性部不純物拡散領域に電気的に接続している第１のフィールドプレートと、
前記層間絶縁膜を貫通して複数のガードリング不純物拡散領域の各々に電気的に接続している複数の第２のフィールドプレートとを有し、
前記活性部内の、前記エッジに最も近い第１のフィールドプレートのエッジ側端部が、前記活性部内の、前記エッジとの境界に設けられた活性部不純物拡散領域のエッジ側端部よりも活性部中央寄りに位置し、かつ前記エッジ内の、前記活性部に最も近い第２のフィールドプレートの活性部側端部が、前記エッジ内の、前記活性部に最も近いガードリング不純物拡散領域の活性部側端部よりもエッジ中央寄りに位置することを特徴とする半導体装置。In the region near the boundary between the active portion and the edge of the semiconductor device having a guard ring withstand voltage structure with a planar type field plate,
An oxide film and a first field plate passing through an interlayer insulating film made of BPSG provided on the oxide film and electrically connected to the active portion impurity diffusion region;
A plurality of second field plates passing through the interlayer insulating film and electrically connected to each of the plurality of guard ring impurity diffusion regions;
The edge part of the first field plate closest to the edge in the active part is more active than the edge part of the active part impurity diffusion region provided at the boundary with the edge in the active part. An active portion side end portion of the second field plate closest to the active portion located near the center and closest to the active portion in the edge is an active portion of the guard ring impurity diffusion region closest to the active portion in the edge wherein a position to Rukoto the edge inboard of the side edges. 前記第１のフィールドプレートがダイオードのアノード電極を兼ねることを特徴とする請求項１に記載の半導体装置。  The semiconductor device according to claim 1, wherein the first field plate also serves as an anode electrode of a diode. 前記第１のフィールドプレートが絶縁ゲート型半導体装置のゲートリングであることを特徴とする請求項１に記載の半導体装置。  The semiconductor device according to claim 1, wherein the first field plate is a gate ring of an insulated gate semiconductor device. 前記活性部不純物拡散領域と前記ガードリング不純物拡散領域との間のイオン注入窓の間隔は１０μｍであることを特徴とする請求項１〜３のいずれか一つに記載の半導体装置。  The semiconductor device according to claim 1, wherein an interval between ion implantation windows between the active part impurity diffusion region and the guard ring impurity diffusion region is 10 μm.
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