JP4830184B2 - Manufacturing method of semiconductor device - Google Patents
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- JP4830184B2 JP4830184B2 JP2000223798A JP2000223798A JP4830184B2 JP 4830184 B2 JP4830184 B2 JP 4830184B2 JP 2000223798 A JP2000223798 A JP 2000223798A JP 2000223798 A JP2000223798 A JP 2000223798A JP 4830184 B2 JP4830184 B2 JP 4830184B2
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Description
【０００１】
【発明の属する技術分野】
この発明は、ＩＧＢＴなどの絶縁ゲート構造のパワー半導体素子である半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
ＩＧＢＴやＭＯＳＦＥＴなどの半導体素子は、電流を通電する領域であるＭＯＳ型セル領域（ＭＯＳ型ゲート構造部と主電流を通電するソース領域を含む領域）とチップ周辺部に配置した耐圧構造部により構成される。
図１２は、従来の半導体装置で、同図（ａ）はチップの平面図、同図（ｂ）は同図（ａ）のＤ部拡大図である。
【０００３】
同図（ａ）において、斜線部分がチップ周辺の耐圧構造部１０３であり、ゲートパッド部１０４を除く部分がＭＯＳ型セル領域１０２で、テラスゲート構造部とｎ+ ソース領域を含む活性領域である。ＭＯＳ型セル領域１０２内には、図示しない数１００本のストライプ構造のＭＯＳ型セルが配置されている。
同図（ｂ）において、ポリシリコンの抜きの部分１０５（ポリシリコン層がない箇所）以外はポリシリコン層が形成されている。ポリシリコン層の下に厚い酸化膜１０６が形成されている。この厚い酸化膜の内、１０７の酸化膜をテラスゲート酸化膜と呼ぶこととする。また、１０６ａはゲート酸化膜である薄い酸化膜である。通常は、テラスゲート酸化膜がないチャネル形成領域上の薄いゲート酸化膜１０６ａのみでＭＯＳ型セル領域全域を形成する場合の方が多い。このテラスゲート構造はチップのゲート容量を低減する効果がある。
【０００４】
図１３は、図１２の要部断面図で、同図（ａ）は図１２（ｂ）のＡ−Ａ線で切断したＭＯＳ型セル領域の断面図、同図（ｂ）は図１２（ａ）のＢ−Ｂ線で切断した耐圧構造部の断面図である。
図１３において、ゲート部分の一部にもテラスゲート酸化膜（厚い酸化膜）である第１ゲート酸化膜１１８が形成されており、ゲート容量を低減させている。同図（ａ）のＡ部拡大図に示すように、テラスゲート部の厚いゲート酸化膜（第２ゲート酸化膜１１８）とチャネル形成領域上に形成された薄いゲート酸化膜１１１の境界箇所（Ａ部）に段差が生じる。
【０００５】
図１４から図２０は、従来の半導体装置の製造工程で、工程順に示した要部工程断面図である。それぞれの図の（ａ）は図１２のＡ−Ａ線で切断したＭＯＳ形セル領域の断面図、図の（ｂ）は図１２（ａ）のＢ−Ｂ線で切断した耐圧構造部の断面図である。
（１）ｎシリコン基板１０８上に第１酸化膜１１６ａを形成する（図１４）。
（２）フォト工程（１ＰＥ）により、第１酸化膜１１６ａを残す部分と第１酸化膜１１６ａを残さない部分を形成する（図１５）。
（３）ボロンイオンの注入を行う。第１酸化膜１１６ａを残さない部分（酸化膜が除去された部分）にボロンイオン１２１が入る（図１６）。
（４）その後、熱処理により、イオン注入されたボロンを拡散させ、高濃度ｐ領域１０９を形成する。この熱処理工程で酸素を流す。それにより、（ｂ）の工程にてｎシリコン基板１０８上の第１酸化膜１１６ａを残した部分の酸化膜の膜厚は、この熱処理工程で形成される第２酸化膜１１６ｂが積層されて、さらに厚くなると共に、第１酸化膜１１６ａを残さなかった部分にも新たな第２酸化膜１１６ｂが形成される（図１７）。
（５）フォト工程（２ＰＥ）により、ｎシリコン基板１０８表面に形成された第１酸化膜１１６ａおよび第２酸化膜１１６ｂを残す部分と、第１酸化膜１１６ａおよび第２酸化膜１１６ｂを残さない部分を形成する（図１８）。
（６）全面に薄い第３酸化膜１１６ｃを形成する。第１酸化膜１１６ａおよび第２酸化膜１１６ｂがない箇所のｎシリコン基板１０８表面が露出している箇所に形成された第３酸化膜１１６ｃは第２ゲート酸化膜１１１となり、第１酸化膜１１６ａ、第２酸化膜１１６ｂおよび第３酸化膜１１６ｃを合わせたものが第２ゲート酸化膜１１８および耐圧構造用酸化膜１１６となる（図１９）。
（７）ポリシリコン層１１２を形成し、ｐウエル領域１０９ａ、ｎ+ ソース領域１１０、層間絶縁膜１１３、金属電極となる金属膜１１４、抵抗性を示すフィールドプレート１１５を形成する。このフィールドプレート１１５は通常のＭＯＳ型半導体素子の抵抗性のフィールドプレートと同じである（図２０）。
【０００６】
図２０のＭＯＳ型セル領域および耐圧構造部において、第１酸化膜１１６ａおよび第２酸化膜１１６ｂおよび第３酸化膜１１６ｃを合わせた第２ゲート酸化膜１１８と耐圧構造部用酸化膜１１６は同時に形成され、その膜厚は１０００ｎｍ程度である。
この製造工程の場合、図１３に示すＡ部の段差箇所で、ｎシリコン基板１０８側にも段差が形成される。これは、第２ゲート酸化膜１１８の形成が、シリコン結晶と製造プロセスで供給される酸素との反応によって行われるため、ｎシリコン基板１０８側にも酸化膜層が形成されるためである。
【０００７】
【発明が解決しようとする課題】
前記のＡ部を拡大すると、上側にｄの第２段差、ｎシリコン基板１０８の表面層にｃの第１段差ができている。第２段差ｄは、第２ゲート酸化膜１１８の膜厚が厚い程大きくなり、また、第１段差ｃは、第２ゲート酸化膜１１８の膜厚が厚い場合に大きくなる。また、製造プロセス条件において、ｎシリコン基板温度が高い場合や酸素の流量が多い場合などに大きくなる。
【０００８】
第１段差ｃおよび第２段差ｄが大きくなると、この箇所での電界強度が大きくなり、コレクタ・エミッタ間耐圧の電圧を印加した場合、この箇所でリーク電流が増大する。これは、半導体素子の耐圧良品率に影響を与える。
そこで、これらの段差ｃ、ｄを極力小さくすることが求められる。そのために、第２ゲート酸化膜１１８を薄くし、段差を小さくすると、段差部分の電界集中は緩和される。その結果、ＭＯＳ型セル領域でのコレクタ・エミッタ間耐圧（アバランシェ耐圧）の低下を防止できる。
【０００９】
しかし、従来素子では、第２ゲート酸化膜１１８と耐圧構造用酸化膜１１６は同一条件で形成されるために、耐圧構造用酸化膜１１６の膜厚が薄くなり、そのために、耐圧構造部でのコレクタ・エミッタ間耐圧が低下する。
この発明の目的は、前記の課題を解決して、ＭＯＳ型セル領域部と耐圧構造部の双方で、コレクタ・エミッタ間の耐圧低下を防止できる半導体装置を提供することにある。
【００１０】
【課題を解決するための手段】
前記の目的を達成するために、第１導電形の半導体基板の表面層に形成された複数の第２導電形領域と、半導体基板周辺部表面に形成された耐圧構造用絶縁膜を有する耐圧構造部と、前記耐圧構造部に囲まれた第２導電形領域の表面層に形成された第１導電形のソース領域、該ソース領域と前記半導体基板表面に挟まれた前記第２導電形領域表面上に形成された第１ゲート絶縁膜、前記第１ゲート絶縁膜より厚く、前記第１ゲート絶縁膜と連続して、前記半導体基板上に形成された第２ゲート絶縁膜とからなるＭＯＳ型セル領域を有する半導体装置の製造方法において、以下の工程とする。
【００１１】
第１導電形の半導体基板上に第１絶縁膜を形成する工程と、該第１絶縁膜を選択的に除去する工程と、前記第１絶縁膜をマスクとして前記半導体基板の第２導電形の前記第２導電形領域を選択的に形成する工程と、前記第１絶縁膜を耐圧構造用絶縁膜となる箇所を残して除去する工程と、前記半導体基板上全面に第２絶縁膜を形成する工程と、前記第２絶縁膜を耐圧構造用絶縁膜となる箇所および前記ＭＯＳ型セル領域の前記第２ゲート絶縁膜となる箇所を残して除去する工程と、前記半導体基板上全面に前記第１絶縁膜および前記第２絶縁膜よりも薄い第３絶縁膜を形成する工程と、前記耐圧構造部と前記ＭＯＳ型セル領域の前記第２導電形領域上の第３絶縁膜を選択的に除去する工程と、前記ＭＯＳ型セル領域の前記第２導電形領域に第１導電形のソース領域を形成する工程とを含む製造工程とするとよい。
【００１２】
前記第２絶縁膜と第３絶縁膜を積層して形成される第２ゲート絶縁膜の厚さが、前記第１絶縁膜と第２絶縁膜および第３絶縁膜で積層されて形成される耐圧構造用絶縁膜の膜厚より薄くなるために、従来のように、第２ゲート絶縁膜の膜厚が、耐圧構造用絶縁膜の膜厚と同じ厚みである場合に比べると、第２ゲート絶縁膜と第１ゲート絶縁膜の境界部の半導体基板側に生じる段差を小さくできる。段差を小さくできることで、第１および第２ゲート絶縁膜内部と半導体基板表面での電界集中を緩和できる。その結果、コレクタ・エミッタ間の耐圧不良が低減され、良品率を向上させることができる。
【００１３】
また、第１導電形の半導体基板上に第１絶縁膜を形成する工程と、該第１絶縁膜を選択的に除去する工程と、前記第１絶縁膜をマスクとし、第２導電形不純物をイオン注入する工程と、前記第１絶縁膜を耐圧構造用絶縁膜となる箇所を残して除去する工程と、酸素を流しながら熱処理して、前記半導体基板の表面層に第２導電形領域を選択的に形成すると共に、全面に第２絶縁膜を形成する工程と、前記第２絶縁膜を耐圧構造用絶縁膜となる箇所および前記ＭＯＳ型セル領域の前記第２ゲート絶縁膜となる箇所を残して除去する工程と、前記半導体基板上全面に前記第１絶縁膜および前記第２絶縁膜よりも薄い第３絶縁膜を形成する工程と、前記耐圧構造部と前記ＭＯＳ型セル領域の前記第２導電形領域上の第３絶縁膜を選択的に除去する工程と、前記ＭＯＳ型セル領域の前記第２導電形領域に第１導電形のソース領域を形成する工程とを含む製造工程とするとよい。
【００１４】
また、第１導電形の半導体基板上に第１絶縁膜を形成する工程と、該第１絶縁膜を選択的に除去する工程と、前記第１絶縁膜をマスクとし、第２導電形不純物をイオン注入し、熱処理して、前記半導体基板の表面層に前記第２導電形領域を選択的に形成する工程と、前記第１絶縁膜を耐圧構造用絶縁膜となる箇所を残して除去する工程と、全面に第２絶縁膜を形成する工程と、前記第２絶縁膜を、耐圧構造用絶縁膜となる箇所および前記ＭＯＳ型セル領域の前記第２ゲート絶縁膜となる箇所を残して除去する工程と、前記第１絶縁膜および前記第２絶縁膜よりも薄い第３絶縁膜を形成する工程と、前記耐圧構造部と前記ＭＯＳ型セル領域の前記第２導電形領域上の第３絶縁膜を選択的に除去する工程と、前記ＭＯＳ型セル領域の前記第２導電形領域に第１導電形のソース領域を形成する工程とを含む製造工程とするとよい。
【００１５】
また、第１導電形の半導体基板上に第１絶縁膜を形成する工程と、該第１絶縁膜を前記耐圧構造用絶縁膜となる箇所を残して除去する工程と、全面に第２絶縁膜を形成する工程と、前記耐圧構造部および前記ＭＯＳ型セル領域の第２導電形領域を形成する箇所の第２絶縁膜を除去する工程と、前記ＭＯＳ型セル領域で前記第２絶縁膜をマスクとし、前記耐圧構造部で前記第１絶縁膜と前記第２絶縁膜をマスクとして第２導電形不純物をイオン注入する工程と、熱処理して、前記半導体基板の表面層に前記第２導電形領域を選択的に形成する工程と、前記第２絶縁膜を前記第２ゲート絶縁膜となる箇所と前記耐圧構造用絶縁膜となる箇所を残して前記ＭＯＳ型セル領域の前記第２絶縁膜を除去する工程と、前記第１絶縁膜および前記第２絶縁膜よりも薄い第３絶縁膜を形成する工程と、前記耐圧構造部と前記ＭＯＳ型セル領域の前記第２導電形領域上の第３絶縁膜を選択的に除去する工程と、前記ＭＯＳ型セル領域の前記第２導電形領域に第１導電形のソース領域を形成する工程とを含む製造工程とするとよい。
【００１６】
また、第１導電形の半導体基板上に第１絶縁膜を形成する工程と、該第１絶縁膜を前記耐圧構造用絶縁膜となる箇所を残して除去する工程と、全面に第２絶縁膜を形成する工程と、前記耐圧構造部および前記ＭＯＳ型セル領域の第２導電形領域を形成する箇所の第２絶縁膜を除去する工程と、全面に第４絶縁膜を形成する工程と、前記第１絶縁膜と第２絶縁膜をマスクとして前記第４絶縁膜を介して第２導電型不純物をイオン注入する工程と、熱処理して、前記半導体基板の表面層に前記第２導電形領域を選択的に形成する工程と、前記第２絶縁膜および前記第４絶縁膜を前記第２ゲート絶縁膜となる箇所と前記耐圧構造用絶縁膜となる箇所を残して除去する工程と、前記第１絶縁膜、前記第２絶縁膜および前記第４絶縁膜よりも薄い第３絶縁膜を形成する工程と、前記耐圧構造部と前記ＭＯＳ型セル領域の前記第２導電形領域上の第３絶縁膜を選択的に除去する工程と、前記ＭＯＳ型セル領域の前記第２導電形領域に第１導電形のソース領域を形成する工程とを含む製造工程とするとよい。
【００１７】
また、第１導電形の半導体基板上に第１絶縁膜を形成する工程と、該第１絶縁膜を前記耐圧構造用絶縁膜となる箇所を残して除去する工程と、全面に第２絶縁膜を形成する工程と、全面にフォトレジストを被覆し、前記第２導電形領域形成箇所と前記第１絶縁膜が除去された箇所のパターニングする工程と、前記第２導電形領域を形成する箇所の前記第２絶縁膜と前記第１絶縁膜が除去された箇所の前記第２絶縁膜を、前記フォトレジストをマスクに除去する工程と、前記フォトレジストをマスクとし、第２導電形不純物をイオン注入する工程と、前記フォトレジストを除去する工程と、熱処理して、前記半導体基板の表面層に第２導電形領域を選択的に形成する工程と、前記第２絶縁膜を、前記耐圧構造用絶縁膜となる箇所と前記第２ゲート絶縁膜となる箇所を残して除去する工程と、前記第１絶縁膜および前記第２絶縁膜よりも薄い第３絶縁膜を形成する工程と、前記耐圧構造部と前記ＭＯＳ型セル領域の前記第２導電形領域上の第３絶縁膜を選択的に除去する工程と、前記ＭＯＳ型セル領域の前記第２導電形領域に第１導電形のソース領域を形成する工程とを含む製造工程とするとよい。
【００１８】
また、第１導電形の半導体基板上に第１絶縁膜を形成する工程と、該第１絶縁膜を前記耐圧構造用絶縁膜となる箇所を残して除去する工程と、全面に第４絶縁膜を形成する工程と、前記第４絶縁膜上にフォトレジストを被覆する工程と、前記ウエル領域形成箇所と前記第１絶縁膜が除去された箇所の第４絶縁膜上のフォトレジストを除去する工程と、前記フォトレジストをマスクとし、前記第４絶縁膜を介して第２導電形不純物をイオン注入する工程と、前記フォトレジストを除去する工程と、熱処理して、前記半導体基板の表面層に前記第２導電形領域を選択的に形成すると共に全面に第２絶縁膜を形成する工程と、前記第２絶縁膜と第４絶縁膜を、前記耐圧構造用絶縁膜となる箇所と前記第２ゲート絶縁膜となる箇所を残して除去する工程と、前記半導体基板上全面に前記第１絶縁膜、前記第２絶縁膜および前記第４絶縁膜よりも薄い第３絶縁膜を形成する工程と、前記耐圧構造部と前記ＭＯＳ型セル領域の前記第２導電形領域上の第３絶縁膜を選択的に除去する工程と、前記ＭＯＳ型セル領域の前記第２導電形領域に第１導電形のソース領域を形成する工程とを含む製造方法とするとよい。
【００１９】
前記のようにすることで、イオン注入された不純物の外方拡散が第２絶縁膜、第４絶縁膜で防止され、素子特性を安定化させることができる。またフォトレジストを介してイオン注入することで絶縁膜への不純物イオンの導入が抑えられて絶縁膜の信頼性が向上する。
【００２０】
【発明の実施の形態】
図１は、この発明の第１実施例の半導体装置の要部断面図で、同図（ａ）はＭＯＳ型セル領域の断面図、同図（ｂ）は耐圧構造部の断面図である。図１（ａ）、（ｂ）は、図２（ａ）、（ｂ）に対応する図である。
図１において、ｎシリコン基板８の表面層に高濃度ｐ領域９を、ＭＯＳ型セル領域と耐圧構造部に形成し、ＭＯＳ型セル領域のｎシリコン基板８の表面層に、ｐウエル領域９ａを形成し、ｐウエル領域９ａの表面層にｎ+ ソース領域１０を形成する。ｎ+ ソース領域１０とｎシリコン基板８に挟まれたｐウエル領域上にＭＯＳ型ゲート構造の酸化膜となる第２ゲート酸化膜１１を形成し、ｎシリコン基板８上に第２およびテラスゲート酸化膜である第２ゲート酸化膜１８を形成し、これらのゲート酸化膜１１、１８上に、ゲート電極となるポリシリコン層１２を形成する。このポリシリコン層１２上に層間絶縁膜１３を形成し、層間絶縁膜１３上とｎ+ ソース領域１０および高濃度ｐ領域９の露出部（コンタクトホール部）上に、ソース電極となる金属膜１４を形成する。
【００２１】
一方、耐圧構造部の高濃度ｐ領域９はｐガードリング領域となり、この高濃度ｐ領域９に挟まれたｎシリコン領域８上に耐圧構造用酸化膜１６を形成する。この耐圧構造用酸化膜１６上に層間絶縁膜１３を介して金属膜１４を形成し、この金属膜１４と、高濃度ｐ領域９が接続している。この金属膜１４上に抵抗性ａ−Ｓｉ膜のフィールドプレート１５を形成する。図中の２０はｎシリコン基板であるチップのチップエッジを示す。
【００２２】
前記の第２ゲート酸化膜１８の膜厚Ｗは、耐圧構造用酸化膜１６の膜厚Ｄより薄く形成する。また、第２ゲート酸化膜１８と第１ゲート酸化膜１１の境界部であるＡ部を拡大すると、上側にｂの段差、ｎシリコン基板８の表面層にａの段差ができている。このａの段差は、従来素子のように、厚い第１ゲート酸化膜の場合の段差ｃに比べると、第２ゲート酸化膜１８の膜厚Ｗが薄いために、極めて小さくなる。その結果、後述するように、酸化膜内部およびシリコン表面での最大電界強度が小さくなり、この箇所でのコレクタ・エミッタ間耐圧の低下は防止される。また、段差ｂも従来の段差ｄより小さくなるので、電界強度が緩和され、コレクタ・エミッタ間耐圧の低下が防止される。また、耐圧構造部での酸化膜（耐圧構造用酸化膜１６）の膜厚は、従来素子並に厚いために、この箇所でのコレクタ・エミッタ間耐圧の低下はない。
【００２３】
前記において、ＭＯＳ型セル領域は、チャネル形成領域上の第１ゲート酸化膜より膜厚が厚い、テラスゲート酸化膜である第２ゲート酸化膜で、ｎシリコン基板８表面の大部分が被覆されているので、テラスゲート構造でない、ｎシリコン基板８上を薄い第１ゲート酸化膜で被覆する場合に比べて、ゲート容量を減少させることができる。
【００２４】
また、前記の耐圧構造部は、数本の高濃度ｐ領域９で形成されたｐガードリング領域と抵抗性ａ−Ｓｉ膜によるフィールドプレート１５を併用した構造となっている。
尚、ＭＯＳ型セル領域のテラスゲートである第２ゲート酸化膜１８の膜厚は３５０ｎｍ程度、チャネル形成用の第１ゲート酸化膜１１の膜厚は８０ｎｍ程度、また、耐圧構造用酸化膜１６の膜厚は１０００ｎｍ程度である。ただし、図中の各膜の膜厚は同じ厚さに描いている。
【００２５】
図２から図９は、この発明の第１実施例の半導体装置の製造工程を工程順に示した要部工程断面図である。各図において（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図である。
（１）ｎシリコン基板８上に第１酸化膜１６ａを形成する（図２）。
（２）フォト工程（１ＰＥ）により、第１酸化膜１６ａを残す部分と第１酸化膜１６ａを残さない部分を形成する（図３）。（３）ｎシリコン基板８上の第１酸化膜１６ａを残さない部分にイオン注入でボロンイオンを注入する（図４）。
（４）フォト工程（１．５ＰＥ：１．５ＰＥとは１ＰＥの工程と２ＰＥの工程の中間にある工程）により、耐圧構造部の第１酸化膜１６ａは残し、ＭＯＳ型セル領域の第１酸化膜１６ａは残さない（図５）。
（５）その後、熱処理（１１５０℃）により拡散させ、高濃度ｐ領域９を形成する。耐圧構造部に形成された高濃度ｐ領域９はｐガードリング領域となる。この熱処理工程は酸素を流しながら行う。そのため、（２）の工程にてｎシリコン基板８上の第１酸化膜１６ａを残した部分（耐圧構造部）の酸化膜の膜厚は第２酸化膜１６ｂの積層により、さらに厚くなり、その膜厚は後工程のゲート酸化膜となる第３酸化膜１６ｃの厚みも加わり１０００ｎｍ程度となる。一方、第１酸化膜１６ａを残さなかった部分（ＭＯＳ型セル領域）のｎシリコン基板８が露出した箇所にも新たに第２酸化膜１６ｂが形成され（図６）、その膜厚は、後工程のゲート酸化膜となる第３酸化膜１６ｃの厚みも加えて３５０ｎｍ程度となる。
（６）フォト工程（２ＰＥ）により、ＭＯＳ型セル領域のｎシリコン基板８表面に新たに形成された第２酸化膜１６ｂを残す部分と第２酸化膜１６ｂを残さない部分を形成する。また、耐圧構造部では、第２酸化膜１６ｂを開口して、高濃度ｐ領域９表面を露出する（図７）。
（７）全面に第３酸化膜１６ｃを形成する（図８）。第１酸化膜１６ａおよび第２酸化膜１６ｂがない箇所のｎシリコン基板８表面が露出している箇所に形成された第３酸化膜１６ｃは図９の第１ゲート酸化膜１１となり、第２酸化膜１６ｂと第３酸化膜１６ｃを合わせたものが図９の第２ゲート酸化膜１８となり、また、第１酸化膜１６ａ、第２酸化膜１６ｂおよび第３酸化膜１６ｃを合わせたものが耐圧構造用酸化膜１６となる。第３酸化膜１６ｃである第１ゲート酸化膜１１の膜厚は８０ｎｍ程度である。
（８）ゲート電極となるポリシリコン層１２を形成し、ｐウエル領域９ａ、ｎ+ ソース領域１０、層間絶縁膜１３、Ａｌ−Ｓｉ金属電極である金属膜１４、抵抗性ａ−Ｓｉ膜であるフィールドプレート１５を形成する。このフィールドプレートは通常のＭＯＳ型デバイスの抵抗性のフィールドプレートと同じで、抵抗性を示せばａ−Ｓｉ膜に限らない。
【００２６】
表１は、本発明のテラスゲート構造と従来のテラスゲート構造の第２ゲート酸化膜の膜厚と最大電界強度の関係をシミュレーションした例を示す。
【００２７】
【表１】
ゲート酸化膜の膜厚を３５０ｎｍとした本発明のテラスゲート構造では、従来のテラスゲート構造に比べて、最大電界強度は酸化膜内部で２０％、シリコン基板表面で２４％低減する。
【００２８】
図１０は、本発明品と従来品のコレクタ・エミッタ間耐圧の不良率を示す図である。本発明品の不良率は半分程度に低減している。
図１１は、コレクタ・エミッタ間耐圧（アバランシェ電圧）と耐圧構造用酸化膜の膜厚の関係を示した図である。
酸化膜の膜厚が３５０ｎｍの場合、コレクタ・エミッタ間耐圧は、１０００ｎｍに比べて９０％に低下する。このことは、従来のテラスゲート構造の場合、耐圧構造用酸化膜の膜厚とテラスゲート部の第２ゲート酸化膜の膜厚が同一であり、その第２ゲート酸化膜を３５０ｎｍで形成すると耐圧構造用酸化膜の膜厚も３５０ｎｍとなり、耐圧が９０％に低下することを意味する。本発明品では、耐圧構造用酸化膜の膜厚を１０００ｎｍとし、第２ゲート酸化膜の膜厚を３５０ｎｍとすることができるために、耐圧低下を防止できる。
【００２９】
前記の工程では、ボロンイオン注入（３）の工程）後に、フォト工程にてＭＯＳ型セル領域の酸化膜を全て除去（（４）の工程）した後、熱処理によりボロンイオンを拡散させる（（５）の工程）。
この場合は、（５）の工程で、熱処理の条件によっては、熱処理時に、注入したボロンイオンが外方拡散（アウトディフュージョン））を起こし、ウエハ外に拡散し、この外方拡散を起こしたボロンイオンが、再度ウエハに拡散して、素子の特性を変化させる危険性がある。図２１は、ＭＯＳ型セル領域を例とした、外方拡散の様子を示した図で、同図（ａ）はイオン注入後で図５（ａ）の図、同図（ｂ）は熱処理で外方拡散の様子を示す図、同図（ｃ）は外方拡散で所定外の箇所にｐ領域９ｂが形成された様子を示す図である。同図（ｂ）の熱処理開始後、注入されているボロンイオン２１が外方拡散を起こし、本来ボロンイオン２１が導入されない部分にもボロンイオン２１が再拡散する。
【００３０】
このような外方拡散を起こした場合、同図（ｃ）のように、ＭＯＳ型セル領域の表面に、本来想定しないｐ領域９ｂが形成される場合がある。図２２は、本来想定しないｐ領域９ｂが形成された場合のＭＯＳ型セル領域の完成図の一例である。
この場合、ＭＯＳ型セル領域のｎシリコン基板８の表面がｐ領域９ｂに覆われてしまい、このｐ領域９ｂの深さが深いときには、形成されたｎチャネルがｎシリコン基板８に接続しなくなる。そのため、ゲート電圧を印加しても、ｎ+ ソース領域からｎシリコン基板８に電子を注入することができず、ＭＯＳ型デバイスはコレクタ電流を流すことができず、スイッチング素子として機能しない。これを防止する方策として以下の実施例を説明する。
【００３１】
図２３から図３０は、この発明の第２実施例の半導体装置の製造方法であり、工程順に示した製造工程断面図である。尚、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図である。
（１）ｎシリコン基板８上に第１酸化膜１６ａを形成する（図２３）。
（２）フォト工程（１ＰＥ）により、第１酸化膜１６ａを残す部分と第１酸化膜１６ａを残さない部分を形成する（図２４）。
（３）ｎシリコン基板８上からイオン注入でボロンイオンを注入する。ｎシリコン基板８上の第１酸化膜１６ａが残っている部分は、ｎシリコン基板８にはイオン注入されず（ボロンイオンは、第１酸化膜１６ａを貫通できない）、ｎシリコン基板８上の第１酸化膜１６ａを残さない部分に、イオン注入でボロンイオン２１を注入する（図２５）。
（４）その後、図５（ａ）のように、ＭＯＳ型セル領域の第１酸化膜１６ａを除去しないで、熱処理（１１５０℃）によりボロンイオン２１を拡散させ、高濃度ｐ領域９を形成する。耐圧構造部に形成された高濃度ｐ領域９はガードリング領域となる。この熱処理工程は酸素を流さないで行う。（２）の工程にて、ｎシリコン基板８上の第１酸化膜１６ａを残した部分の酸化膜の膜厚および第１酸化膜１６ａを残さなかった部分の酸化膜の膜厚に大きな変化はない（図２６）。
（５）フォト工程（１．５ＰＥ）により、耐圧構造部の第１酸化膜１６ａは残し、ＭＯＳ型セル領域の第１酸化膜１６ａは残さない（図２７）。
（６）その後、熱処理（１１５０℃）を行う。この熱処理工程は酸素を流しながら行う。そのため、（２）の工程にてｎシリコン基板８上の第１酸化膜１６ａを残した部分（耐圧構造部）の酸化膜の膜厚は、第２酸化膜１６ｂの積層により、さらに厚くなり、その膜厚は後工程のゲート酸化膜となる第３酸化膜１６ｃの厚みも加わり１０００ｎｍ程度となる。一方、第１酸化膜１６ａを残さなかった部分（ＭＯＳ型セル領域）のｎシリコン基板８が露出した箇所にも新たな第２酸化膜１６ｂが形成され、その膜厚は後工程のゲート酸化膜となる第３酸化膜１６ｃの厚みも加えて３５０ｎｍ程度となる。このとき、（４）の工程にて拡散した高濃度ｐ領域９は、さらに深く拡散される（図２８）。
（７）フォト工程（２ＰＥ）により、ＭＯＳ型セル領域のｎシリコン基板８表面に新たに形成された第２酸化膜１６ｂを残す部分と、第２酸化膜１６ｂを残さない部分を形成する。また、耐圧構造部では、第２酸化膜１６ｂを開口して、高濃度ｐ領域９を露出する（図２９）。
（８）全面に薄い第３酸化膜１６ｃを形成する。第１酸化膜１６ａおよび第２酸化膜１６ｂがない箇所のｎシリコン基板８表面が露出している箇所に形成された第３酸化膜１６ｃは図９の第１ゲート酸化膜１１となり、第２酸化膜１６ｂと第３酸化膜１６ｃを合わせたものが図９の第２ゲート酸化膜１８となり、また、第１酸化膜１６ａ、第２酸化膜１６ｂおよび第３酸化膜１６ｃを合わせたものが耐圧構造酸化膜１６となる。第３酸化膜１６ｃである第１ゲート酸化膜１１の膜厚は８０ｎｍ程度である（図３０）。
（９）図９と同様に、ゲート電極となるポリシリコン層１２を形成し、ｐウエル領域９ａ、ｎ+ ソース領域１０、層間絶縁膜１３、金属電極となる金属膜１４、抵抗性を示すフィールドプレート１５を形成する。このフィールドプレートは通常のＭＯＳ型半導体素子のフィールドプレートと同じで、抵抗性を示せば、ａ−Ｓｉ膜に限らない。
【００３２】
尚、（５）の工程でｎシリコン基板８表面が露出するが、このときにはボロンイオンの拡散工程を行った後であるので、シリコン表面のイオン濃度は非常に低下しており、（６）の工程での熱処理で、ボロンイオン２１の外方拡散量は極めて少ない。そのため、素子特性に変化は起こらない。
図３１から図３８は、この発明の第３実施例の半導体装置の製造方法であり、工程順に示した製造工程断面図である。尚、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図である。
（１）ｎシリコン基板８上に第１酸化膜１６ａを形成する（図３１）。
（２）フォト工程（１ＰＥ）により、第１酸化膜１６ａを残す部分と第１酸化膜１６ａを残さない部分を形成する。ＭＯＳ型セル領域の第１酸化膜１６ａは残さない（図３２）。
（３）その後、熱処理（１１５０℃）を行う。この熱処理工程は酸素を流しながら行う。そのため、（２）の工程にてｎシリコン基板８上の第１酸化膜１６ａを残した部分（耐圧構造部）の酸化膜の膜厚は、第２酸化膜１６ｂの積層により、さらに厚くなり、その膜厚は後工程のゲート酸化膜となる第３酸化膜１６ｃの厚みも加わり１０００ｎｍ程度となる。一方、第１酸化膜１６ａを残さなかった部分（ＭＯＳ型セル領域）のｎシリコン基板８が露出した箇所にも新たな第２酸化膜１６ｂが形成され、その厚みは、後工程のゲート酸化膜となる第３酸化膜１６ｃの厚みも加えて３５０ｎｍ程度となる（図３３）。
（４）フォト工程（１．５ＰＥ）により、耐圧構造部は、第２酸化膜１６ｂを残す部分と第２酸化膜１６ｂを残さない部分を形成する。ＭＯＳ型セル領域は、第２酸化膜１６ｂを残す部分と第２酸化膜１６ｂを残さない部分を形成する（図３４）。
（５）ｎシリコン基板８上からイオン注入でボロンイオンを注入する。ｎシリコン基板８上の第１酸化膜１６ａあるいは第２酸化膜１６ｂが残っている部分は、ｎシリコン基板８にはイオン注入されず（ボロンイオンは、第１酸化膜１６ａあるいは第２酸化膜１６ｂを貫通できない）、ｎシリコン基板８上の第１酸化膜１６ａおよび第２酸化膜１６ｂを残さない部分にイオン注入でボロンイオンを注入する（図３５）。
（６）その後、熱処理（１１５０℃）により拡散させ、高濃度ｐ領域９を形成する。耐圧構造部に形成された高濃度ｐ領域９はガードリング領域となる。この熱処理工程は、酸素を流さないで行う。（４）の工程にてｎシリコン基板８上の第２酸化膜１６ｂを残した部分の酸化膜の膜厚および第２酸化膜１６ｂを残さなかった部分の酸化膜の膜厚に大きな変化はない（図３６）。
（７）フォト工程（２ＰＥ）により、ＭＯＳ型セル領域のｎシリコン基板８表面に新たに形成された第２酸化膜１６ｂを残す部分と、第２酸化膜１６ｂを残さない部分を形成する。また耐圧構造部では、第２酸化膜１６ｂを開口して、高濃度ｐ領域９を露出する（図３７）。
（８）全面に薄い第３酸化膜１６ｃを形成する。第１酸化膜１６ａおよび第２酸化膜１６ｂがない箇所のｎシリコン基板８表面が露出している箇所に形成された第３酸化膜１６ｃは図９の第１ゲート酸化膜１１となり、第２酸化膜１６ｂと第３酸化膜１６ｃを合わせたものが図９の第２ゲート酸化膜１８となり、また、第１ゲート酸化膜１６ａ、第２酸化膜１６ｂおよび第３酸化膜１６ｃを合わせたものが耐圧構造用酸化膜１６となる。第３酸化膜１６ｃである第１ゲート酸化膜１１の膜厚は８０ｎｍ程度である（図３８）。
（９）図９と同様に、ゲート電極となるポリシリコン層１２を形成し、ｐウエル領域９ａ、ｎ+ ソース領域１０、層間絶縁膜１３、金属電極となる金属膜１４、抵抗性を示すフィールドプレート１５を形成する。このフィールドプレートは通常のＭＯＳ型半導体素子のフィールドプレートと同じで、抵抗性を示せば、ａ−Ｓｉ膜に限らない。
【００３３】
尚、（６）の工程の段階では、ボロンイオンを注入した箇所以外のｎシリコン基板８表面のシリコンは露出がなく、ＭＯＳ型セル領域のｎシリコン基板８の表面に本来想定しない図２１（ｃ）で示すようなｐ領域９ｂが形成されることはない。
図３９から図４７は、この発明の第４実施例の半導体装置の製造方法であり、工程順に示した製造工程断面図である。尚、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図である。
（１）ｎシリコン基板８上に第１酸化膜１６ａを形成する（図３９）。
（２）フォト工程（１ＰＥ）により、第１酸化膜１６ａを残す部分と第１酸化膜１６ａを残さない部分を形成する。ＭＯＳ型セル領域の第１酸化膜１６ａは残さない（図４０）。
（３）その後、熱処理（１１５０℃）を行う。この熱処理工程は酸素を流しながら行う。そのため、（２）の工程にてｎシリコン基板８上の第１酸化膜１６ａを残した部分（耐圧構造部）の酸化膜の膜厚は、第２酸化膜１６ｂの積層により、さらに厚くなり、その膜厚は後工程のゲート酸化膜となる第３酸化膜１６ｃの厚みも加わり１０００ｎｍ程度となる。一方、第１酸化膜１６ａを残さなかった部分（ＭＯＳ型セル領域）のｎシリコン基板８が露出した箇所にも新たな第２酸化膜１６ｂが形成され、その厚みは、後工程のゲート酸化膜となる第３酸化膜１６ｃの厚みも加えて３５０ｎｍ程度となる（図４１）。
（４）フォト工程（１．５ＰＥ）により、耐圧構造部は、第１酸化膜１６ａと第２酸化膜１６ｂを残す部分と残さない部分を形成する。ＭＯＳ型セル領域は、第２酸化膜１６ｂを残す部分と残さない部分を形成する（図４２）。
（５）その後、熱処理（９００℃）を行う。この熱処理工程は酸素を流しながら行う。（４）の工程にて、第２酸化膜１６ｂを残さない部分のｎシリコン基板８が露出した箇所にも新たな酸化膜１６ｄが形成され、第１酸化膜１６ａあるいは第２酸化膜１６ｂを残した他の部分の酸化膜の膜厚は、さらに厚くなる。酸化膜１６ｄはスクリーン酸化膜で、その膜厚は、５０ｎｍ程度である（図４３）。
（６）ｎシリコン基板８上からイオン注入でボロンイオンを注入する。ｎシリコン基板８上の第１酸化膜１６ａあるいは第２酸化膜１６ｂが残っている部分は、ｎシリコン基板８にはイオン注入されず（ボロンイオンは、第１酸化膜１６ａあるいは第２酸化膜１６ｂを貫通できない）、ｎシリコン基板８上の第１酸化膜１６ａおよび第２酸化膜１６ｂを残さない部分に新たな酸化膜１６ｄを介してイオン注入でボロンイオンを注入する（酸化膜１６ｄは、５０ｎｍ程度と薄いので、ボロン照射加速電圧を大きくすれば、ボロンイオンは酸化膜１６ｄは貫通できる）（図４４）。
（７）その後、熱処理（１１５０℃）により拡散させ、高濃度ｐ領域９を形成する。耐圧構造部に形成された高濃度ｐ領域９はガードリング領域となる。この熱処理工程は、酸素を流さないで行う。（６）の工程にてｎシリコン基板８上の第２酸化膜１６ｂを残した部分の酸化膜の膜厚および第２酸化膜１６ｂを残さなかった部分の酸化膜の膜厚に大きな変化はない（図４５）。
（８）フォト工程（２ＰＥ）により、ＭＯＳ型セル領域のｎシリコン基板８表面に新たに形成された酸化膜１６ｄを残す部分と、酸化膜１６ｄを残さない部分を形成する。また耐圧構造部では、酸化膜１６ｄを開口して、高濃度ｐ領域９を露出する（図４６）。
（９）全面に薄い第３酸化膜１６ｃを形成する。第２酸化膜１６ｂおよび酸化膜１６ｄがない箇所のｎシリコン基板８表面が露出している箇所に形成された第３酸化膜１６ｃは図９の第１ゲート酸化膜１１となり、第２酸化膜１６ｂと第３酸化膜１６ｃおよび酸化膜１６ｄを合わせたものが図９の第２ゲート酸化膜１８に相当し、また、第１ゲート酸化膜１６ａ、第２酸化膜１６ｂ、第３酸化膜１６ｃおよび酸化膜１６ｄを合わせたものが耐圧構造用酸化膜１６となる。第３酸化膜１６ｃである第１ゲート酸化膜１１の膜厚は８０ｎｍ程度である（図４７）。
（１０）図９と同様に、ゲート電極となるポリシリコン層１２を形成し、ｐウエル領域９ａ、ｎ+ ソース領域１０、層間絶縁膜１３、金属電極となる金属膜１４、抵抗性を示すフィールドプレート１５を形成する。このフィールドプレートは通常のＭＯＳ型半導体素子のフィールドプレートと同じで、抵抗性を示せば、ａ−Ｓｉ膜に限らない。
【００３４】
尚、第３実施例との違いは、ボロンイオン注入（（６）の工程）前に５０ｎｍ程度の酸化膜（スクリーン酸化膜）を形成する（（５）の工程）ことである。この５０ｎｍ程度の酸化膜を形成することで、（７）の熱処理で外方拡散を防止すことができる。
図４８から図５６は、この発明の第５実施例の半導体装置の製造方法であり、工程順に示した製造工程断面図である。尚、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図である。
（１）ｎシリコン基板８上に第１酸化膜１６ａを形成する（図４８）。
（２）フォト工程（１ＰＥ）により、耐圧構造部には、第１酸化膜１６ａを残す部分と第１酸化膜１６ａを残さない部分を形成する。ＭＯＳ型セル領域の第１酸化膜１６ａは残さない（図４９）。
（３）その後、熱処理（１１５０℃）を行う。この熱処理工程は酸素を流しながら行う。そのため、（２）の工程にてｎシリコン基板８上の第１酸化膜１６ａを残した部分（耐圧構造部）の酸化膜の膜厚は、第２酸化膜１６ｂの積層により、さらに厚くなり、その膜厚は後工程のゲート酸化膜となる第３酸化膜１６ｃの厚みも加わり１０００ｎｍ程度となる。一方、第１酸化膜１６ａを残さなかった部分（ＭＯＳ型セル領域）のｎシリコン基板８が露出した箇所にも新たな第２酸化膜１６ｂが形成され、その厚みは、後工程のゲート酸化膜となる第３酸化膜１６ｃの厚みも加えて３５０ｎｍ程度となる（図５０）。
（４）フォト工程（１．５ＰＥ）を行う。フォト工程（１．５ＰＥ）は、ウエハ全域にレジスト膜２２を塗布し、露光、エッチングを行い、その後ベークを行い硬化させる。その後、第１酸化膜１６ａおよび第２酸化膜１６ｂのエッチングを行う。この後、ウエハ表面には、レジスト膜を残しておく。このとき、耐圧構造部では、第２酸化膜１６ｂを残す部分と第２酸化膜１６ｂを残さない部分を形成する（図５１）。
（５）ｎシリコン基板８上からイオン注入でボロンイオンを注入する。レジスト膜２２が残っている部分のｎシリコン基板８にはイオン注入されず（ボロンイオンは、レジスト膜２２を貫通できない）、レジスト膜２２を残さない部分のみにイオン注入でボロンイオン２１が注入される（図５２）。
（６）レジスト膜２２を剥離液で除去する（図５３）。
（７）その後、熱処理（１１５０℃）により拡散させ、高濃度ｐ領域９を形成する。耐圧構造部に形成された高濃度ｐ領域９はガードリング領域となる。この熱処理工程は、酸素を流さないで行う。（３）の工程にてｎシリコン基板８上の第１酸化膜１６ａを残した部分の酸化膜の膜厚および第１酸化膜１６ａを残さなかった部分の酸化膜の膜厚に大きな変化はない（図５４）。
（８）フォト工程（２ＰＥ）により、ＭＯＳ型セル領域のｎシリコン基板８表面に新たに形成された第２酸化膜１６ｂを残す部分と、第２酸化膜１６ｂを残さない部分を形成する。また耐圧構造部では、第２酸化膜１６ｂを開口して、高濃度ｐ領域９を露出する（図５５）。
（９）全面に薄い第３酸化膜１６ｃを形成する。第１酸化膜１６ａおよび第２酸化膜１６ｂがない箇所のｎシリコン基板８表面が露出している箇所に形成された第３酸化膜１６ｃは図９の第１ゲート酸化膜１１となり、第２酸化膜１６ｂと第３酸化膜１６ｃおよび酸化膜１６ｄを合わせたものが図９の第２ゲート酸化膜１８となり、また、第１ゲート酸化膜１６ａ、第２酸化膜１６ｂ、第３酸化膜１６ｃおよび酸化膜１６ｄを合わせたものが耐圧構造用酸化膜１６となる。第３酸化膜１６ｃである第１ゲート酸化膜１１の膜厚は８０ｎｍ程度である（図５６）。
（１０）図９と同様に、ゲート電極となるポリシリコン層１２を形成し、ｐウエル領域９ａ、ｎ+ ソース領域１０、層間絶縁膜１３、金属電極となる金属膜１４、抵抗性を示すフィールドプレート１５を形成する。このフィールドプレートは通常のＭＯＳ型半導体素子のフィールドプレートと同じで、抵抗性を示せば、ａ−Ｓｉ膜に限らない。
【００３５】
尚、（７）の熱処理工程では、ボロンイオンを注入した箇所以外のｎシリコン基板８表面のシリコンは露出がなく、ＭＯＳ型セル領域のｎシリコン基板８の表面に本来想定しないｐ領域が形成されることはない。また、レジスト膜がボロンイオン注入のストッパとなり、その下の第２酸化膜１６ｂにボロンイオンが打ち込まれず、酸化膜の長期信頼性が高まる。
【００３６】
図５７から図６５は、この発明の第６実施例の半導体装置の製造方法であり、工程順に示した製造工程断面図である。尚、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図である。
（１）ｎシリコン基板８上に第１酸化膜１６ａを形成する（図５７）。
（２）フォト工程（１ＰＥ）により、耐圧構造部には、第１酸化膜１６ａを残す部分と第１酸化膜１６ａを残さない部分を形成する。ＭＯＳ型セル領域の第１酸化膜１６ａは残さない（図５８）。
（３）その後、熱処理（９００℃）を行う。この熱処理工程は酸素を流しながら行う。（２）の工程にて、第１酸化膜１６ａを残さない部分のｎシリコン基板８が露出した箇所にも新たな酸化膜１６ｄが形成され、第１酸化膜１６ａを残した他の部分の酸化膜の膜厚は、さらに厚くなる。酸化膜１６ｄの膜厚は、５０ｎｍ程度である（図５９）。
（４）フォト工程（１．５ＰＥ）を行う。フォト工程（１．５ＰＥ）は、ウエハ表面全域にレジスト膜２２を塗布し、露光、エッチングを行い、その後ベークを行い硬化させる。ウエハの表面には、パターニングされたレジスト膜を残す。このとき、耐圧構造部では、（２）のフォト工程（１ＰＥ）により、第１酸化膜１６ａを残した部分と対応してレジスト膜２２を残す。ＭＯＳ型セル領域では、レジスト膜２２を残す部分とレジスト膜２２を残さない部分を形成する（図６０）。
（５）ｎシリコン基板８上からイオン注入でボロンイオンを注入する。レジスト膜２２が残っている部分のｎシリコン基板８にはイオン注入されず（ボロンイオンは、レジスト膜２２を貫通できない）、レジスト膜２２を残さない部分のみにイオン注入でボロンイオンが注入される（図６１）。
（６）レジスト膜２２を剥離液で除去する（図６２）。
（７）その後、熱処理（１１５０℃）により拡散させ、高濃度ｐ領域９を形成する。耐圧構造部に形成された高濃度ｐ領域９はガードリング領域となる。この熱処理工程は、酸素を流しながら行う。そのため、（２）の工程にてｎシリコン基板８上の第１酸化膜１６ａを残した部分（耐圧構造部）の酸化膜の膜厚は、第２酸化膜１６ｂの積層により、さらに厚くなり、その膜厚は、後工程のゲート酸化膜となる第２酸化膜１６ｃの厚みも加わり１０００ｎｍ程度となる。一方、第１酸化膜１６ａを残さなかった部分（ＭＯＳ型セル領域）のｎシリコン基板８が露出した箇所にも新たな第２酸化膜１６ｂが形成され、その膜厚は、後工程のゲート酸化膜となる第３酸化膜１６ｃの厚みも加えて３５０ｎｍ程度となる（図６３）。
（８）フォト工程（２ＰＥ）により、ＭＯＳ型セル領域のｎシリコン基板８表面に新たに形成された第２酸化膜１６ｂを残す部分と、第２酸化膜１６ｂを残さない部分を形成する。また耐圧構造部では、第２酸化膜１６ｂを開口して、高濃度ｐ領域９を露出する（図６４）。
（９）全面に薄い第３酸化膜１６ｃを形成する。第１酸化膜１６ａおよび第２酸化膜１６ｂがない箇所のｎシリコン基板８表面が露出している箇所に形成された第３酸化膜１６ｃは図９の第１ゲート酸化膜１１となり、第２酸化膜１６ｂと酸化膜１６ｄと第３酸化膜１６ｃを合わせたものが図９の第２ゲート酸化膜１８となり、また、第１ゲート酸化膜１６ａ、第２酸化膜１６ｂ、酸化膜１６ｄおよび第３酸化膜１６ｃを合わせたものが耐圧構造用酸化膜１６となる。第３酸化膜１６ｃである第１ゲート酸化膜１１の膜厚は８０ｎｍ程度である（図６５）。
（１０）図９と同様に、ゲート電極となるポリシリコン層１２を形成し、ｐウエル領域９ａ、ｎ+ ソース領域１０、層間絶縁膜１３、金属電極となる金属膜１４、抵抗性を示すフィールドプレート１５を形成する。このフィールドプレートは通常のＭＯＳ型半導体素子のフィールドプレートと同じで、抵抗性を示せば、ａ−Ｓｉ膜に限らない。
【００３７】
尚、第６実施例では、第５実施例の効果に加えて、ボロンイオン注入箇所に酸化膜を被覆しているので、（７）の熱処理工程で外方拡散が起こらない。
前記の第１から第６実施例では、１ＰＥあるいは１．５ＰＥのフォト工程にて、耐圧構造部に第１酸化膜１６ａあるいは第２酸化膜１６ｂを残さない部分を形成したが、２ＰＥ以降に耐圧構造部に高濃度ｐ領域を拡散しガードリング領域を形成する場合もあるので、耐圧構造部全てに第１酸化膜１６ａあるいは第２酸化膜１６ｂを残しても問題ない。また、第６実施例では、１．５ＰＥのフォト工程にて、耐圧構造部にレジスト膜を残したが、耐圧構造部には、厚い第１酸化膜１６ａがあるので、耐圧構造部のレジスト膜２２は必ずしも残さなくても問題ない。
【００３８】
【発明の効果】
この発明によれば、耐圧構造用絶縁膜の膜厚を厚くし、第２ゲート絶縁膜の膜厚を薄くすることで、第２ゲート絶縁膜と第１ゲート絶縁膜の境界部での半導体基板表面の段差を極めて小さくし、この段差を小さくすることで、境界部の電界強度を低下させ、半導体装置の耐圧低下を防止できる。また、耐圧構造用絶縁膜の膜厚を厚くすることで、半導体装置の周辺部での耐圧低下を防止できる。その結果、半導体装置の耐圧良品率を向上させることができる。
【００３９】
また、ＭＯＳ型セル領域のｐウエル領域形成箇所以外を絶縁膜で被覆することで、イオン注入後の熱処理による外方拡散した不純物（ボロンイオン）が再度ｐウエル以外の箇所に再拡散することを防止することで、素子特性の悪化を防止することができる。
さらに、イオン注入する箇所に薄い酸化膜（スクリーン酸化膜）を形成することで、その後の熱処理による外方拡散を防止し、素子特性の悪化を防止することができる。
【００４０】
また、イオン注入時のマスクとなる酸化膜の上にレジスト膜を被覆することで、不純物（ボロンイオン）が酸化膜に導入されることを防止し、酸化膜の長期信頼性を確保することができる。
【図面の簡単な説明】
【図１】 この発明の第１実施例の半導体装置の要部断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図２】 この発明の第１実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図３】 図２に続く、この発明の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図４】 図３に続く、この発明の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図５】 図４に続く、この発明の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図６】 図５に続く、この発明の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図７】 図６に続く、この発明の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図８】 図７に続く、この発明の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図９】 図８に続く、この発明の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図１０】 本発明品と従来品のコレクタ・エミッタ間耐圧の不良率を示す図
【図１１】 コレクタ・エミッタ間耐圧（アバランシェ電圧）と耐圧構造用酸化膜の膜厚の関係を示した図
【図１２】 従来の半導体装置で、（ａ）はチップの平面図、（ｂ）は（ａ）のＡ部拡大図
【図１３】 図１２の要部断面図で、（ａ）は図１２（ｂ）のＡ−Ａ線で切断したＭＯＳ型セル領域の断面図、（ｂ）は図１２（ａ）のＢ−Ｂ線で切断じた耐圧構造部の断面図
【図１４】 従来の半導体装置の製造工程で、工程順に示した要部工程断面図
【図１５】 図１４に続く、従来の半導体装置の製造工程で、工程順に示した要部工程断面図
【図１６】 図１５に続く、従来の半導体装置の製造工程で、工程順に示した要部工程断面図
【図１７】 図１６に続く、従来の半導体装置の製造工程で、工程順に示した要部工程断面図
【図１８】 図１７に続く、従来の半導体装置の製造工程で、工程順に示した要部工程断面図
【図１９】 図１８に続く、従来の半導体装置の製造工程で、工程順に示した要部工程断面図
【図２０】 図１９に続く、従来の半導体装置の製造工程で、工程順に示した要部工程断面図
【図２１】 ＭＯＳセル型領域を例とした、外方拡散の様子を示した図で、（ａ）はイオン注入後の図、（ｂ）は熱処理で外方拡散の様子を示す図、（ｃ）は外方拡散で所定外の箇所にｐ領域９ｂが形成された様子を示す図
【図２２】 本来想定しないｐ領域９ｂが形成された場合のＭＯＳ型セル領域の完成図
【図２３】 この発明の第２実施例の半導体装置の製造工程を、工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図２４】 図２３に続く、この発明の第２実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図２５】 図２４に続く、この発明の第２実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図２６】 図２５に続く、この発明の第２実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図２７】 図２６に続く、この発明の第２実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図２８】 図２７に続く、この発明の第２実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図２９】 図２８に続く、この発明の第２実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図３０】 図２９に続く、この発明の第２実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図３１】 この発明の第３実施例の半導体装置の製造工程を、工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図３２】 図３１に続く、この発明の第３実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図３３】 図３２に続く、この発明の第３実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図３４】 図３３に続く、この発明の第３実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図３５】 図３４に続く、この発明の第３実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図３６】 図３５に続く、この発明の第３実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図３７】 図３６に続く、この発明の第３実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図３８】 図３７に続く、この発明の第３実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図３９】 この発明の第４実施例の半導体装置の製造工程を、工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図４０】 図３９に続く、この発明の第４実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図４１】 図４０に続く、この発明の第４実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図４２】 図４１に続く、この発明の第４実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図４３】 図４２に続く、この発明の第４実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図４４】 図４３に続く、この発明の第４実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図４５】 図４４に続く、この発明の第４実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図４６】 図４５に続く、この発明の第４実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図４７】 図４６に続く、この発明の第４実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図４８】 この発明の第５実施例の半導体装置の製造工程を、工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図４９】 図４８に続く、この発明の第５実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図５０】 図４９に続く、この発明の第５実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図５１】 図５０に続く、この発明の第５実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図５２】 図５１に続く、この発明の第５実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図５３】 図５２に続く、この発明の第５実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図５４】 図５３に続く、この発明の第５実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図５５】 図５４に続く、この発明の第５実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図５６】 図５５に続く、この発明の第５実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図５７】 この発明の第６実施例の半導体装置の製造工程を、工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図５８】 図５７に続く、この発明の第６実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図５９】 図５８に続く、この発明の第６実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図６０】 図５９に続く、この発明の第６実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図６１】 図６０に続く、この発明の第６実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図６２】 図６１に続く、この発明の第６実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図６３】 図６２に続く、この発明の第６実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図６４】 図６３に続く、この発明の第６実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【図６５】 図６４に続く、この発明の第６実施例の半導体装置の製造工程を工程順に示した要部工程断面図で、（ａ）はＭＯＳ型セル領域の断面図、（ｂ）は耐圧構造部の断面図
【符号の説明】
８ ｎシリコン基板
９ 高濃度ｐ領域
９ａ ｐウエル領域
９ｂ ｐ領域
１０ ｎ+ ソース領域
１１ 第１ゲート酸化膜
１２ ポリシリコン膜
１３ 層間絶縁膜
１４ 金属膜
１５ フィールドプレート
１６ 耐圧構造用酸化膜
１６ａ 第１酸化膜
１６ｂ 第２酸化膜
１６ｃ 第３酸化膜
１６ｄ 酸化膜（スクリーン酸化膜）
１８ 第２ゲート酸化膜
２０ チップエッジ
２１ ボロンイオン
２２ レジスト膜
ａ、ｂ 段差
Ｗ 第１ゲート酸化膜の膜厚
Ｄ 耐圧構造用酸化膜の膜厚[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device which is a power semiconductor element having an insulated gate structure such as an IGBT and a method for manufacturing the same.
[0002]
[Prior art]
Semiconductor elements such as IGBTs and MOSFETs are composed of a MOS type cell region (a region including a MOS type gate structure portion and a source region for supplying main current) that is a region through which current flows, and a breakdown voltage structure portion disposed at the periphery of the chip. Is done.
12A and 12B show a conventional semiconductor device, in which FIG. 12A is a plan view of the chip, and FIG. 12B is an enlarged view of a D portion of FIG.
[0003]
In FIG. 6A, the hatched portion is the breakdown voltage structure portion 103 around the chip, the portion excluding the gate pad portion 104 is the MOS type cell region 102, and the terrace gate structure portion and n+An active region including a source region. In the MOS cell region 102, several hundreds of MOS cells having a stripe structure (not shown) are arranged.
In FIG. 5B, a polysilicon layer is formed except for a portion 105 where polysilicon is removed (a portion where there is no polysilicon layer). A thick oxide film 106 is formed under the polysilicon layer. Of these thick oxide films, 107 oxide films are referred to as terrace gate oxide films. Reference numeral 106a denotes a thin oxide film which is a gate oxide film. Usually, there are more cases where the entire MOS type cell region is formed only by the thin gate oxide film 106a on the channel forming region without the terrace gate oxide film. This terrace gate structure is effective in reducing the gate capacity of the chip.
[0004]
13 is a cross-sectional view of the main part of FIG. 12. FIG. 13A is a cross-sectional view of the MOS cell region cut along the line AA in FIG. 12B, and FIG. It is sectional drawing of the pressure | voltage resistant structure part cut | disconnected by the BB line | wire of FIG.
In FIG. 13, a first gate oxide film 118, which is a terrace gate oxide film (thick oxide film), is also formed on part of the gate portion to reduce the gate capacitance. As shown in the enlarged view of the A part in FIG. 5A, the boundary portion (A of the thick gate oxide film 118 formed on the channel formation region and the thick gate oxide film (second gate oxide film 118) of the terrace gate part). Step).
[0005]
14 to 20 are cross-sectional views of main processes shown in the order of processes in the manufacturing process of the conventional semiconductor device. In each figure, (a) is a cross-sectional view of the MOS cell region cut along line AA in FIG. 12, and (b) is a cross-sectional view of the breakdown voltage structure section cut along line BB in FIG. 12 (a). FIG.
(1) A first oxide film 116a is formed on an n silicon substrate 108 (FIG. 14).
(2) By the photo step (1PE), a portion where the first oxide film 116a is left and a portion where the first oxide film 116a is not left are formed (FIG. 15).
(3) Boron ions are implanted. Boron ions 121 enter the portion where the first oxide film 116a is not left (the portion from which the oxide film has been removed) (FIG. 16).
(4) Thereafter, ion-implanted boron is diffused by heat treatment to form a high concentration p region 109. In this heat treatment step, oxygen is flowed. As a result, the second oxide film 116b formed in this heat treatment process is laminated so that the thickness of the oxide film on the n silicon substrate 108 where the first oxide film 116a is left in the process (b) is laminated. As the thickness further increases, a new second oxide film 116b is formed in the portion where the first oxide film 116a is not left (FIG. 17).
(5) A portion where the first oxide film 116a and the second oxide film 116b formed on the surface of the n silicon substrate 108 are left by the photo step (2PE), and a portion where the first oxide film 116a and the second oxide film 116b are not left. (FIG. 18).
(6) A thin third oxide film 116c is formed on the entire surface. The third oxide film 116c formed at the place where the surface of the n silicon substrate 108 where the first oxide film 116a and the second oxide film 116b are not exposed becomes the second gate oxide film 111, and the first oxide film 116a, A combination of the second oxide film 116b and the third oxide film 116c becomes the second gate oxide film 118 and the breakdown voltage structure oxide film 116 (FIG. 19).
(7) The polysilicon layer 112 is formed, and the p-well region 109a, n+A source region 110, an interlayer insulating film 113, a metal film 114 serving as a metal electrode, and a field plate 115 exhibiting resistance are formed. This field playG115 is the same as a resistive field plate of a normal MOS type semiconductor device (FIG. 20).
[0006]
In the MOS type cell region and the breakdown voltage structure portion of FIG. 20, the second gate oxide film 118 and the breakdown voltage structure oxide film 116, which are the first oxide film 116a, the second oxide film 116b, and the third oxide film 116c, are formed simultaneously. The film thickness is about 1000 nm.
In the case of this manufacturing process, a step is also formed on the side of the n silicon substrate 108 at the step portion of the portion A shown in FIG. This is because the formation of the second gate oxide film 118 is performed by the reaction between the silicon crystal and oxygen supplied in the manufacturing process, so that an oxide film layer is also formed on the n silicon substrate 108 side.
[0007]
[Problems to be solved by the invention]
When the portion A is enlarged, a second step d is formed on the upper side, and a first step c is formed on the surface layer of the n silicon substrate 108. The second step “d” increases as the thickness of the second gate oxide film 118 increases, and the first step “c” increases as the thickness of the second gate oxide film 118 increases. In addition, it becomes large when the n silicon substrate temperature is high or the flow rate of oxygen is large under the manufacturing process conditions.
[0008]
As the first step c and the second step d increase, the electric field strength at this point increases, and the collector-emitter breakdown voltage increases.VoltageIs applied, the leakage current increases at this point. This affects the yield rate of semiconductor devices.
Therefore, it is required to make these steps c and d as small as possible.ThisThe Therefore, if the second gate oxide film 118 is made thinner and the step is made smaller, the electric field concentration in the step portion is alleviated. As a result, a decrease in collector-emitter breakdown voltage (avalanche breakdown voltage) in the MOS cell region can be prevented.
[0009]
However, in the conventional device, since the second gate oxide film 118 and the breakdown voltage structure oxide film 116 are formed under the same conditions, the thickness of the breakdown voltage structure oxide film 116 is reduced. Collector-emitter breakdown voltage decreases.
An object of the present invention is to provide a semiconductor device that solves the above-described problems and can prevent a decrease in breakdown voltage between a collector and an emitter in both a MOS type cell region portion and a breakdown voltage structure portion.
[0010]
[Means for Solving the Problems]
To achieve the above object, a plurality of layers formed on the surface layer of the semiconductor substrate of the first conductivity type.Second conductivity type regionA withstand voltage structure having an insulation film for a withstand voltage structure formed on the surface of the periphery of the semiconductor substrate;Second conductivity type region surrounded by breakdown voltage structureThe source region of the first conductivity type formed in the surface layer ofArea,The source region and the semiconductor substrateSecond conductivity type regionFirst gate insulation formed on the surfacefilm,A second gate insulating film which is thicker than the first gate insulating film and formed on the semiconductor substrate continuously with the first gate insulating filmMOS cell area consisting ofSemiconductor device havingIn this manufacturing method, the following steps are taken.
[0011]
FirstForming a first insulating film on a semiconductor substrate of one conductivity type, selectively removing the first insulating film, and using the first insulating film as a mask, the second conductivity type of the semiconductor substrate;Second conductivity type regionAnd selectively forming the first insulationMembraneA step of removing leaving a portion to be a withstand voltage structure insulating film, a step of forming a second insulating film on the entire surface of the semiconductor substrate, a portion of the second insulating film to be a withstand voltage structure insulating film, andOf the MOS type cell regionRemoving the portion to be the second gate insulating filmAnd beforeOn the entire surface of the semiconductor substrateThinner than the first insulating film and the second insulating filmForming a third insulating film;The second conductivity type region of the breakdown voltage structure and the MOS type cell regionSelectively removing the upper third insulating film;Forming a source region of a first conductivity type in the second conductivity type region of the MOS type cell region;A manufacturing process including
[0012]
The thickness of the second gate insulating film formed by stacking the second insulating film and the third insulating film is the breakdown voltage formed by stacking the first insulating film, the second insulating film, and the third insulating film. Since the thickness of the second insulating film is smaller than the thickness of the structural insulating film, the second gate insulating film is thinner than the conventional case where the thickness of the second gate insulating film is the same as the thickness of the withstand voltage structural insulating film. A step generated on the semiconductor substrate side at the boundary between the film and the first gate insulating film can be reduced. Small stepTheBy being able to do so, electric field concentration in the first and second gate insulating films and on the surface of the semiconductor substrate can be reduced. As a result, the breakdown voltage failure between the collector and the emitter is reduced, and the yield rate can be improved.
[0013]
Also,FirstForming a first insulating film on a semiconductor substrate of one conductivity type, selectively removing the first insulating film, and ion-implanting a second conductivity impurity using the first insulating film as a mask; A step of removing the first insulating film leaving a portion to be a dielectric structure for a withstand voltage structure; andWhile flowing oxygenA second conductivity type region is selectively formed on the surface layer of the semiconductor substrate by heat treatment.AndA step of forming a second insulating film on the entire surface, a location where the second insulating film becomes a dielectric structure for a withstand voltage structure, andOf the MOS type cell regionRemoving the portion to be the second gate insulating filmAnd beforeOn the entire surface of the semiconductor substrateThinner than the first insulating film and the second insulating filmForming a third insulating film;The second conductivity type region of the breakdown voltage structure and the MOS type cell regionSelectively removing the upper third insulating film;Forming a source region of a first conductivity type in the second conductivity type region of the MOS type cell region;A manufacturing process including
[0014]
Also,FirstForming a first insulating film on a semiconductor substrate of one conductivity type; selectively removing the first insulating film; and ion-implanting a second conductivity type impurity using the first insulating film as a maskAndHeat treatment is performed on the surface layer of the semiconductor substrate.The second conductivity type regionSelectively formingRemoving the first insulating film leaving a portion to be an insulating film for a withstand voltage structure;Forming a second insulating film on the entire surface, and forming the second insulating film into a portion to be an insulating film for a withstand voltage structure andOf the MOS type cell regionRemoving the portion to be the second gate insulating filmAnd thinner than the first insulating film and the second insulating filmForming a third insulating film;The second conductivity type region of the breakdown voltage structure and the MOS type cell regionSelectively removing the upper third insulating film;Forming a source region of a first conductivity type in the second conductivity type region of the MOS type cell region;A manufacturing process including
[0015]
Also,FirstForming a first insulating film on a semiconductor substrate of one conductivity type; andLeaving a place to be the insulating film for the withstand voltage structureRemoving, forming a second insulating film on the entire surface,Second breakdown type region of the breakdown voltage structure and the MOS type cell regionRemoving the second insulating film at the location where the film is to be formed; andIn the MOS type cell regionFirst2Insulation filmAs a mask and the pressure-resistant structure portionA first insulating film;SaidSecond insulating filmTheAs a maskTheA step of ion-implanting a second conductivity type impurity and a heat treatment to form a surface layer of the semiconductor substrate;The second conductivity type regionSelectively forming the second insulating film, leaving a portion to be the second gate insulating film and a portion to be the insulating film for the withstand voltage structure.The second insulating film in the MOS type cell region;Removing, andThinner than the first insulating film and the second insulating filmForming a third insulating film;The second conductivity type region of the breakdown voltage structure and the MOS type cell regionSelectively removing the upper third insulating film;Forming a source region of a first conductivity type in the second conductivity type region of the MOS type cell region;A manufacturing process including
[0016]
Also,FirstForming a first insulating film on a semiconductor substrate of one conductivity type; andLeaving a place to be the insulating film for the withstand voltage structureRemoving, forming a second insulating film on the entire surface,Second breakdown type region of the breakdown voltage structure and the MOS type cell regionRemoving the second insulating film at the location where the film is to be formed, forming the fourth insulating film over the entire surface,The first insulating film and the second insulating filmA step of ion-implanting a second conductivity type impurity as a mask through the fourth insulating film and a heat treatment are performed on the surface layer of the semiconductor substrate.The second conductivity type regionSelectively removing the second insulating film and the fourth insulating film, leaving a portion to be the second gate insulating film and a portion to be the withstand voltage structure insulating film,Thinner than the first insulating film, the second insulating film, and the fourth insulating filmForming a third insulating film;The second conductivity type region of the breakdown voltage structure and the MOS type cell regionSelectively removing the upper third insulating film;Forming a source region of a first conductivity type in the second conductivity type region of the MOS type cell region;A manufacturing process including
[0017]
Also,FirstForming a first insulating film on a semiconductor substrate of one conductivity type; andLeaving a place to be the insulating film for the withstand voltage structureRemoving, covering the entire surface with a second insulating film, covering the entire surface with a photoresist,The second conductivity type region formation location and the location where the first insulating film is removedPatterning, andSecond conductivity type regionRemoving the second insulating film at a position where the first insulating film is formed and the second insulating film at a position where the first insulating film is removed, using the photoresist as a mask;SaidUsing the photoresist as a mask, a step of ion-implanting a second conductivity type impurity, a step of removing the photoresist, and a heat treatment are performed on the surface layer of the semiconductor substrate.Second conductivity type regionSelectively removing the second insulating film, leaving a portion to be the withstand voltage structure insulating film and a portion to be the second gate insulating film, andThinner than the first insulating film and the second insulating filmForming a third insulating film;The second conductivity type region of the breakdown voltage structure and the MOS type cell regionSelectively removing the upper third insulating film;Forming a source region of a first conductivity type in the second conductivity type region of the MOS type cell region;A manufacturing process including
[0018]
Also,FirstForming a first insulating film on a semiconductor substrate of one conductivity type; andLeaving a place to be the insulating film for the withstand voltage structureA step of removing, a step of forming a fourth insulating film on the entire surface, a step of covering the fourth insulating film with a photoresist, a well region forming portion, and a first portion of the portion where the first insulating film has been removed. A step of removing the photoresist on the fourth insulating film; a step of ion-implanting a second conductivity type impurity through the fourth insulating film using the photoresist as a mask; a step of removing the photoresist; and a heat treatment And selectively forming the second conductivity type region on the surface layer of the semiconductor substrate.And forming a second insulating film on the entire surface.And the step2Removing the insulating film and the fourth insulating film, leaving a portion to be the withstand voltage structure insulating film and a portion to be the second gate insulating film;Thinner than the first insulating film, the second insulating film, and the fourth insulating filmForming a third insulating film;The second conductivity type region of the breakdown voltage structure and the MOS type cell regionSelectively removing the upper third insulating film;Forming a source region of a first conductivity type in the second conductivity type region of the MOS type cell region;A manufacturing method including
[0019]
By doing so, outward diffusion of the ion-implanted impurity is prevented by the second insulating film and the fourth insulating film, and the device characteristics can be stabilized. Further, by ion implantation through the photoresist, introduction of impurity ions into the insulating film is suppressed, and the reliability of the insulating film is improved.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
1A and 1B are cross-sectional views of the main part of the semiconductor device according to the first embodiment of the present invention. FIG. 1A is a cross-sectional view of a MOS type cell region, and FIG. FIGS. 1A and 1B correspond to FIGS. 2A and 2B.
In FIG. 1, a high concentration p region 9 is formed in a surface layer of an n silicon substrate 8 in a MOS type cell region and a breakdown voltage structure, and a p well region 9a is formed in a surface layer of the n silicon substrate 8 in the MOS type cell region. Formed on the surface layer of the p-well region 9a.+A source region 10 is formed. n+A second gate oxide film 11 serving as an oxide film having a MOS gate structure is formed on a p-well region sandwiched between the source region 10 and the n silicon substrate 8, and second and terrace gate oxide films are formed on the n silicon substrate 8. A certain second gate oxide film 18 is formed, and a polysilicon layer 12 to be a gate electrode is formed on these gate oxide films 11 and 18. An interlayer insulating film 13 is formed on the polysilicon layer 12, and the interlayer insulating film 13 and n+On the exposed part (contact hole part) of the source region 10 and the high-concentration p region 9, a metal film 14 to be a source electrode is formed.
[0021]
On the other hand, the high concentration p region 9 of the breakdown voltage structure portion becomes a p guard ring region, and an oxide film 16 for breakdown voltage structure is formed on the n silicon region 8 sandwiched between the high concentration p regions 9. A metal film 14 is formed on the breakdown voltage structure oxide film 16 via an interlayer insulating film 13, and the metal film 14 and the high concentration p region 9 are connected. A field plate 15 of a resistive a-Si film is formed on the metal film 14. In the figure, 20 indicates the chip edge of a chip which is an n silicon substrate.
[0022]
The film thickness W of the second gate oxide film 18 is made thinner than the film thickness D of the breakdown voltage structure oxide film 16. Further, when the portion A which is the boundary between the second gate oxide film 18 and the first gate oxide film 11 is enlarged, a step b is formed on the upper side and a step is formed on the surface layer of the n silicon substrate 8. The step a is extremely small because the film thickness W of the second gate oxide film 18 is smaller than the step c in the case of the thick first gate oxide film as in the conventional element. As a result, as will be described later, the maximum electric field strength in the oxide film and on the silicon surface is reduced, and the reduction in the collector-emitter breakdown voltage at this point is prevented. In addition, since the step b is smaller than the conventional step d, the electric field strength is relaxed and the breakdown voltage between the collector and the emitter is prevented from being lowered. Further, since the oxide film (the oxide film 16 for withstand voltage structure) in the breakdown voltage structure is as thick as the conventional element, the breakdown voltage between the collector and the emitter does not decrease at this point.
[0023]
In the above, the MOS type cell region is a second gate oxide film which is a terrace gate oxide film having a thickness larger than that of the first gate oxide film on the channel formation region, and most of the surface of the n silicon substrate 8 is covered. Therefore, the gate capacitance can be reduced as compared with the case where the n-silicon substrate 8 not having the terrace gate structure is covered with the thin first gate oxide film.
[0024]
The breakdown voltage structure has a structure in which a p guard ring region formed of several high-concentration p regions 9 and a field plate 15 made of a resistive a-Si film are used in combination.
The film thickness of the second gate oxide film 18 which is the terrace gate of the MOS type cell region is about 350 nm, the film thickness of the first gate oxide film 11 for forming the channel is about 80 nm, and the oxide film 16 for the breakdown voltage structure. The film thickness is about 1000 nm. However, the thickness of each film in the figure is drawn to the same thickness.
[0025]
FIGS. 2 to 9 are cross-sectional views of essential parts showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention in the order of processes. In each figure, (a) is a cross-sectional view of a MOS type cell region, and (b) is a cross-sectional view of a breakdown voltage structure portion.
(1) A first oxide film 16a is formed on an n silicon substrate 8 (FIG. 2).
(2) By the photo step (1PE), a portion where the first oxide film 16a is left and a portion where the first oxide film 16a is not left are formed (FIG. 3). (3) Boron ions are implanted by ion implantation into a portion of the n silicon substrate 8 where the first oxide film 16a is not left (FIG. 4).
(4) By the photo process (1.5PE: 1.5PE is a process between the 1PE process and the 2PE process), the first oxide film 16a of the breakdown voltage structure portion is left, and the first oxidation of the MOS type cell region is performed. The film 16a is not left (FIG. 5).
(5) Thereafter, diffusion is performed by heat treatment (1150 ° C.) to form the high concentration p region 9. The high concentration p region 9 formed in the breakdown voltage structure portion becomes a p guard ring region. This heat treatment step is performed while flowing oxygen. Therefore, the thickness of the oxide film in the portion (breakdown voltage structure portion) where the first oxide film 16a is left on the n silicon substrate 8 in the step (2) is further increased by the lamination of the second oxide film 16b. The film thickness is about 1000 nm with the addition of the thickness of the third oxide film 16c to be a gate oxide film in a later process. On the other hand, a second oxide film 16b is newly formed at a portion where the first silicon oxide film 16a is not left (MOS type cell region) where the n silicon substrate 8 is exposed.(Fig. 6)The film thickness is about 350 nm, including the thickness of the third oxide film 16c, which will be a gate oxide film in a later process.
(6) By the photolithography step (2PE), a portion where the second oxide film 16b newly formed on the surface of the n silicon substrate 8 in the MOS type cell region is left and a portion where the second oxide film 16b is not left are formed. In the breakdown voltage structure, the second oxide film 16b is opened to expose the surface of the high concentration p region 9 (FIG. 7).
(7) A third oxide film 16c is formed on the entire surface.(Fig. 8). The third oxide film 16c formed in the portion where the surface of the n silicon substrate 8 where the first oxide film 16a and the second oxide film 16b are not exposed becomes the first gate oxide film 11 in FIG. The combination of the film 16b and the third oxide film 16c is the second gate oxide film 18 of FIG. 9, and the combination of the first oxide film 16a, the second oxide film 16b and the third oxide film 16c is a breakdown voltage structure. The oxide film 16 is used. The thickness of the first gate oxide film 11 which is the third oxide film 16c is about 80 nm.
(8) A polysilicon layer 12 to be a gate electrode is formed, and a p-well region 9a, n+A source region 10, an interlayer insulating film 13, a metal film 14 that is an Al-Si metal electrode, and a field plate 15 that is a resistive a-Si film are formed. This field plate is the same as a resistive field plate of a normal MOS device, and is not limited to an a-Si film as long as the resistance is exhibited.
[0026]
Table 1 shows an example in which the relationship between the thickness of the second gate oxide film of the terrace gate structure of the present invention and the conventional terrace gate structure and the maximum electric field strength is simulated.
[0027]
[Table 1]
In the terrace gate structure of the present invention in which the thickness of the gate oxide film is 350 nm, the maximum electric field strength is reduced by 20% inside the oxide film and 24% on the surface of the silicon substrate as compared with the conventional terrace gate structure.
[0028]
FIG. 10 is a diagram showing the failure rate of the collector-emitter breakdown voltage between the product of the present invention and the conventional product. The defect rate of the product of the present invention is reduced to about half.
FIG. 11 is a graph showing the relationship between the collector-emitter breakdown voltage (avalanche voltage) and the thickness of the breakdown voltage structure oxide film.
When the thickness of the oxide film is 350 nm, the collector-emitter breakdown voltage is reduced to 90% compared to 1000 nm. This is because, in the case of the conventional terrace gate structure, the thickness of the oxide film for breakdown voltage structure is the same as the thickness of the second gate oxide film in the terrace gate portion, and the breakdown voltage when the second gate oxide film is formed at 350 nm. The thickness of the structural oxide film is also 350 nm, which means that the breakdown voltage is reduced to 90%. In the product of the present invention, since the thickness of the oxide film for breakdown voltage structure can be set to 1000 nm and the thickness of the second gate oxide film can be set to 350 nm, a decrease in breakdown voltage can be prevented.
[0029]
In the above process, after the boron ion implantation (3) process), the oxide film in the MOS type cell region is completely removed by the photo process (process (4)), and then boron ions are diffused by heat treatment ((5 Step)).
In this case, in the step (5), depending on the conditions of the heat treatment, the implanted boron ions cause outward diffusion (out diffusion) during the heat treatment and diffuse out of the wafer. There is a risk that ions may diffuse again into the wafer and change the characteristics of the device. FIG. 21 shows the MOSType cellFIGS. 5A and 5B show a state of outward diffusion taking a region as an example. FIG. 5A shows a state of FIG. 5A after ion implantation, and FIG. 5B shows a state of outward diffusion by heat treatment. FIG. 4C is a diagram showing a state in which the p region 9b is formed at a place outside a predetermined position by outward diffusion. After the start of the heat treatment in FIG. 5B, the implanted boron ions 21 cause outward diffusion, and the boron ions 21 are re-diffused also into portions where the boron ions 21 are not originally introduced.
[0030]
When such outward diffusion occurs, a p region 9b that is not originally assumed may be formed on the surface of the MOS type cell region as shown in FIG. FIG. 22 is an example of a completed drawing of the MOS type cell region when the p region 9b that is not supposed to be formed is formed.
In this case, the surface of the n silicon substrate 8 in the MOS type cell region is covered with the p region 9b, and the formed n channel is not connected to the n silicon substrate 8 when the depth of the p region 9b is deep. Therefore, even if a gate voltage is applied, n+Electrons cannot be injected from the source region into the n silicon substrate 8, and the MOS device cannot flow a collector current and does not function as a switching element. As a measure for preventing this, the following embodiment will be described.
[0031]
23 to 30 show a method of manufacturing a semiconductor device according to the second embodiment of the present invention and are manufacturing process sectional views shown in the order of processes. 2A is a cross-sectional view of a MOS type cell region, and FIG. 2B is a cross-sectional view of a breakdown voltage structure portion.
(1) A first oxide film 16a is formed on an n silicon substrate 8 (FIG. 23).
(2) By the photo step (1PE), a portion where the first oxide film 16a is left and a portion where the first oxide film 16a is not left are formed (FIG. 24).
(3) Boron ions are implanted from above the n silicon substrate 8 by ion implantation. The portion where the first oxide film 16a on the n silicon substrate 8 remains is not ion-implanted into the n silicon substrate 8 (boron ions cannot penetrate the first oxide film 16a). Boron ions 21 are implanted by ion implantation into the portion where the 1 oxide film 16a is not left (FIG. 25).
(4) Thereafter, as shown in FIG. 5A, without removing the first oxide film 16a in the MOS type cell region, the boron ions 21 are diffused by heat treatment (1150 ° C.) to form the high-concentration p region 9. . The high concentration p region 9 formed in the breakdown voltage structure portion becomes a guard ring region. This heat treatment step is performed without flowing oxygen. In the step (2), there is a large change in the thickness of the oxide film on the n silicon substrate 8 where the first oxide film 16a is left and the thickness of the oxide film on the portion where the first oxide film 16a is not left. No (FIG. 26).
(5) By the photo step (1.5PE), the first oxide film 16a in the breakdown voltage structure portion is left, and the first oxide film 16a in the MOS type cell region is not left (FIG. 27).
(6) Thereafter, heat treatment (1150 ° C.) is performed. This heat treatment step is performed while flowing oxygen. Therefore, the thickness of the oxide film in the portion (breakdown voltage structure portion) where the first oxide film 16a is left on the n silicon substrate 8 in the step (2) is further increased by the lamination of the second oxide film 16b. The film thickness is about 1000 nm with the addition of the thickness of the third oxide film 16c to be a gate oxide film in a later process. On the other hand, a new second oxide film 16b is also formed at a portion where the first oxide film 16a is not left (MOS type cell region) where the n silicon substrate 8 is exposed, and the film thickness thereof is a gate oxide film in a later step. In addition, the thickness of the third oxide film 16c is about 350 nm. At this time, the high-concentration p region 9 diffused in the step (4) is further diffused (FIG. 28).
(7) By the photolithography step (2PE), a portion where the newly formed second oxide film 16b is left on the surface of the n silicon substrate 8 in the MOS type cell region and a portion where the second oxide film 16b is not left are formed. In the breakdown voltage structure, the second oxide film 16b is opened to expose the high concentration p region 9 (FIG. 29).
(8) A thin third oxide film 16c is formed on the entire surface. The third oxide film 16c formed in the portion where the surface of the n silicon substrate 8 where the first oxide film 16a and the second oxide film 16b are not exposed becomes the first gate oxide film 11 in FIG. The combination of the film 16b and the third oxide film 16c is the second gate oxide film 18 of FIG. 9, and the combination of the first oxide film 16a, the second oxide film 16b and the third oxide film 16c is a breakdown voltage structure. The oxide film 16 is formed. The thickness of the first gate oxide film 11 which is the third oxide film 16c is about 80 nm (FIG. 30).
(9) As in FIG. 9, a polysilicon layer 12 to be a gate electrode is formed, and p well regions 9a, n+A source region 10, an interlayer insulating film 13, a metal film 14 serving as a metal electrode, and a field plate 15 exhibiting resistance are formed. This field plate is the same as a field plate of a normal MOS type semiconductor element, and is not limited to an a-Si film as long as it exhibits resistance.
[0032]
Note that the surface of the n silicon substrate 8 is exposed in the step (5). At this time, since the boron ion diffusion step is performed, the ion concentration on the silicon surface is very low. The amount of outward diffusion of boron ions 21 is extremely small by the heat treatment in the process. Therefore, no change occurs in the element characteristics.
FIG. 31 to FIG. 38 show a manufacturing method of the semiconductor device according to the third embodiment of the present invention, and are manufacturing process sectional views shown in the order of processes. 2A is a cross-sectional view of a MOS type cell region, and FIG. 2B is a cross-sectional view of a breakdown voltage structure portion.
(1) A first oxide film 16a is formed on an n silicon substrate 8 (FIG. 31).
(2) A portion where the first oxide film 16a is left and a portion where the first oxide film 16a is not left are formed by a photo step (1PE). The first oxide film 16a in the MOS cell region is not left (FIG. 32).
(3) Thereafter, heat treatment (1150 ° C.) is performed. This heat treatment step is performed while flowing oxygen. Therefore, the thickness of the oxide film in the portion (breakdown voltage structure portion) where the first oxide film 16a is left on the n silicon substrate 8 in the step (2) is further increased by the lamination of the second oxide film 16b. The film thickness is about 1000 nm with the addition of the thickness of the third oxide film 16c to be a gate oxide film in a later process. On the other hand, a new second oxide film 16b is also formed in a portion where the first silicon oxide film 16a is not left (MOS type cell region) where the n silicon substrate 8 is exposed, and the thickness thereof is determined as a gate oxide film in a later step. In addition, the thickness of the third oxide film 16c is about 350 nm (FIG. 33).
(4) By the photo step (1.5PE), the breakdown voltage structure portion forms a portion where the second oxide film 16b is left and a portion where the second oxide film 16b is not left. In the MOS type cell region, a portion where the second oxide film 16b is left and a portion where the second oxide film 16b is not left are formed (FIG. 34).
(5) Boron ions are implanted from above the n silicon substrate 8 by ion implantation. The portion where the first oxide film 16a or the second oxide film 16b on the n silicon substrate 8 remains is not ion-implanted into the n silicon substrate 8 (boron ions are generated in the first oxide film 16a or the second oxide film 16b. Boron ions are implanted by ion implantation into the portion of the n silicon substrate 8 where the first oxide film 16a and the second oxide film 16b are not left (FIG. 35).
(6) Thereafter, diffusion is performed by heat treatment (1150 ° C.) to form a high concentration p region 9. The high concentration p region 9 formed in the breakdown voltage structure portion becomes a guard ring region. This heat treatment step is performed without flowing oxygen. In the step (4), there is no significant change in the thickness of the oxide film in the portion where the second oxide film 16b is left on the n silicon substrate 8 and the thickness of the oxide film in the portion where the second oxide film 16b is not left. (FIG. 36).
(7) By the photolithography step (2PE), a portion where the newly formed second oxide film 16b is left on the surface of the n silicon substrate 8 in the MOS type cell region and a portion where the second oxide film 16b is not left are formed. In the breakdown voltage structure, the second oxide film 16b is opened to expose the high concentration p region 9 (FIG. 37).
(8) A thin third oxide film 16c is formed on the entire surface. The third oxide film 16c formed in the portion where the surface of the n silicon substrate 8 where the first oxide film 16a and the second oxide film 16b are not exposed becomes the first gate oxide film 11 in FIG. The combination of the film 16b and the third oxide film 16c becomes the second gate oxide film 18 of FIG. 9, and the combination of the first gate oxide film 16a, the second oxide film 16b, and the third oxide film 16c is a breakdown voltage. This becomes the structural oxide film 16. The film thickness of the first gate oxide film 11 which is the third oxide film 16c is about 80 nm (FIG. 38).
(9) As in FIG. 9, a polysilicon layer 12 to be a gate electrode is formed, and p well regions 9a, n+A source region 10, an interlayer insulating film 13, a metal film 14 serving as a metal electrode, and a field plate 15 exhibiting resistance are formed. This field plate is the same as a field plate of a normal MOS type semiconductor element, and is not limited to an a-Si film as long as it exhibits resistance.
[0033]
At the stage of the step (6), silicon on the surface of the n silicon substrate 8 other than the portion where boron ions are implanted is not exposed, and the surface of the n silicon substrate 8 in the MOS type cell region is not supposed to be originally shown in FIG. The p region 9b as shown in FIG.
FIG. 39 to FIG. 47 show a manufacturing method of the semiconductor device according to the fourth embodiment of the present invention, and are manufacturing process sectional views shown in the order of processes. 2A is a cross-sectional view of a MOS type cell region, and FIG. 2B is a cross-sectional view of a breakdown voltage structure portion.
(1) A first oxide film 16a is formed on an n silicon substrate 8 (FIG. 39).
(2) A portion where the first oxide film 16a is left and a portion where the first oxide film 16a is not left are formed by a photo step (1PE). The first oxide film 16a in the MOS cell region is not left (FIG. 40).
(3) Thereafter, heat treatment (1150 ° C.) is performed. This heat treatment step is performed while flowing oxygen. Therefore, the thickness of the oxide film in the portion (breakdown voltage structure portion) where the first oxide film 16a is left on the n silicon substrate 8 in the step (2) is further increased by the lamination of the second oxide film 16b. The film thickness is about 1000 nm with the addition of the thickness of the third oxide film 16c to be a gate oxide film in a later process. On the other hand, a new second oxide film 16b is also formed in a portion where the first silicon oxide film 16a is not left (MOS type cell region) where the n silicon substrate 8 is exposed, and the thickness thereof is determined as a gate oxide film in a later step. In addition, the thickness of the third oxide film 16c becomes about 350 nm (FIG. 41).
(4) By the photo step (1.5PE), the breakdown voltage structure portion forms a portion where the first oxide film 16a and the second oxide film 16b are left and a portion where the first oxide film 16b is not left. In the MOS cell region, a portion where the second oxide film 16b is left and a portion where it is not left are formed (FIG. 42).
(5) Thereafter, heat treatment (900 ° C.) is performed. This heat treatment step is performed while flowing oxygen. In the step (4), a new oxide film 16d is also formed at the portion where the n silicon substrate 8 where the second oxide film 16b is not left is exposed, leaving the first oxide film 16a or the second oxide film 16b. In addition, the thickness of the oxide film in other portions is further increased. The oxide film 16d is a screen oxide film, and its film thickness is about 50 nm (FIG. 43).
(6) Boron ions are implanted from above the n silicon substrate 8 by ion implantation. The portion where the first oxide film 16a or the second oxide film 16b on the n silicon substrate 8 remains is not ion-implanted into the n silicon substrate 8 (boron ions are generated in the first oxide film 16a or the second oxide film 16b. A new oxide film on the portion of the n silicon substrate 8 where the first oxide film 16a and the second oxide film 16b are not left.16Boron ions are implanted by ion implantation through d (the oxide film 16d is as thin as about 50 nm, so that the boron ion can penetrate the oxide film 16d if the boron irradiation acceleration voltage is increased) (FIG. 44).
(7) Thereafter, diffusion is performed by heat treatment (1150 ° C.) to form the high concentration p region 9. The high concentration p region 9 formed in the breakdown voltage structure portion becomes a guard ring region. This heat treatment step is performed without flowing oxygen. There is no significant change in the thickness of the oxide film in the portion where the second oxide film 16b is left on the n silicon substrate 8 and the thickness of the oxide film in the portion where the second oxide film 16b is not left in the step (6). (FIG. 45).
(8) Newly formed on the surface of the n-type silicon substrate 8 in the MOS type cell region by the photo step (2PE).Oxide film 16dThe part to leave,Oxide film 16dThe part which does not leave is formed. In the pressure resistant structure,Oxide film 16dTo expose the high-concentration p region 9 (FIG. 46).
(9) A thin third oxide film 16c is formed on the entire surface. The third oxide film 16c formed at the place where the surface of the n silicon substrate 8 where the second oxide film 16b and the oxide film 16d are not exposed is the first gate oxide film 11 of FIG. 9, and the second oxide film 16b. 9 and the third oxide film 16c and the oxide film 16d correspond to the second gate oxide film 18 of FIG. 9, and the first gate oxide film 16a, the second oxide film 16b, the third oxide film 16c and the oxide film The combination of the films 16d is the breakdown voltage structure oxide film 16. The thickness of the first gate oxide film 11 which is the third oxide film 16c is about 80 nm (FIG. 47).
(10) As in FIG. 9, a polysilicon layer 12 to be a gate electrode is formed, and p well regions 9a, n+A source region 10, an interlayer insulating film 13, a metal film 14 serving as a metal electrode, and a field plate 15 exhibiting resistance are formed. This field plate is the same as a field plate of a normal MOS type semiconductor element, and is not limited to an a-Si film as long as it exhibits resistance.
[0034]
The difference from the third embodiment is that an oxide film (screen oxide film) of about 50 nm is formed (step (5)) before boron ion implantation (step (6)). By forming the oxide film of about 50 nm, outward diffusion can be prevented by the heat treatment of (7).
48 to 56 show a semiconductor device manufacturing method according to the fifth embodiment of the present invention, and are manufacturing process sectional views shown in the order of processes. 2A is a cross-sectional view of a MOS type cell region, and FIG. 2B is a cross-sectional view of a breakdown voltage structure portion.
(1) A first oxide film 16a is formed on an n silicon substrate 8 (FIG. 48).
(2) By the photo step (1PE), a portion where the first oxide film 16a is left and a portion where the first oxide film 16a is not left are formed in the breakdown voltage structure portion. The first oxide film 16a in the MOS type cell region is not left (FIG. 49).
(3) Thereafter, heat treatment (1150 ° C.) is performed. This heat treatment step is performed while flowing oxygen. Therefore, the thickness of the oxide film in the portion (breakdown voltage structure portion) where the first oxide film 16a is left on the n silicon substrate 8 in the step (2) is further increased by the lamination of the second oxide film 16b. The film thickness is about 1000 nm with the addition of the thickness of the third oxide film 16c to be a gate oxide film in a later process. On the other hand, a new second oxide film 16b is also formed in a portion where the first silicon oxide film 16a is not left (MOS type cell region) where the n silicon substrate 8 is exposed, and the thickness thereof is determined as a gate oxide film in a later step. In addition, the thickness of the third oxide film 16c is about 350 nm (FIG. 50).
(4) A photo process (1.5PE) is performed. In the photo step (1.5PE), a resist film 22 is applied over the entire wafer, exposed and etched, and then baked and cured. Thereafter, the first oxide film 16a and the second oxide film 16b are etched. Thereafter, a resist film is left on the wafer surface. At this time, in the breakdown voltage structure portion, a portion where the second oxide film 16b is left and a portion where the second oxide film 16b is not left are formed (FIG. 51).
(5) Boron ions are implanted from above the n silicon substrate 8 by ion implantation. Ions are not implanted into the n silicon substrate 8 where the resist film 22 remains (boron ions cannot penetrate the resist film 22), and boron ions 21 are implanted only into the portion where the resist film 22 does not remain. (FIG. 52).
(6) The resist film 22 is removed with a stripping solution (FIG. 53).
(7) Thereafter, diffusion is performed by heat treatment (1150 ° C.) to form the high concentration p region 9. The high concentration p region 9 formed in the breakdown voltage structure portion becomes a guard ring region. This heat treatment step is performed without flowing oxygen. In the step (3), there is no significant change in the thickness of the oxide film on the n silicon substrate 8 where the first oxide film 16a is left and the thickness of the oxide film on the portion where the first oxide film 16a is not left. (FIG. 54).
(8) By the photolithography step (2PE), a portion for leaving the newly formed second oxide film 16b on the surface of the n silicon substrate 8 in the MOS type cell region and a portion for leaving no second oxide film 16b are formed. In the breakdown voltage structure, the second oxide film 16b is opened to expose the high concentration p region 9 (FIG. 55).
(9) A thin third oxide film 16c is formed on the entire surface. The third oxide film 16c formed in the portion where the surface of the n silicon substrate 8 where the first oxide film 16a and the second oxide film 16b are not exposed becomes the first gate oxide film 11 in FIG. The combination of the film 16b, the third oxide film 16c, and the oxide film 16d becomes the second gate oxide film 18 of FIG. 9, and the first gate oxide film 16a, the second oxide film 16b, the third oxide film 16c, and the oxide film The combination of the films 16d is the breakdown voltage structure oxide film 16. The thickness of the first gate oxide film 11 which is the third oxide film 16c is about 80 nm (FIG. 56).
(10) As in FIG. 9, a polysilicon layer 12 to be a gate electrode is formed, and p well regions 9a, n+A source region 10, an interlayer insulating film 13, a metal film 14 serving as a metal electrode, and a field plate 15 exhibiting resistance are formed. This field plate is the same as a field plate of a normal MOS type semiconductor element, and is not limited to an a-Si film as long as it exhibits resistance.
[0035]
In the heat treatment step (7), silicon on the surface of the n silicon substrate 8 other than the portion into which boron ions are implanted is not exposed, and an unexpected p region is formed on the surface of the n silicon substrate 8 in the MOS type cell region. Never happen. Further, the resist film serves as a stopper for boron ion implantation, and boron ions are not implanted into the second oxide film 16b therebelow, so that the long-term reliability of the oxide film is enhanced.
[0036]
57 to 65 show a manufacturing method of the semiconductor device according to the sixth embodiment of the present invention, and are manufacturing process sectional views shown in the order of processes. 2A is a cross-sectional view of a MOS type cell region, and FIG. 2B is a cross-sectional view of a breakdown voltage structure portion.
(1) A first oxide film 16a is formed on an n silicon substrate 8 (FIG. 57).
(2) By the photo step (1PE), a portion where the first oxide film 16a is left and a portion where the first oxide film 16a is not left are formed in the breakdown voltage structure portion. The first oxide film 16a in the MOS cell region is not left (FIG. 58).
(3) Thereafter, heat treatment (900 ° C.) is performed. This heat treatment step is performed while flowing oxygen. In step (2),First oxide film 16aA new oxide film 16d is also formed at a portion where the n silicon substrate 8 in the portion that does not leave is exposed, and the first oxide film 16 is formed.aThe thickness of the remaining oxide film in the remaining part is further increased. The film thickness of the oxide film 16d is about 50 nm (FIG. 59).
(4) A photo process (1.5PE) is performed. In the photo step (1.5PE), a resist film 22 is applied over the entire wafer surface, exposed and etched, and then baked and cured. A patterned resist film is left on the surface of the wafer. At this time, in the breakdown voltage structure portion, the resist film 22 is left corresponding to the portion where the first oxide film 16a is left by the photo step (1PE) of (2). In the MOS type cell region, a portion where the resist film 22 is left and a portion where the resist film 22 is not left are formed (FIG. 60).
(5) Boron ions are implanted from above the n silicon substrate 8 by ion implantation. Ions are not implanted into the n silicon substrate 8 where the resist film 22 remains (boron ions cannot penetrate the resist film 22), and boron ions are implanted only into the portion where the resist film 22 is not left. (FIG. 61).
(6) The resist film 22 is removed with a stripping solution (FIG. 62).
(7) Thereafter, diffusion is performed by heat treatment (1150 ° C.) to form the high concentration p region 9. The high concentration p region 9 formed in the breakdown voltage structure portion becomes a guard ring region. This heat treatment step is performed while flowing oxygen. Therefore, the thickness of the oxide film in the portion (breakdown voltage structure portion) where the first oxide film 16a is left on the n silicon substrate 8 in the step (2) is further increased by the lamination of the second oxide film 16b. The film thickness is about 1000 nm with the addition of the thickness of the second oxide film 16c to be a gate oxide film in a later process. On the other hand, a new second oxide film 16b is also formed at a portion where the first silicon oxide film 16a is not left (MOS type cell region) where the n silicon substrate 8 is exposed. The thickness of the third oxide film 16c to be a film is also added to about 350 nm (FIG. 63).
(8) By the photolithography step (2PE), a portion for leaving the newly formed second oxide film 16b on the surface of the n silicon substrate 8 in the MOS type cell region and a portion for leaving no second oxide film 16b are formed. In the breakdown voltage structure, the second oxide film 16b is opened to expose the high concentration p region 9 (FIG. 64).
(9) A thin third oxide film 16c is formed on the entire surface. The third oxide film 16c formed in the portion where the surface of the n silicon substrate 8 where the first oxide film 16a and the second oxide film 16b are not exposed becomes the first gate oxide film 11 in FIG. Membrane 16b andOxide film 16d andThe combination of the third oxide film 16c becomes the second gate oxide film 18 of FIG. 9, and the first gate oxide film 16a and the second oxide film 16b., Oxide film 16dA combination of the third oxide film 16c and the third oxide film 16c is a breakdown voltage structure oxide film 16. The film thickness of the first gate oxide film 11 which is the third oxide film 16c is about 80 nm (FIG. 65).
(10) As in FIG. 9, a polysilicon layer 12 to be a gate electrode is formed, and p well regions 9a, n+A source region 10, an interlayer insulating film 13, a metal film 14 serving as a metal electrode, and a field plate 15 exhibiting resistance are formed. This field plate is the same as a field plate of a normal MOS type semiconductor element, and is not limited to an a-Si film as long as it exhibits resistance.
[0037]
In the sixth embodiment, in addition to the effects of the fifth embodiment, the boron ion implantation site is covered with an oxide film, so that no outward diffusion occurs in the heat treatment step (7).
In the first to sixth embodiments, the portion where the first oxide film 16a or the second oxide film 16b is not left is formed in the breakdown voltage structure in the 1PE or 1.5PE photo process. Since the high concentration p region may be diffused in the structure portion to form a guard ring region, there is no problem even if the first oxide film 16a or the second oxide film 16b is left in the entire breakdown voltage structure portion. In the sixth embodiment, the resist film is left in the breakdown voltage structure portion in the 1.5 PE photo process. However, since the breakdown voltage structure portion includes the thick first oxide film 16a, the resist film in the breakdown voltage structure portion is used. There is no problem even if 22 is not necessarily left.
[0038]
【The invention's effect】
According to the present invention, the semiconductor substrate at the boundary between the second gate insulating film and the first gate insulating film is formed by increasing the thickness of the insulating film for the withstand voltage structure and decreasing the thickness of the second gate insulating film. By making the step on the surface extremely small and making this step small, the electric field strength at the boundary can be reduced and the breakdown voltage of the semiconductor device can be prevented from being lowered. Further, by increasing the film thickness of the insulating film for the withstand voltage structure, it is possible to prevent a decrease in withstand voltage in the peripheral portion of the semiconductor device. As a result, it is possible to improve the breakdown voltage non-defective rate of the semiconductor device.
[0039]
In addition, by covering the MOS-type cell region other than the p-well region formation region with an insulating film, the outwardly diffused impurities (boron ions) due to the heat treatment after the ion implantation are re-diffused to the region other than the p-well. By preventing the deterioration of the element characteristics can be prevented.
Furthermore, by forming a thin oxide film (screen oxide film) at the site where ions are implanted, outward diffusion due to subsequent heat treatment can be prevented, and deterioration of device characteristics can be prevented.
[0040]
In addition, by covering the oxide film serving as a mask during ion implantation with a resist film, impurities (boron ions) can be prevented from being introduced into the oxide film, and long-term reliability of the oxide film can be ensured. it can.
[Brief description of the drawings]
1A and 1B are cross-sectional views of main parts of a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a cross-sectional view of a MOS type cell region, and FIG.
FIGS. 2A and 2B are cross-sectional views of main steps showing the manufacturing steps of the semiconductor device according to the first embodiment of the present invention in the order of steps, where FIG. 2A is a cross-sectional view of a MOS type cell region, and FIG. Figure
3 is a cross-sectional view of a principal part showing the manufacturing process of the semiconductor device according to the present invention in order of steps, following FIG. 2, where (a) is a cross-sectional view of a MOS type cell region, and (b) is a cross-sectional view of a breakdown voltage structure portion; Figure
4 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the present invention in order of steps, following FIG. 3, where (a) is a cross-sectional view of a MOS type cell region, and (b) is a cross-sectional view of a breakdown voltage structure portion; Figure
5 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the present invention in order of steps, following FIG. 4. FIG. 5A is a cross-sectional view of the MOS type cell region, and FIG. Figure
6 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device of the present invention in order of steps, following FIG. 5, where (a) is a cross-sectional view of the MOS type cell region, and (b) is a cross-sectional view of the breakdown voltage structure portion; Figure
7 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the present invention in order of steps, following FIG. 6; (a) is a cross-sectional view of the MOS type cell region, and (b) is a cross-sectional view of the breakdown voltage structure portion. Figure
8 is a cross-sectional view of a principal part showing the manufacturing process of the semiconductor device according to the present invention in order of steps, following FIG. 7. FIG. 8A is a cross-sectional view of a MOS type cell region, and FIG. Figure
FIGS. 9A and 9B are cross-sectional views of principal parts showing the manufacturing process of the semiconductor device of the present invention in order of steps, following FIG. 8, where FIG. 9A is a cross-sectional view of a MOS type cell region, and FIG. Figure
FIG. 10 is a graph showing the failure rate of the collector-emitter breakdown voltage between the product of the present invention and the conventional product.
FIG. 11 is a graph showing the relationship between the collector-emitter breakdown voltage (avalanche voltage) and the breakdown voltage oxide film thickness.
12A is a plan view of a chip in a conventional semiconductor device, and FIG. 12B is an enlarged view of a portion A in FIG.
13 is a cross-sectional view of the main part of FIG. 12, where (a) is a cross-sectional view of the MOS cell region cut along the line AA in FIG. 12 (b), and (b) is a cross-sectional view of FIG. Sectional view of the pressure-resistant structure cut along line B
FIG. 14 is a cross-sectional view of main processes shown in the order of processes in a conventional semiconductor device manufacturing process;
FIG. 15 is a cross-sectional view of main parts, shown in order of steps, in the manufacturing process of the conventional semiconductor device continued from FIG. 14;
16 is a cross-sectional view of main parts, shown in order of steps, in the manufacturing process of the conventional semiconductor device, continued from FIG. 15;
17 is a cross-sectional view of main parts, shown in order of steps, in the manufacturing process of the conventional semiconductor device, continued from FIG. 16;
FIG. 18 is a cross-sectional view of main part steps shown in the order of steps in the manufacturing process of the conventional semiconductor device continued from FIG. 17;
FIG. 19 is a fragmentary process cross-sectional view illustrating the conventional semiconductor device manufacturing process following FIG. 18 in the order of processes.
FIG. 20 is a cross-sectional view of main part steps shown in the order of steps in the manufacturing process of the conventional semiconductor device continued from FIG. 19;
FIGS. 21A and 21B are diagrams showing a state of outward diffusion taking a MOS cell type region as an example, FIG. 21A is a view after ion implantation, FIG. 21B is a view showing a state of outward diffusion by heat treatment, (c) is a diagram showing a state in which the p region 9b is formed at a place outside a predetermined position by outward diffusion.
FIG. 22 is a completed view of a MOS type cell region when a p region 9b that is not supposed to be formed is formed.
FIGS. 23A and 23B are cross-sectional views of the principal part showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention in the order of steps, wherein FIG. 23A is a cross-sectional view of the MOS type cell region, and FIG. Cross section
24 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention in order of steps, following FIG. 23, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
25 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention in order of steps, following FIG. 24, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 26 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention in order of steps, following FIG. 25, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
27 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention in the order of steps, following FIG. 26, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
28 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention in the order of steps, following FIG. 27, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
29 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention in the order of steps, following FIG. 28, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
30 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention in order of steps, following FIG. 29, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
FIG. 31 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention in the order of steps, (a) is a cross-sectional view of the MOS type cell region, and (b) is the breakdown voltage structure portion. Cross section
FIG. 32 is a process cross-sectional view of the principal part illustrating the manufacturing process of the semiconductor device according to the third embodiment of the present invention in the order of steps, following FIG. 31; (a) is a cross-sectional view of the MOS type cell region, and (b) is a cross-sectional view. Cross section of pressure-resistant structure
33 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the third embodiment of the invention in order of processes, continued from FIG. 32, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
34 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention in order of steps, following FIG. 33, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
35 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the third embodiment of the invention in order of processes, continued from FIG. 34, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 36 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention in order of steps, following FIG. 35, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 37 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention in order of steps, following FIG. 36, (a) is a cross-sectional view of the MOS type cell region, (b) is Cross section of pressure-resistant structure
38 is a process cross-sectional view of the principal part illustrating the manufacturing process of the semiconductor device according to the third embodiment of the present invention in order of processes, continued from FIG. 37, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
FIG. 39 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention in the order of steps, (a) is a cross-sectional view of the MOS type cell region, and (b) is the breakdown voltage structure portion. Cross section
40 is a process cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention in order of processes, continued from FIG. 39, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
41 is a process cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention in order of processes, continued from FIG. 40, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
42 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention in order of processes, continued from FIG. 41, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
43 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention in order of steps, following FIG. 42, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
44 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention in order of steps, continued from FIG. 43, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
45 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention in order of processes, continued from FIG. 44, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
46 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention in the order of steps, following FIG. 45, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
47 is a process cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention in the order of steps, following FIG. 46, (a) is a cross-sectional view of the MOS type cell region, (b) is FIG. Cross section of pressure-resistant structure
48 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention in the order of steps, (a) is a cross-sectional view of the MOS type cell region, and (b) is the breakdown voltage structure part. Cross section
FIG. 49 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention in order of steps, following FIG. 48, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 50 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention in order of steps, following FIG. 49, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 51 is a cross-sectional view of the principal part showing the manufacturing step of the semiconductor device according to the fifth embodiment of the invention in order of steps, following FIG. 50, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 52 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention in order of steps, following FIG. 51, (a) is a cross-sectional view of the MOS type cell region, (b) is Cross section of pressure-resistant structure
53 is a process cross-sectional view of the principal part illustrating the manufacturing process of the semiconductor device according to the fifth embodiment of the invention in order of processes, continued from FIG. 52, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 54 is a process cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention in order of processes, continued from FIG. 53, (a) is a cross-sectional view of the MOS type cell region, and (b) is Cross section of pressure-resistant structure
FIG. 55 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention in order of processes, continued from FIG. 54, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 56 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention in order of processes, continued from FIG. 55, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 57 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention in the order of steps, (a) is a cross-sectional view of the MOS type cell region, and (b) is of the breakdown voltage structure part. Cross section
FIG. 58 is a process cross-sectional view of the principal part illustrating the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention in order of processes, continued from FIG. 57, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 59 is a process cross-sectional view of the principal part illustrating the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention in order of processes, continued from FIG. 58, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 60 is a process cross-sectional view of the principal part illustrating the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention in order of processes, following FIG. 59, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 61 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the sixth embodiment of the invention in order of processes, continued from FIG. 60, (a) is a cross-sectional view of the MOS type cell region, (b) is Cross section of pressure-resistant structure
FIG. 62 is a process cross-sectional view of the principal part illustrating the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention in order of processes, continued from FIG. 61, (a) is a cross-sectional view of the MOS type cell region, and (b) is FIG. Cross section of pressure-resistant structure
FIG. 63 is a process cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the sixth embodiment of the invention in order of processes, continued from FIG. 62, (a) is a cross-sectional view of the MOS type cell region, (b) is Cross section of pressure-resistant structure
FIG. 64 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the sixth embodiment of the invention in order of processes, continued from FIG. 63, (a) is a cross-sectional view of the MOS type cell region, and (b) is Cross section of pressure-resistant structure
FIG. 65 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device according to the sixth embodiment of the invention in order of processes, continued from FIG. 64, (a) is a cross-sectional view of the MOS type cell region, and (b) is Cross section of pressure-resistant structure
[Explanation of symbols]
8 n silicon substrate
9 High concentration p region
9a p-well region
9bp region
10 n+Source area
11 First gate oxide film
12 Polysilicon film
13 Interlayer insulation film
14 Metal film
15 Field plate
16 Oxide film for breakdown voltage structure
16a First oxide film
16b Second oxide film
16c Third oxide film
16d oxide film (screen oxide film)
18 Second gate oxide film
20 chip edge
21 Boron ion
22 resist film
a, b steps
W First gate oxide film thickness
D Thickness of oxide film for pressure-resistant structure
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000223798A JP4830184B2 (en) | 1999-08-04 | 2000-07-25 | Manufacturing method of semiconductor device |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22114199 | 1999-08-04 | ||
| JP11-221141 | 1999-08-04 | ||
| JP1999221141 | 1999-08-04 | ||
| JP2000223798A JP4830184B2 (en) | 1999-08-04 | 2000-07-25 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001111052A JP2001111052A (en) | 2001-04-20 |
| JP4830184B2 true JP4830184B2 (en) | 2011-12-07 |
Family
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| Application Number | Title | Priority Date | Filing Date |
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| JP2000223798A Expired - Fee Related JP4830184B2 (en) | 1999-08-04 | 2000-07-25 | Manufacturing method of semiconductor device |
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| JP (1) | JP4830184B2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP5162804B2 (en) * | 2001-09-12 | 2013-03-13 | 富士電機株式会社 | Semiconductor device |
| JP3935042B2 (en) * | 2002-04-26 | 2007-06-20 | 株式会社東芝 | Insulated gate semiconductor device |
| JP5128100B2 (en) * | 2006-09-29 | 2013-01-23 | 三菱電機株式会社 | Power semiconductor device |
| JP5626325B2 (en) * | 2012-12-18 | 2014-11-19 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| WO2015033406A1 (en) * | 2013-09-04 | 2015-03-12 | 株式会社日立製作所 | Semiconductor device, method for manufacturing same, power conversion apparatus, and rail vehicle |
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| JP3162745B2 (en) * | 1991-08-29 | 2001-05-08 | 三洋電機株式会社 | Method of manufacturing insulated gate field effect transistor |
| US5869371A (en) * | 1995-06-07 | 1999-02-09 | Stmicroelectronics, Inc. | Structure and process for reducing the on-resistance of mos-gated power devices |
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