JP3424635B2 - Semiconductor device and power conversion device using the same - Google Patents
Semiconductor device and power conversion device using the sameInfo
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- JP3424635B2 JP3424635B2 JP2000034311A JP2000034311A JP3424635B2 JP 3424635 B2 JP3424635 B2 JP 3424635B2 JP 2000034311 A JP2000034311 A JP 2000034311A JP 2000034311 A JP2000034311 A JP 2000034311A JP 3424635 B2 JP3424635 B2 JP 3424635B2
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置及びそれを
使った電力変換装置に係り、特に１.７ｋＶ以上の高い
阻止電圧を有するプレーナ型半導体装置及びそれを使っ
た高電圧の電力変換装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a power converter using the same, and more particularly to a planar semiconductor device having a high blocking voltage of 1.7 kV or more and a high voltage power converter using the same. Regarding
【０００２】[0002]
【従来の技術】最近、プレーナ型半導体装置の阻止電圧
の向上が著しい。プレーナ型半導体装置とは、少なくと
も１つのｐｎ接合が主表面に露出している半導体装置を
言うが、従来使われてきたメサ型半導体装置，ベベル型
の半導体装置に比べ、主表面からの不純物の拡散や絶縁
膜の形成のみで高電圧の阻止特性を得られることから、
ＩＣ，ＬＳＩの微細化プロセスと共用化できるというメ
リットがある。高電圧の半導体装置でも性能向上には微
細化が必須で、微細化プロセスを使ったプレーナ半導体
装置の開発が著しい。2. Description of the Related Art Recently, the blocking voltage of a planar semiconductor device has been remarkably improved. The planar type semiconductor device is a semiconductor device in which at least one pn junction is exposed on the main surface. Compared to the mesa type semiconductor device and the bevel type semiconductor device which have been conventionally used, the impurity from the main surface can be prevented. Since high voltage blocking characteristics can be obtained only by diffusion and formation of an insulating film,
There is an advantage that it can be shared with the miniaturization process of IC and LSI. Even in high-voltage semiconductor devices, miniaturization is essential for improving performance, and the development of planar semiconductor devices using miniaturization processes is remarkable.
【０００３】図３は、プレーナ型半導体装置の一例であ
るダイオードの平面図を示す。半導体装置１には、電流
を流す主電極２２と、この主電極２２をトラック状に取
り囲むフィールドプレート電極２２１，２２２，２２
３，２２４，２２５と、さらに半導体装置１の最外周部
であるｎ+ 層１４（但し本図では記号「ｎ+ 」は記載せ
ず）の電位に固定された電極２３が形成されている。FIG. 3 is a plan view of a diode which is an example of a planar type semiconductor device. The semiconductor device 1 includes a main electrode 22 through which a current flows, and field plate electrodes 221, 222, 22 surrounding the main electrode 22 in a track shape.
3, 224, 225, and the electrode 23 fixed to the potential of the n + layer 14 (however, the symbol “n + ” is not shown in this figure) which is the outermost peripheral portion of the semiconductor device 1 is formed.
【０００４】図４は、図３の半導体装置１のＡ−Ａ′の
断面を示す。半導体装置１は、例えば半導体基体１１上
にｎ- 層１２が形成され、上側の主表面よりｐ層１３，
131,１３２，１３３，１３４，１３５が拡散されてい
る。また最外周にはｎ+ 層１４が形成されている。下面
の主表面には主電極２１が半導体基体１１に低抵抗接触
している。ｐ層１３にはもう一方の主電極２２が形成さ
れ、その一部は、絶縁膜３０を介してｎ- 層１２上に延
びている。この部分をフィールドプレートと言い、ｐ層
１３とｎ- 層１２が逆バイアスされたときに生じる電界
を緩和する役目を持つ。特に、電界が強くなりやすいｐ
層１３の角の領域の電界緩和に有効である。その他のｐ
層１３１，１３２，１３３，１３４，１３５は、主電極
２１にプラス、もう一方の主電極２２にマイナスが印加
された場合、その印加電圧を分散する役目を持つ。主電
極２１の電位は半導体基体１１に伝わり、半導体基体１
１とｎ- 層１２はｎ+ ／ｎ- 接合であるため、ほぼ同電
位となり、さらにｎ+ 層１４も同様の電位となる。この
結果、ｐ層１３とｎ+ 層１４が逆バイアス状態になり、
各ｐ層１３１，１３２，１３３，１３４，１３５は中間
の電位を持つことになる。例えば、主電極２１に２００
０Ｖが印加され、もう一方の主電極２２が０Ｖの場合、
ｐ層１３１は３００Ｖ，ｐ層１３２は６００Ｖ，ｐ層１
３３は９００Ｖ，ｐ層１３４は１２００Ｖ，ｐ層１３５
は１５００Ｖ、ｎ+ 層１４は約２０００Ｖとなる。この
ように電位を分散することで、プレーナ型半導体装置１
の高電圧化が可能となる。FIG. 4 shows a cross section taken along the line AA 'of the semiconductor device 1 of FIG. In the semiconductor device 1, for example, an n − layer 12 is formed on a semiconductor substrate 11, and a p layer 13 is formed from an upper main surface.
131, 132, 133, 134, 135 are diffused. An n + layer 14 is formed on the outermost circumference. The main electrode 21 is in low resistance contact with the semiconductor substrate 11 on the main surface of the lower surface. The other main electrode 22 is formed on the p layer 13, and a part of the main electrode 22 extends on the n − layer 12 via the insulating film 30. This portion is called a field plate, and has a role of relaxing an electric field generated when the p layer 13 and the n − layer 12 are reversely biased. In particular, the electric field tends to be strong
It is effective in relaxing the electric field in the corner region of the layer 13. Other p
The layers 131, 132, 133, 134 and 135 have a role of dispersing the applied voltage when a plus voltage is applied to the main electrode 21 and a minus voltage is applied to the other main electrode 22. The potential of the main electrode 21 is transmitted to the semiconductor substrate 11, and the semiconductor substrate 1
Since 1 and the n − layer 12 are n + / n − junctions, they have substantially the same potential, and the n + layer 14 also has the same potential. As a result, the p layer 13 and the n + layer 14 are in the reverse bias state,
Each p-layer 131, 132, 133, 134, 135 will have an intermediate potential. For example, 200
When 0V is applied and the other main electrode 22 is 0V,
p layer 131 is 300 V, p layer 132 is 600 V, p layer 1
33 is 900V, p layer 134 is 1200V, p layer 135
Is 1500 V and the n + layer 14 is about 2000 V. By distributing the potential in this manner, the planar semiconductor device 1
It is possible to increase the voltage.
【０００５】さらに、各ｐ層１３１，１３２，１３３，
１３４，１３５には補助電極２２１，２２２，２２３，
２２４，２２５が各々形成され、フィールドプレートが
それぞれに設けられ、長さＲがｎ- 層１２上に延びてい
る。これらのフィールドプレートＲも各ｐ層の角に加わ
る電界を緩和する。また、ｎ+ 層１４には、別の補助電
極２３が形成され、半導体装置１の内側に延びるフィー
ルドプレートが設けられている。これもｎ+ 層１４の角
に加わる電界を緩和する役目を持つ。このように、ｐ層
１３１，１３２，１３３，１３４，１３５による電位分
散と、フィールドプレートによる電界緩和によりプレー
ナ型半導体装置の高電圧化が可能となってきている。Further, each p layer 131, 132, 133,
Auxiliary electrodes 221, 222, 223 and
224 and 225 are each formed, a field plate is provided for each, and a length R extends over the n @-layer 12. These field plates R also relax the electric field applied to the corners of each p layer. Further, another auxiliary electrode 23 is formed on the n + layer 14, and a field plate extending inside the semiconductor device 1 is provided. This also has a role of relaxing the electric field applied to the corner of the n + layer 14. As described above, the potential distribution by the p layers 131, 132, 133, 134, 135 and the electric field relaxation by the field plate enable the planar type semiconductor device to have a higher voltage.
【０００６】なお、ｐ層１３１，１３２，１３３，１３
４，１３５は、ＦＬＲ（Field Limiting Ring ）と呼ば
れている。また、半導体装置１の周辺に向かってｎ- 層
上に延びるフィールドプレートを順フィールドプレート
（順ＦＰ），内側方向に延びるフィールドプレートを逆
フィールドプレート（逆ＦＰ）と呼ぶことにする。さら
に、ＦＬＲやＦＰを持つ電圧阻止領域のことをターミネ
ーション領域という。The p layers 131, 132, 133, 13
4, 135 are called FLR (Field Limiting Ring). A field plate extending on the n − layer toward the periphery of the semiconductor device 1 is called a forward field plate (forward FP), and a field plate extending inward is called a reverse field plate (reverse FP). Further, the voltage blocking region having FLR and FP is called a termination region.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、このよ
うなＦＬＲやフィールドプレートを持つ高電圧のプレー
ナ型半導体装置を、使用環境が厳しい、例えば地下鉄や
近郊電車などの電車のインバータ装置に使った場合、屋
内で使われるインバータ装置に比べ湿度や温度の変化が
激しい。このため、阻止電圧の低下や漏れ電流の増加と
いう問題が生じる。特に、インバータ電車では、架線電
圧が１５００Ｖに達するため、中性点電圧を持つ３レベ
ルインバータ装置でも、半導体装置には１７００Ｖ以上
の阻止電圧が要求される。これをプレーナ構造で実現す
るにはＦＬＲが約８個以上必要であるため、ターミネー
ション領域の長さが１０００ミクロンにも及ぶ場合があ
る。そのため、モジュール等の有機樹脂でモールドされ
たパッケージでは、湿度や温度の変化により樹脂中の電
荷や水分等の変動の影響を受けやすい。その結果、イン
バータ装置の電圧制御能力が低下し、最悪の場合電車等
の運行に支障を来す場合がある。However, when such a high voltage planar type semiconductor device having an FLR or a field plate is used for an inverter device of a train, such as a subway or a suburban train, where the operating environment is severe, Humidity and temperature changes more drastically than inverters used indoors. Therefore, there arises a problem that the blocking voltage is lowered and the leakage current is increased. In particular, in an inverter train, the overhead line voltage reaches 1500 V, so that even a three-level inverter device having a neutral point voltage requires a blocking voltage of 1700 V or higher for a semiconductor device. In order to realize this with a planar structure, about 8 or more FLRs are required, so the length of the termination region may reach up to 1000 microns. Therefore, a package molded with an organic resin, such as a module, is easily affected by changes in electric charge, moisture, etc. in the resin due to changes in humidity and temperature. As a result, the voltage control capability of the inverter device is reduced, and in the worst case, operation of a train or the like may be hindered.
【０００８】図５は、その原因を説明する図４の部分拡
大図である。破線は、等電位線４０を示す。順フィール
ドプレートＲにより、等電位線４０が周辺方向に伸ばさ
れ、ｐ層１３４の角の領域のｎ- 層１２の電界が緩和さ
れていることが判る。本発明者等の実験結果、湿度の高
い状態では半導体装置１の絶縁膜３０上の表面にマイナ
スの電荷が発生し、ｎ- 層１２表面をｐ反転することが
判った。マイナスの電荷としては、水分中のＯＨ−イオ
ン，樹脂中のマイナスイオン等がある。FIG. 5 is a partially enlarged view of FIG. 4 for explaining the cause. The broken line indicates the equipotential line 40. It is understood that the equipotential line 40 is extended in the peripheral direction by the forward field plate R, and the electric field of the n − layer 12 in the corner region of the p layer 134 is relaxed. As a result of experiments conducted by the present inventors, it was found that negative charges are generated on the surface of the insulating film 30 of the semiconductor device 1 in a high humidity state, and the surface of the n − layer 12 is p-inverted. Negative charges include OH-ions in water and negative ions in resin.
【０００９】ｐ層１３４は、ｐ層１３５より低電位にあ
るため、ｐ層１３４と同電位の順フィールドプレートＲ
はｎ- 層１２より低電位となる。その結果、順ＦＰ下の
ｎ-層１２はｐ反転しやすく、さらに絶縁膜３０を介し
て露出しているｎ- 層１２表面もマイナス電荷によりｐ
反転するため、ｐ層１３４とｐ層１３５はｐ反転層で電
位的につながり、ＦＬＲの効果が損なわれ、阻止電圧が
低下する。Since the p layer 134 has a lower potential than the p layer 135, the forward field plate R having the same potential as the p layer 134 is formed.
Has a lower potential than the n − layer 12. As a result, the n − layer 12 under the forward FP is likely to undergo p inversion, and the surface of the n − layer 12 exposed through the insulating film 30 is also p due to the negative charge.
Because of the inversion, the p layer 134 and the p layer 135 are electrically connected in the p inversion layer, the effect of FLR is impaired, and the blocking voltage is lowered.
【００１０】これを防ぐために、図６に示すようなター
ミネーション構造が特開昭59−76466 号公報に記載され
ている。各ＦＬＲ１３１，１３２，１３３，１３４，１
３５に逆フィールドプレートＬを設けることにより、ｐ
反転層の形成が防止され、阻止電圧が安定化する。In order to prevent this, a termination structure as shown in FIG. 6 is disclosed in JP-A-59-76466. Each FLR 131, 132, 133, 134, 1
By providing the reverse field plate L on 35, p
The formation of the inversion layer is prevented and the blocking voltage is stabilized.
【００１１】これを、図７を使ってさらに詳しく説明す
る。逆フィールドプレートＬを形成することで、高電位
側にあるｐ層１３５の電位を補助電極２２５により、逆
フィールドプレートＬ下のｎ- 層１２表面の電位を緩
和，固定できる。逆フィールドプレートＬの電位は、そ
の下のｎ- 層１２表面の電位より高電位となるため、ｐ
反転層が形成されず、ｐ層１３４とｐ層１３５が同電位
とならないために阻止電圧が低下することなく、安定化
するという効果がある。しかし、インバータ電車が海岸
近くを走行する場合、塩水による影響を受け、特にナト
リウムイオンのプラス電荷により、逆フィールドプレー
トＬが長くなった様な状態となり、ｐ層１３４の角の電
界が強くなり、阻止電圧が低下する不具合がある。この
不具合は、ナトリウムイオンだけでなく、モジュールの
中に含まれる樹脂中のアルカリ金属イオンや、半導体装
置及びモジュールの製造途中で不可避に汚染されるアル
カリ金属イオンによっても生じる。This will be described in more detail with reference to FIG. By forming the reverse field plate L, the potential of the p layer 135 on the high potential side can be relaxed and fixed by the auxiliary electrode 225 on the surface of the n − layer 12 below the reverse field plate L. Since the potential of the reverse field plate L is higher than the potential of the surface of the n − layer 12 therebelow, p
Since the inversion layer is not formed and the p layer 134 and the p layer 135 do not have the same potential, there is an effect that the blocking voltage does not decrease and is stabilized. However, when the inverter train runs near the coast, it is affected by salt water, and due to the positive charge of sodium ions, the reverse field plate L becomes long and the electric field at the corner of the p layer 134 becomes strong. There is a problem that the blocking voltage drops. This defect is caused not only by sodium ions but also by alkali metal ions in the resin contained in the module and alkali metal ions which are inevitably contaminated during the manufacturing of the semiconductor device and the module.
【００１２】一方、図５と図７の構造をあわせ持つ図８
に示すような順フィールドプレートＲ４と逆フィールド
プレートＬ４を有する構造が考えられる。このような構
造とすることにより、阻止電圧の安定化が図られるが、
製造バラツキが多く、歩留まりが悪いという問題があ
る。本発明者等の原因究明の結果、半導体装置１０１の
絶縁膜３０上を覆う有機樹脂が阻止電圧試験でプラスと
マイナスに分極し、等電位線４０を乱していることが判
った。また、製造途中で不可避に導入される樹脂のボイ
ドや亀裂、また異物等により誘電率の異なる物質が絶縁
膜３０上に形成されると、等電位線４０が歪み、所望の
阻止電圧が安定して得られないことがＯＢＩＣ（光ビー
ム誘導電流）法等により観察された。このような不具合
は、インバータ電車の模擬試験でも生じ、駅間の半導体
装置の温度の上下，春夏秋冬の環境変化によるパッケー
ジの劣化により、樹脂等に亀裂，変質が起こり、絶縁膜
３０上の誘電率が変化し、阻止電圧が変動する。On the other hand, FIG. 8 having the structure of FIG. 5 and FIG. 7 together.
A structure having a forward field plate R4 and a reverse field plate L4 as shown in FIG. With such a structure, the blocking voltage can be stabilized,
There are many manufacturing variations, and the yield is low. As a result of investigating the cause by the present inventors, it was found that the organic resin covering the insulating film 30 of the semiconductor device 101 was polarized positively and negatively in the blocking voltage test and disturbed the equipotential line 40. Further, when a substance having a different dielectric constant is formed on the insulating film 30 due to voids or cracks of the resin, which are inevitably introduced during the manufacturing process, or a foreign substance, the equipotential line 40 is distorted and the desired blocking voltage is stabilized. It was observed by the OBIC (light beam induced current) method or the like that the above cannot be obtained. Such a problem also occurs in a simulated test of an inverter train, and cracks and deterioration of the resin or the like occur due to deterioration of the package due to changes in the temperature of the semiconductor device between the stations and environmental changes in the spring, summer, autumn, and winter, and on the insulating film 30. The permittivity changes and the blocking voltage changes.
【００１３】本発明は、上で述べたような問題点を考慮
してなされたものであり、阻止電圧が安定でしかも高歩
留まりのプレーナ型半導体装置及びそれを使った高信頼
の電力変換装置を実現する。The present invention has been made in consideration of the above-mentioned problems, and provides a planar semiconductor device having a stable blocking voltage and a high yield, and a highly reliable power conversion device using the same. To be realized.
【００１４】[0014]
【課題を解決するための手段】本発明の半導体装置は、
一対の主表面を持っている。これら主表面の一方の側に
おいては、第１導電型の第１の半導体領域の表面が接す
るとともに、第１の半導体領域内に延びる第２導電型の
第２の半導体領域が形成される。そして、この第２の半
導体領域を囲むように、第１の半導体領域内に延びる第
２導電型の第３の半導体領域が形成される。The semiconductor device of the present invention comprises:
It has a pair of major surfaces. On one side of these main surfaces, the surface of the first semiconductor region of the first conductivity type is in contact, and the second semiconductor region of the second conductivity type extending in the first semiconductor region is formed. Then, a third semiconductor region of the second conductivity type extending in the first semiconductor region is formed so as to surround the second semiconductor region.
【００１５】さらに、半導体装置の他方の主表面には第
１の主電極が形成され、第２の半導体領域にはこの領域
に低抵抗接触するとともに絶縁膜を介して第１の半導体
領域の表面を覆う第２の主電極が設けられる。そして、
第３の半導体領域には、この領域に低抵抗接触するとと
もに第２半導体領域の側及び第２半導体領域とは反対側
において絶縁膜を介して第１の半導体領域の表面上を覆
う補助電極を設ける。Further, a first main electrode is formed on the other main surface of the semiconductor device, and the second semiconductor region has a low resistance contact with this region and a surface of the first semiconductor region through an insulating film. A second main electrode is provided to cover the. And
The third semiconductor region is provided with an auxiliary electrode which is in low resistance contact with this region and covers the surface of the first semiconductor region through an insulating film on the side of the second semiconductor region and the side opposite to the second semiconductor region. Set up.
【００１６】このような構成のもとで、半導体装置の一
方の主表面と接する第１の半導体領域の表面において、
補助電極によって覆われる領域の面積が、一方の主表面
と接する第１の半導体領域の表面の面積の１／２以上に
なるようにする。With such a structure, on the surface of the first semiconductor region which is in contact with one main surface of the semiconductor device,
The area of the region covered by the auxiliary electrode is set to be ½ or more of the area of the surface of the first semiconductor region in contact with one main surface.
【００１７】[0017]
【作用】本発明において第１の半導体領域と第２の半導
体領域との接合が逆バイアスされる場合、半導体装置の
主表面上に広がる等電位線は、いったん第１の半導体領
域表面の電極で覆われない領域に集められ、再び第１の
半導体領域内において広がる。ここで、半導体装置の一
方の主表面と接する第１の半導体領域の表面の半分以上
の面積が、絶縁膜を介して補助電極によって、すなわち
順フィールドプレートと逆フィールドプレートによって
覆われているので、等電位線は第１の半導体領域表面の
電極で覆われない領域に高い密度で集められる。このた
め、半導体装置の主表面上の領域の誘電率が変化してこ
の領域における等電位線が歪んでも、等電位線が集めら
れた領域では等電位線の密度は実質一様になる。従っ
て、再び第１の半導体領域内において広がる等電位線に
は歪は生じない。すなわち、第１の半導体領域内の等電
位線は安定であり、電界の集中が起きにくく阻止電圧が
安定する。また、イオン性物質や水分の影響を受けにく
いため、インバータ電車などの使用環境が厳しく、経時
変化しやすい樹脂製のパッケージでも高信頼の電力変換
装置を実現できる。In the present invention, when the junction between the first semiconductor region and the second semiconductor region is reverse-biased, the equipotential lines spreading on the main surface of the semiconductor device are once generated by the electrodes on the surface of the first semiconductor region. Collected in the uncovered area and once again spread out in the first semiconductor area. Here, since the area of more than half of the surface of the first semiconductor region in contact with one main surface of the semiconductor device is covered by the auxiliary electrode, that is, the forward field plate and the reverse field plate through the insulating film, The equipotential lines are concentrated with high density in the region of the surface of the first semiconductor region which is not covered by the electrode. Therefore, even if the dielectric constant of the region on the main surface of the semiconductor device changes and the equipotential lines are distorted in this region, the density of the equipotential lines becomes substantially uniform in the region where the equipotential lines are collected. Therefore, the equipotential lines spreading again in the first semiconductor region are not distorted. That is, the equipotential lines in the first semiconductor region are stable, the concentration of the electric field hardly occurs, and the blocking voltage becomes stable. Further, since it is not easily affected by ionic substances and water, it is possible to realize a highly reliable power conversion device even in a resin package which is harsh in the use environment such as an inverter train and easily changes with time.
【００１８】[0018]
【実施例】以下、本発明を、実施例により詳細に説明す
る。EXAMPLES The present invention will be described in detail below with reference to examples.
【００１９】図１は、本発明を適用した高電圧半導体装
置の一実施例のターミネーション領域を示す断面図であ
る。半導体装置１においては、ｎ+ 型またはｐ+ 型の半
導体基体１１の上に、ｎ- 層１２が形成される。ここ
で、半導体基体１１の導電型は、絶縁ゲート型バイポー
ラトランジスタやＭＯＳ制御サイリスタ等のｐエミッタ
層を有する半導体装置の場合にはｐ+ 型となり、MOSFET
やダイオード等の場合はｎ+ となる。半導体基体１１は
一方の主表面に接し、ｎ- 層１２は他方の主表面に接す
る。ｎ- 層１２が接する主表面からｐ層１３が拡散によ
り形成されている。ｐ層１３を囲むようにＦＬＲのｐ層
１３１，１３２，１３３，１３４，１３５が形成され
る。さらに半導体装置１の最外周には、これらのＦＬＲ
を囲むようにチャンネルストッパとなるｎ+ 層１４が設
けられている。半導体基体１１が接する主表面には主電
極２１が、ｐ層１３には順フィールドプレートを持つも
う一方の主電極２２が、それぞれ低抵抗接触するように
形成されている。各ｐ層１３１，１３２，１３３，１３
４，１３５、およびｎ+ 層１４には、それぞれ補助電極
２２１，２２２，２２３，２２４，２２５、２３が、各
層に低抵抗接触するように設けられている。補助電極２
２１〜２２５は、絶縁膜３０を介してｎ- 層１２の表面
上を覆う順及び逆フィールドプレートを有している。ま
た、補助電極２３も同様に、逆フィールドプレートを有
している。FIG. 1 is a sectional view showing a termination region of an embodiment of a high voltage semiconductor device to which the present invention is applied. In the semiconductor device 1, the n − layer 12 is formed on the n + type or p + type semiconductor substrate 11. Here, the conductivity type of the semiconductor substrate 11 is p + type in the case of a semiconductor device having a p-emitter layer such as an insulated gate bipolar transistor or a MOS control thyristor.
In the case of a diode or the like, it becomes n + . Semiconductor substrate 11 is in contact with one main surface, and n − layer 12 is in contact with the other main surface. The p layer 13 is formed by diffusion from the main surface with which the n − layer 12 is in contact. FL layers p 131, 132, 133, 134, 135 are formed so as to surround the p layer 13. Further, these FLRs are provided on the outermost periphery of the semiconductor device 1.
An n + layer 14 serving as a channel stopper is provided so as to surround the. A main electrode 21 is formed on the main surface with which the semiconductor substrate 11 is in contact, and another main electrode 22 having a forward field plate is formed on the p layer 13 so as to make a low resistance contact. Each p layer 131, 132, 133, 13
Auxiliary electrodes 221, 222, 223, 224, 225, and 23 are provided on the 4, 135 and n + layers 14 so as to make low resistance contact with the layers. Auxiliary electrode 2
21 to 225 have forward and reverse field plates that cover the surface of the n − layer 12 via the insulating film 30. Similarly, the auxiliary electrode 23 also has a reverse field plate.
【００２０】本発明が、図４および図６が示す従来構造
と異なる点は、補助電極２２１，２２２，２２３，２２
４，２２５，２３が、ｎ- 層１２の主表面に接する面積
のほとんどを覆っている点である。この効果を図２に示
す、本実施例における電位分布の計算結果を使って説明
する。The present invention differs from the conventional structure shown in FIGS. 4 and 6 in that auxiliary electrodes 221, 222, 223, 22 are provided.
4, 225 and 23 cover most of the area in contact with the main surface of the n − layer 12. This effect will be described using the calculation result of the potential distribution in this embodiment shown in FIG.
【００２１】図２は図１の部分拡大図である。ｐ層１３
４に形成された補助電極２２４は絶縁膜３０を介して長
さＲ４の順フィールドプレートを有している。また、ｐ
層１３５には補助電極２２５が形成され、長さＬ４の逆
フィールドプレートが設けられている。なお、Ｒ４は、
ｐ層１３４とｎ- 層の接合部の露出位置から補助電極２
２４の順フィールドプレートの端部までの長さである。
Ｌ４についても同様である。FIG. 2 is a partially enlarged view of FIG. p layer 13
The auxiliary electrode 224 formed in No. 4 has a forward field plate of length R4 with the insulating film 30 interposed therebetween. Also, p
An auxiliary electrode 225 is formed on the layer 135, and an inverse field plate having a length L4 is provided. In addition, R4 is
From the exposed position of the junction of the p layer 134 and the n − layer, the auxiliary electrode 2
24 to the end of the forward field plate.
The same applies to L4.
【００２２】順フィールドプレートによりｐ層１３４の
角の電界が緩められている。また、逆フィールドプレー
トによりｐ層１３５近傍のｎ- 層１２表面がｐ反転しに
くい。さらに、順フィールドプレート，逆フィールドプ
レートにより補助電極２２４，２２５間の距離Ｓ４が極
めて狭くなっている。後述するように、Ｓ４の寸法は、
順逆フィールドプレート間に置いて主表面に接するｎ-
層の面積が、ｐ層134と１３５の間で主表面と接するｎ-
層の面積の１／２以下になるように設定する。このこ
とにより、ｎ- 層１２内の等電位線は領域Ｓ４で一端密
集し、補助電極２２４，２２５上でまた分散する。その
結果、樹脂の変質や、水分の影響により、補助電極上に
誘電率の異なる領域や、イオン性物質が形成され、補助
電極上の等電位線が乱れても、領域Ｓ４で等電位線が実
質一様な密度となり歪が矯正される。このため、ｎ- 層
１２内の等電位線には、外部の等電位線の乱れが影響し
ない。すなわち、ｎ- 層１２内の等電位線は安定化され
るので、ｎ- 層１２中の電界の変動が起きにくく阻止電
圧が安定する。The electric field at the corner of the p layer 134 is relaxed by the forward field plate. In addition, the surface of the n − layer 12 in the vicinity of the p layer 135 is less likely to undergo p inversion due to the reverse field plate. Further, the distance S4 between the auxiliary electrodes 224 and 225 is extremely narrow due to the forward field plate and the reverse field plate. As will be described later, the size of S4 is
N − which is placed between the forward and reverse field plates and contacts the main surface
The area of the layer is n − which is in contact with the main surface between the p layers 134 and 135.
The area is set to be 1/2 or less of the area of the layer. As a result, the equipotential lines in the n − layer 12 are once concentrated in the region S4 and are dispersed again on the auxiliary electrodes 224 and 225. As a result, even if a region having a different dielectric constant or an ionic substance is formed on the auxiliary electrode due to the deterioration of the resin or the influence of water, and the equipotential line on the auxiliary electrode is disturbed, the equipotential line is generated in the region S4. The density becomes substantially uniform and the distortion is corrected. Therefore, the disturbance of the external equipotential lines does not affect the equipotential lines in the n − layer 12. That is, since the equipotential lines in the n − layer 12 are stabilized, fluctuations in the electric field in the n − layer 12 are unlikely to occur and the blocking voltage is stable.
【００２３】本発明者らは、長さＲ４，Ｌ４，Ｓ４の好
ましい長さを検討した。その結果、ｎ- 層内におけるｐ
層１３４，１３５の付近の電界の２倍以上に、Ｓ４領域
の電界を強くすると、つまり主表面に露出するｎ- 層１
２の面積の半分以上を順フィールドプレートと逆フィー
ルドプレートで覆うと、高い歩留まりが得られることが
判った。図９はその結果を示す。（Ｌ＋Ｒ）／（Ｌ＋Ｒ
＋Ｓ）を０.５ 以上とすることにより、約９５％の歩留
まりが安定して得られる（Ｌ，Ｒ，Ｓはそれぞれ長さＬ
４，Ｒ４，Ｓ４に対応する）。本実施例においては、Ｓ
４領域における絶縁膜３０は、絶縁破壊強度が半導体領
域よりも大きい。例えばシリコン酸化膜は、その絶縁破
壊強度がシリコンの約２５倍である。このため、順フィ
ールドプレートと逆フィールドプレートによって等電位
線が密集し電界強度が増大しても、Ｓ４領域が絶縁破壊
することがなく、阻止電圧の劣化は起こさない。The present inventors have examined preferable lengths of R4, L4 and S4. As a result, p in the n-layer
When the electric field in the S4 region is made stronger than twice the electric field in the vicinity of the layers 134 and 135, that is, the n − layer 1 exposed on the main surface is exposed.
It was found that a high yield can be obtained by covering more than half of the area of 2 with the forward field plate and the reverse field plate. FIG. 9 shows the result. (L + R) / (L + R
By setting + S) to 0.5 or more, a yield of about 95% can be stably obtained (L, R, and S are length L respectively.
4, R4, S4). In this embodiment, S
The dielectric breakdown strength of the insulating film 30 in the four regions is larger than that in the semiconductor region. For example, a silicon oxide film has a dielectric breakdown strength about 25 times that of silicon. Therefore, even if the equipotential lines are densely packed by the forward field plate and the reverse field plate and the electric field strength increases, the S4 region does not undergo dielectric breakdown and the blocking voltage does not deteriorate.
【００２４】さらに、本実施例では図１に示すように、
高電圧の阻止電圧を実現するため、ｐ層１３１，１３
２，１３３，１３４，１３５はそれらの間隔（隣接する
ｐ層間の距離、すなわちｐ層間に露出するｎ- 層の幅）
がｎ+ 層１４側ほど、すなわち周辺側ほど広くしてい
る。これにより、内側ほどすなわち主電極２２が接触す
るｐ層 １３側ほど等電位線が密で電界が強くなってい
ても各ＦＬＲでほぼ均等に電圧を分散できる。さらに好
ましくは、内側ほど順フィールドプレートより逆フィー
ルドプレートを長くした方が高電圧を達成しやすい。こ
れは、逆フィールドプレートによりｐ反転層を形成する
ことなく、電位を周辺方向のＦＬＲへ伝え、電位を分散
しやすいためである。この逆フィールドプレートの長さ
は、ＦＬＲのｐ層の深さより長ければさらに良い。Further, in this embodiment, as shown in FIG.
In order to realize a high blocking voltage, the p layers 131, 13
2, 133, 134 and 135 are their intervals (distance between adjacent p layers, that is, the width of the n − layer exposed between p layers)
Is wider on the n + layer 14 side, that is, on the peripheral side. As a result, even when the equipotential lines are denser and the electric field is stronger toward the inside, that is, toward the p layer 13 side where the main electrode 22 contacts, the voltage can be substantially evenly distributed in each FLR. More preferably, it is easier to achieve a high voltage by making the reverse field plate longer than the forward field plate toward the inside. This is because it is easy to disperse the potential by transmitting the potential to the FLR in the peripheral direction without forming the p inversion layer by the reverse field plate. It is more preferable that the length of the reverse field plate is longer than the depth of the p layer of the FLR.
【００２５】図１に示すように、等電位線を順フィール
ドプレートと逆フィールドプレートで密集させる本発明
の構造は、ＦＬＲの最外周のｐ層１３５とチャンネルス
トッパｎ+ １４の間でも適用でき、同様の効果があるこ
とは言うまでもない。従来この領域は、電圧を阻止する
最終の領域であることからｎ- 層の露出面積を一般に大
きくしていた。ところが、本発明者等が調べた結果、製
造工程で不可避に導入される誘電率の異なる異物や有機
樹脂のボイド，亀裂により、阻止電圧が変動しやすいこ
とが判った。また阻止電圧の信頼性試験で、半導体装置
１００の絶縁膜３０上を覆う有機樹脂がプラスとマイナ
スに分極し、等電位線４０が歪み所望の阻止電圧が安定
して得られないという問題があった。本発明をｐ層１３
５とｎ+層１４の間にさらに適用することにより、製造
工程の歩留まりをさらに９５％以上に安定化することが
できる。As shown in FIG. 1, the structure of the present invention in which equipotential lines are densely packed in the forward field plate and the reverse field plate can be applied between the outermost p layer 135 of the FLR and the channel stopper n + 14, It goes without saying that there are similar effects. Conventionally, since this region is the final region for blocking the voltage, the exposed area of the n-layer is generally increased. However, as a result of investigations by the present inventors, it was found that the blocking voltage is likely to change due to foreign matter inevitably introduced in the manufacturing process, which has a different dielectric constant, and voids and cracks in the organic resin. Further, in the reliability test of the blocking voltage, the organic resin covering the insulating film 30 of the semiconductor device 100 is polarized positively and negatively, and the equipotential line 40 is distorted, so that a desired blocking voltage cannot be stably obtained. It was The present invention is applied to the p-layer 13
By further applying between 5 and the n + layer 14, the yield of the manufacturing process can be further stabilized to 95% or more.
【００２６】以上、本発明の１実施例について説明した
が、本実施例において各半導体領域の導電型を逆極性に
したものについても同じ作用，効果がある。Although one embodiment of the present invention has been described above, the same action and effect can be obtained even if the conductivity type of each semiconductor region in the present embodiment is reversed.
【００２７】また、半絶縁膜を補助電極上に形成し、半
絶縁膜を流れる電流によって電極間の電界を均一化する
ことにより、阻止電圧をさらに安定化できる。また、さ
らに、補助電極の上にさらに絶縁膜を形成すると、半導
体装置上の領域の誘電率の変化の影響が少なくするた
め、パッケージに組み込んだときに樹脂の分極や亀裂の
影響を受けにくくなる。Further, the blocking voltage can be further stabilized by forming the semi-insulating film on the auxiliary electrode and making the electric field between the electrodes uniform by the current flowing through the semi-insulating film. Further, if an insulating film is further formed on the auxiliary electrode, the influence of the change in the dielectric constant of the region on the semiconductor device is reduced, and thus the influence of the polarization and crack of the resin when incorporated into the package is reduced. .
【００２８】なお、本発明を適用したプレーナ構造を持
つ絶縁ゲート型バイポーラトランジスタ（以下ＩＧＢＴ
と略記する）とダイオードを内蔵した阻止電圧２ｋＶの
IGBTモジュールは、従来の圧接型の平形セラミックパッ
ケージに入ったベベル構造の高電圧素子と同等以上の信
頼性を確保できる。An insulated gate bipolar transistor (hereinafter referred to as an IGBT) having a planar structure to which the present invention is applied.
And a blocking voltage of 2 kV with a built-in diode.
The IGBT module can secure the reliability equal to or higher than that of the conventional high voltage device with the bevel structure in the pressure contact type flat ceramic package.
【００２９】次に、本発明を適用した半導体装置を使っ
た電力変換装置の実施例について説明する。Next, an embodiment of a power conversion device using a semiconductor device to which the present invention is applied will be described.
【００３０】図１０は、本発明を適用したＩＧＢＴ及び
ダイオードを使ったインバータ装置の一実施例の主回路
を示す。本実施例は、直列多重インバータ装置であり、
いわゆる中性点クランプ方式の３相インバータ装置であ
る。本インバータ装置では、一対の直流端子４４３及び
４４４、並びに相数に等しい３個の交流端子４５７〜４
５９を備え、直流端子に直流電源を接続し、IGBT470 〜
４８１をスイッチングすることにより、直流電力を交流
電力に変換して交流端子に出力する。直流端子間には、
直列に接続されたフィルタコンデンサ４６０と４６１が
接続される。FIG. 10 shows a main circuit of an embodiment of an inverter device using an IGBT and a diode to which the present invention is applied. This embodiment is a series multiple inverter device,
This is a so-called neutral point clamp type three-phase inverter device. In the present inverter device, a pair of DC terminals 443 and 444 and three AC terminals 457 to 4 having the same number of phases are used.
59 equipped with a DC power supply connected to the DC terminal, IGBT470 ~
By switching 481, DC power is converted into AC power and output to the AC terminal. Between the DC terminals,
Filter capacitors 460 and 461 connected in series are connected.
【００３１】ＩＧＢＴの組４７０と４７１，４７２と４
７３,４７４と４７５,４７６と477,４７８と４７９，４
８０と４８１がそれぞれ直列に接続され、それぞれの接
続点と、フィルタコンデンサ４６０と４６１の接続点と
の間にはクランプダイオード４９４〜４９９が接続され
る。２個のＩＧＢＴの組、例えば直列に接続されたIGBT
470と４７１の組及びIGBT476と４７７の組が、さらに直
列に接続され、その両端は直流端子間に接続される。ま
た、２組のＩＧＢＴの組の各接続点から交流端子が取り
出される。ここで、IGBT470 〜４８１及びダイオード４
８２〜４９３は、図１に示したターミネーション構造を
持っている。また、IGBT470 〜４８１及びダイオード４
８２〜４９３は複数個の樹脂性のパッケージ内に分けて
納められている。IGBT sets 470 and 471, 472 and 4
73,474 and 475,476 and 477,478 and 479,4
80 and 481 are connected in series, and clamp diodes 494 to 499 are connected between the respective connection points and the connection points of the filter capacitors 460 and 461. A set of two IGBTs, eg IGBTs connected in series
The set of 470 and 471 and the set of IGBT 476 and 477 are further connected in series, and both ends thereof are connected between the DC terminals. Further, an AC terminal is taken out from each connection point of the two IGBT sets. Here, the IGBTs 470 to 481 and the diode 4
82 to 493 have the termination structure shown in FIG. In addition, IGBTs 470 to 481 and diode 4
82-493 are stored separately in a plurality of resin packages.
【００３２】本実施例によれば、ＩＧＢＴおよびダイオ
ードがイオン性物質や水分の影響を受けにくいため、イ
ンバータ電車などの厳しい使用環境のもとでも経時変化
しやすい樹脂性のパッケージを使用しても、高信頼かつ
高電圧のインバータ制御装置が実現できる。According to this embodiment, since the IGBT and the diode are not easily affected by the ionic substance and the water, even if the resin package which is easily changed with time is used even in a severe operating environment such as an inverter train. A highly reliable and high voltage inverter controller can be realized.
【００３３】また本実施例のインバータ装置を搭載した
インバータ電車の模擬試験で、駅間の半導体装置の温度
上下や春夏秋冬の環境変化によるパッケージの劣化によ
り、樹脂等に亀裂や変質が起こり絶縁膜３０上の誘電率
が変化しても、半導体装置の阻止電圧の変動及び漏れ電
流の増加がないという高信頼性を確認することができ
た。Further, in a simulation test of an inverter train equipped with the inverter device of this embodiment, a resin is cracked or deteriorated due to the deterioration of the package due to the temperature rise and fall of the semiconductor device between stations and the environmental change in the spring, summer, autumn, winter, and insulation. Even if the dielectric constant on the film 30 was changed, it was possible to confirm high reliability that the blocking voltage of the semiconductor device did not change and the leakage current did not increase.
【００３４】図１１は、本発明を適用したＩＧＢＴ及び
ダイオードを使ったインバータ装置の他の実施例の主回
路を示す。本インバータ装置も前実施例と同様に、一対
の直流端子５４３及び５４４、並びに相数に等しい３個
の交流端子５５７〜５５９を備え、直流端子に直流電源
を接続し、IGBT545 〜５５０をスイッチングすることに
より、直流電力を交流電力に変換して交流端子に出力す
る。直流端子間には、直列接続されたＩＧＢＴの組５４
５と５４６，５４７と５４８，５４９と５５０の各両端
が接続される。各ＩＧＢＴの組における２個のＩＧＢＴ
の直列接続点からは交流端子が取りだされる。また、各
ＩＧＢＴには負荷電流を還流させるためにダイオードが
逆並列に接続される。本実施例においても、ＩＧＢＴ及
びダイオードは、図１に示したターミネーション構造を
持っている。また、ＩＧＢＴ及びダイオードは複数個の
樹脂性のパッケージ内に分けて納められている。例え
ば、一相分のＩＧＢＴ２個及びダイオード２個が１つの
パッケージに納められる。本実施例も、前実施例のイン
バータ装置と同様の作用，効果を持っている。FIG. 11 shows a main circuit of another embodiment of the inverter device using the IGBT and the diode to which the present invention is applied. This inverter device also includes a pair of DC terminals 543 and 544 and three AC terminals 557 to 559 having the same number of phases as in the previous embodiment. A DC power supply is connected to the DC terminals to switch the IGBTs 545 to 550. As a result, the DC power is converted into AC power and output to the AC terminal. A series of IGBTs 54 connected in series between the DC terminals.
Both ends of 5 and 546, 547 and 548, 549 and 550 are connected. Two IGBTs in each IGBT set
An AC terminal is taken out from the series connection point of. In addition, a diode is connected in antiparallel to each IGBT in order to return a load current. Also in this embodiment, the IGBT and the diode have the termination structure shown in FIG. The IGBT and the diode are separately housed in a plurality of resin packages. For example, two IGBTs for one phase and two diodes for one phase are accommodated in one package. This embodiment also has the same operation and effect as the inverter device of the previous embodiment.
【００３５】[0035]
【発明の効果】以上詳述したように、本発明によれば、
インバータ電車などの厳しい環境においても、阻止電圧
が安定な高電圧の半導体装置を実現できる。さらに、本
発明を適用した半導体装置を使用すれば、電力変換装置
の信頼性を向上できる。As described in detail above, according to the present invention,
Even in a severe environment such as an inverter train, a high-voltage semiconductor device with a stable blocking voltage can be realized. Furthermore, by using the semiconductor device to which the present invention is applied, the reliability of the power conversion device can be improved.
【図１】本発明を適用した高電圧半導体装置の一実施例
のターミネーション領域を示す断面図。FIG. 1 is a cross-sectional view showing a termination region of an embodiment of a high voltage semiconductor device to which the present invention is applied.
【図２】図１の部分拡大図。FIG. 2 is a partially enlarged view of FIG.
【図３】従来のプレーナ型半導体装置の一例であるダイ
オードの平面図。FIG. 3 is a plan view of a diode which is an example of a conventional planar semiconductor device.
【図４】図３の半導体装置のＡ−Ａ′の断面。4 is a cross section taken along the line AA ′ of the semiconductor device of FIG.
【図５】図４の部分拡大図。5 is a partially enlarged view of FIG.
【図６】従来のターミネーション構造。FIG. 6 shows a conventional termination structure.
【図７】図６の部分拡大図。7 is a partially enlarged view of FIG.
【図８】従来の順フィールドプレートと逆フィールドプ
レートを有する構造。FIG. 8 is a structure having a conventional forward field plate and a reverse field plate.
【図９】ターミネーション構造と歩留まりの関係。FIG. 9 shows the relationship between the termination structure and the yield.
【図１０】本発明を適用したＩＧＢＴ及びダイオードを
使ったインバータ装置の一実施例の主回路。FIG. 10 is a main circuit of an embodiment of an inverter device using an IGBT and a diode to which the present invention is applied.
【図１１】本発明を適用したＩＧＢＴ及びダイオードを
使ったインバータ装置の他の実施例の主回路。FIG. 11 is a main circuit of another embodiment of the inverter device using the IGBT and the diode to which the present invention is applied.
１…半導体装置、１１…半導体基体、１２…ｎ- 層、１
３…ｐ層、１４…ｎ+層、２１，２２…主電極、２３，
２２１，２２２，２２３，２２４，２２５…補助電極、
３０…絶縁膜、４０…等電位線、１３１，１３２，１３
３，１３４，１３５…ｐ層（ＦＬＲ）。DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Semiconductor substrate, 12 ... n - layer, 1
3 ... P layer, 14 ... N + layer, 21, 22 ... Main electrode, 23,
221, 222, 223, 224, 225 ... auxiliary electrodes,
30 ... Insulating film, 40 ... Equipotential line, 131, 132, 13
3,134,135 ... p layer (FLR).
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０２Ｍ 7/537 Ｈ０１Ｌ 29/74 Ｗ (56)参考文献 特開 平６−97469（ＪＰ，Ａ) 特開 昭63−227063（ＪＰ，Ａ) 特開 平２−11646（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/06 H01L 29/41 H01L 29/78 H01L 29/861 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 7 identification code FI H02M 7/537 H01L 29/74 W (56) References JP-A-6-97469 (JP, A) JP-A-63-127063 ( JP, A) JP-A-2-11646 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 29/06 H01L 29/41 H01L 29/78 H01L 29/861
Claims (11)
半導体領域と、 一方の主表面より第１の半導体領域内に延びる第２導電
型の第２の半導体領域と、 第２の半導体領域を囲むように形成され、一方の主表面
より第１の半導体領域内に延びる第２導電型の複数の第
３の半導体領域と、 他方の主表面に形成された第１の主電極と、 第２の半導体領域に低抵抗接触し、絶縁膜を介して第１
の半導体領域の表面を覆う第２の主電極と、 第３の半導体領域に低抵抗接触し、第２の半導体領域の
側及びその反対側において絶縁膜を介して第１の半導体
領域の表面上を覆う複数の補助電極と、を有し、 一方の主表面と接する第１の半導体領域の表面を覆う補
助電極の長さが、第３の半導体領域間の距離の１／２以
上であり、 第３の半導体領域間の距離が、周辺側ほど広くすること
を特徴とする半導体装置。1. A first conductivity type first semiconductor region having a pair of main surfaces, a surface in contact with one main surface side, and a second conductivity type extending from one main surface into the first semiconductor region. Second semiconductor region, a plurality of second conductivity type third semiconductor regions formed so as to surround the second semiconductor region and extending from one main surface into the first semiconductor region, and the other main semiconductor region. The first main electrode formed on the surface is in low resistance contact with the second semiconductor region, and the first main electrode is formed through the insulating film.
And a second main electrode covering the surface of the semiconductor region of the first semiconductor region and the third semiconductor region in low resistance contact, and on the surface of the first semiconductor region through the insulating film on the second semiconductor region side and the opposite side. A length of the auxiliary electrode covering a surface of the first semiconductor region in contact with one of the main surfaces is ½ or more of a distance between the third semiconductor regions, the distance between the third semiconductor region, and wherein a is wider peripheral side.
半導体領域と、 一方の主表面より第１の半導体領域内に延びる第２導電
型の第２の半導体領域と、 第２の半導体領域を囲むように形成され、一方の主表面
より第１の半導体領域内に延びる第２導電型の複数の第
３の半導体領域と、 第３の半導体領域をさらに囲むように形成され、一方の
主表面より第１の半導体領域内に延びる第１導電型の第
４の半導体領域と、 他方の主表面に形成された第１の主電極と、 第２の半導体領域に低抵抗接触し、絶縁膜を介して第１
の半導体領域の表面を覆う第２の主電極と、 第３の半導体領域に低抵抗接触し、第２及び第４の半導
体領域の側において絶縁膜を介して第１の半導体領域の
表面上を覆う複数の第１の補助電極と、 第４の半導体領域に低抵抗接触し、第３の半導体領域側
において絶縁膜を介して第１の半導体領域の表面上を覆
う第２の補助電極と、を有し、 一方の主表面と接する第１の半導体領域の表面を覆う第
３の半導体領域間における、隣接する第１の補助電極の
長さが、第３の半導体領域間の距離の１／２以上であ
り、 一方の主表面と接する第１の半導体領域の表面を覆う隣
接する第３の半導体領域と第４の半導体領域の間におけ
る、第１及び第２の補助電極を合わせた長さが、第３及
び第４半導体領域間の距離の１／２以上であり、 第３の半導体領域間の距離及び隣接する第３の半導体領
域と第４の半導体領域の距離が、第４の半導体領域側ほ
ど広く、内側ほど、第２の半導体領域側において第１の半導体領
域の表面上を覆う第１の補助電極の長さを、第４の半導
体領域側において第１の半導体領域の表面上を覆う第１
または第２の補助電極の長さより大きくする ことを特徴
とする半導体装置。2. A first conductivity type first semiconductor region having a pair of main surfaces, a surface in contact with one of the main surfaces, and a second conductivity type extending from the one main surface into the first semiconductor region. Second semiconductor region, a plurality of second conductivity type third semiconductor regions formed so as to surround the second semiconductor region and extending from the one main surface into the first semiconductor region, A fourth semiconductor region of a first conductivity type formed so as to further surround the semiconductor region and extending from one main surface into the first semiconductor region; and a first main electrode formed on the other main surface, It is in low resistance contact with the second semiconductor region, and the first semiconductor layer is formed through the insulating film.
A second main electrode that covers the surface of the semiconductor region and a low resistance contact with the third semiconductor region, and on the surface of the first semiconductor region through the insulating film on the second and fourth semiconductor region sides. A plurality of first auxiliary electrodes for covering, a second auxiliary electrode having a low resistance contact with the fourth semiconductor region, and covering the surface of the first semiconductor region through an insulating film on the side of the third semiconductor region, And covering the surface of the first semiconductor region in contact with one of the main surfaces .
Of adjacent first auxiliary electrodes between the three semiconductor regions.
The length is ½ or more of the distance between the third semiconductor regions, and is adjacent to the surface of the first semiconductor region in contact with one main surface.
Between the third semiconductor region and the fourth semiconductor region which are in contact with each other
The total length of the first and second auxiliary electrodes is ½ or more of the distance between the third and fourth semiconductor regions, the distance between the third semiconductor regions and the adjacent third semiconductor. The distance between the region and the fourth semiconductor region is wider toward the fourth semiconductor region side, and the inner side is closer to the first semiconductor region on the second semiconductor region side.
The length of the first auxiliary electrode covering the surface of the region is
A first semiconductor layer covering the surface of the first semiconductor region on the body region side;
Alternatively, the semiconductor device is characterized in that the length is larger than the length of the second auxiliary electrode .
体領域の表面上の内側の長さが、第３の半導体領域の第
１の半導体領域内に延びた深さより大きいことを特徴と
する半導体装置。3. The inner length of the auxiliary electrode on the surface of the first semiconductor region is larger than the depth of the auxiliary electrode extending into the first semiconductor region. Semiconductor device.
導体領域側の長さが、第３の半導体領域の第１の半導体
領域内に延びた深さより大きく、第１の補助電極の第１
の半導体領域の表面上の第４の半導体領域側の長さよ
り、第１の補助電極の第１の半導体領域の表面上の第２
の半導体領域側の長さが長い ことを特徴とする半導体装
置。 4. The method of claim 2, first the first second half on the surface of the semiconductor region of the auxiliary electrode
The length of the conductor region side is the first semiconductor of the third semiconductor region.
A first auxiliary electrode having a depth greater than a depth extending into the region;
On the surface of the semiconductor region of the fourth semiconductor region side
A second auxiliary layer on the surface of the first semiconductor region of the first auxiliary electrode.
The semiconductor device is characterized in that the length of the semiconductor region side is long .
補助電極、及び第２の補助電極を絶縁膜または半絶縁膜
で覆ったことを特徴とする半導体装置。5. A semiconductor device according to claim 2, wherein the second main electrode, the first auxiliary electrode, and the second auxiliary electrode are covered with an insulating film or a semi-insulating film.
半導体領域と、 一方の主表面より第１の半導体領域内に延びる第２導電
型の第２の半導体領域と、 第２の半導体領域を囲むように形成され、一方の主表面
より第１の半導体領域内に延びる第２導電型の複数の第
３の半導体領域と、 他方の主表面に形成された第１の主電極と、 第２の半導体領域に低抵抗接触し、絶縁膜を介して第１
の半導体領域の表面を覆う第２の主電極と、 第３の半導体領域に低抵抗接触し、第２の半導体領域の
側及びその反対側において絶縁膜を介して第１の半導体
領域の表面上を覆う複数の補助電極と、を有し、 一方の主表面と接する第１の半導体領域の表面を覆う補
助電極の長さが、第３の半導体領域間の距離の１／２以
上であり、 第３の半導体領域間の距離が、周辺側ほど広く、 補助電極の第１の半導体領域の表面上の内側の長さが、
第３の半導体領域の第１の半導体領域内に延びた深さよ
り大きいことを特徴とする半導体装置。6. A first conductivity type first semiconductor region having a pair of main surfaces, a surface in contact with one main surface side, and a second conductivity type extending from one main surface into the first semiconductor region. Second semiconductor region, a plurality of second conductivity type third semiconductor regions formed so as to surround the second semiconductor region and extending from one main surface into the first semiconductor region, and the other main semiconductor region. The first main electrode formed on the surface is in low resistance contact with the second semiconductor region, and the first main electrode is formed through the insulating film.
And a second main electrode covering the surface of the semiconductor region of the first semiconductor region and the third semiconductor region in low resistance contact, and on the surface of the first semiconductor region through the insulating film on the second semiconductor region side and the opposite side. A length of the auxiliary electrode covering a surface of the first semiconductor region in contact with one of the main surfaces is ½ or more of a distance between the third semiconductor regions, The distance between the third semiconductor regions is wider toward the peripheral side, and the inner length of the auxiliary electrode on the surface of the first semiconductor region is
A semiconductor device, wherein the depth of the third semiconductor region is greater than the depth of the third semiconductor region extending into the first semiconductor region.
半導体領域と、 一方の主表面より第１の半導体領域内に延びる第２導電
型の第２の半導体領域と、 第２の半導体領域を囲むように形成され、一方の主表面
より第１の半導体領域内に延びる第２導電型の複数の第
３の半導体領域と、 第３の半導体領域をさらに囲むように形成され、一方の
主表面より第１の半導体領域内に延びる第１導電型の第
４の半導体領域と、 他方の主表面に形成された第１の主電極と、 第２の半導体領域に低抵抗接触し、絶縁膜を介して第１
の半導体領域の表面を覆う第２の主電極と、 第３の半導体領域に低抵抗接触し、第２及び第４の半導
体領域の側において絶縁膜を介して第１の半導体領域の
表面上を覆う複数の第１の補助電極と、 第４の半導体領域に低抵抗接触し、第３の半導体領域側
において絶縁膜を介して第１の半導体領域の表面上を覆
う第２の補助電極と、を有し、 一方の主表面と接する第１の半導体領域の表面を覆う第
３の半導体領域間における、隣接する第１の補助電極の
長さが、第３の半導体領域間の距離の１／２以上であ
り、 一方の主表面と接する第１の半導体領域の表面を覆う隣
接する第３の半導体領域と第４の半導体領域の間におけ
る、第１及び第２の補助電極を合わせた長さが、第３及
び第４半導体領域間の距離の１／２以上であり、 第３の半導体領域間の距離及び隣接する第３の半導体領
域と第４の半導体領域の距離が、第４の半導体領域側ほ
ど広く、第１の補助電極の第１の半導体領域の表面上の第２の半
導体領域側の長さが、第３の半導体領域の第１の半導体
領域内に延びた深さより大きく、第１の補助電極の第１
の半導体領域の表面上の第４の半導体領域側の長さよ
り、第１の補助電極の第１の半導体領域の表面上の第２
の半導体領域側の長さが長い ことを特徴とする半導体装
置。7. A first conductivity type first semiconductor region having a pair of main surfaces, a surface in contact with one of the main surfaces, and a second conductivity type extending from the one main surface into the first semiconductor region. Second semiconductor region, a plurality of second conductivity type third semiconductor regions formed so as to surround the second semiconductor region and extending from the one main surface into the first semiconductor region, A fourth semiconductor region of a first conductivity type formed so as to further surround the semiconductor region and extending from one main surface into the first semiconductor region; and a first main electrode formed on the other main surface, It is in low resistance contact with the second semiconductor region, and the first semiconductor layer is formed through the insulating film.
A second main electrode that covers the surface of the semiconductor region and a low resistance contact with the third semiconductor region, and on the surface of the first semiconductor region through the insulating film on the second and fourth semiconductor region sides. A plurality of first auxiliary electrodes for covering, a second auxiliary electrode having a low resistance contact with the fourth semiconductor region, and covering the surface of the first semiconductor region through an insulating film on the side of the third semiconductor region, And covering the surface of the first semiconductor region in contact with one of the main surfaces .
Of adjacent first auxiliary electrodes between the three semiconductor regions.
The length is ½ or more of the distance between the third semiconductor regions, and is adjacent to the surface of the first semiconductor region in contact with one main surface.
Between the third semiconductor region and the fourth semiconductor region which are in contact with each other
The total length of the first and second auxiliary electrodes is ½ or more of the distance between the third and fourth semiconductor regions, the distance between the third semiconductor regions and the adjacent third semiconductor. The distance between the region and the fourth semiconductor region is wider on the side of the fourth semiconductor region , and the second half on the surface of the first semiconductor region of the first auxiliary electrode is
The length of the conductor region side is the first semiconductor of the third semiconductor region.
A first auxiliary electrode having a depth greater than a depth extending into the region;
On the surface of the semiconductor region of the fourth semiconductor region side
A second auxiliary layer on the surface of the first semiconductor region of the first auxiliary electrode.
The semiconductor device is characterized in that the length of the semiconductor region side is long .
ング素子と、を備える電力変換装置において、 半導体スイッチング素子が、 一対の主表面と、 一方の主表面側に接する表面を持つ第１導電型の第１の
半導体領域と、 一方の主表面より第１の半導体領域内に延びる第２導電
型の第２の半導体領域と、 第２の半導体領域を囲むように形成され、一方の主表面
より第１の半導体領域内に延びる第２導電型の複数の第
３の半導体領域と、 他方の主表面に形成された第１の主電極と、 第２の半導体領域に低抵抗接触し、絶縁膜を介して第１
の半導体領域の表面を覆う第２の主電極と、 第３の半導体領域に低抵抗接触し、第２の半導体領域の
側及びその反対側において絶縁膜を介して第１の半導体
領域の表面上を覆う複数の補助電極と、を有し、 一方の主表面と接する第１の半導体領域の表面を覆う補
助電極の長さが、第３の半導体領域間の距離の１／２以
上であり、 第３の半導体領域間の距離が、周辺側ほど広くすること
を特徴とする電力変換装置。8. A power conversion device comprising a pair of DC terminals, AC terminals of the same number as the number of phases, and a semiconductor switching element connected between the DC terminal and the AC terminal. A first conductive type first semiconductor region having a pair of main surfaces, a surface in contact with one main surface side, and a second conductive type second semiconductor extending from the one main surface into the first semiconductor region. A plurality of third conductive semiconductor regions of the second conductivity type, which are formed so as to surround the region and the second semiconductor region and extend from the one main surface into the first semiconductor region, and the other main surface. The first main electrode is in low resistance contact with the second semiconductor region, and the first main electrode and the second semiconductor region are in contact with each other through the insulating film.
And a second main electrode covering the surface of the semiconductor region of the first semiconductor region and the third semiconductor region in low resistance contact, and on the surface of the first semiconductor region through the insulating film on the second semiconductor region side and the opposite side. A length of the auxiliary electrode covering a surface of the first semiconductor region in contact with one of the main surfaces is ½ or more of a distance between the third semiconductor regions, A power converter characterized in that the distance between the third semiconductor regions is made wider toward the peripheral side.
ング素子と、を備える電力変換装置において、 半導体スイッチング素子が、 一対の主表面と、 一方の主表面側に接する表面を持つ第１導電型の第１の
半導体領域と、 一方の主表面より第１の半導体領域内に延びる第２導電
型の第２の半導体領域と、 第２の半導体領域を囲むように形成され、一方の主表面
より第１の半導体領域内に延びる第２導電型の複数の第
３の半導体領域と、 第３の半導体領域をさらに囲むように形成され、一方の
主表面より第１の半導体領域内に延びる第１導電型の第
４の半導体領域と、 他方の主表面に形成された第１の主電極と、 第２の半導体領域に低抵抗接触し、絶縁膜を介して第１
の半導体領域の表面を覆う第２の主電極と、 第３の半導体領域に低抵抗接触し、第２及び第４の半導
体領域の側において絶縁膜を介して第１の半導体領域の
表面上を覆う複数の第１の補助電極と、 第４の半導体領域に低抵抗接触し、第３の半導体領域側
において絶縁膜を介して第１の半導体領域の表面上を覆
う第２の補助電極と、を有し、 一方の主表面と接する第１の半導体領域の表面を覆う第
３の半導体領域間における、隣接する第１の補助電極の
長さが、第３の半導体領域間の距離の１／２以上であ
り、 一方の主表面と接する第１の半導体領域の表面を覆う隣
接する第３の半導体領域と第４の半導体領域の間におけ
る、第１及び第２の補助電極を合わせた長さが、第３及
び第４半導体領域間の距離の１／２以上であり、 第３の半導体領域間の距離及び隣接する第３の半導体領
域と第４の半導体領域の距離が、第４の半導体領域側ほ
ど広く、内側ほど、第２の半導体領域側において第１の半導体領
域の表面上を覆う第１の補助電極の長さを、第４の半導
体領域側において第１の半導体領域の表面上を覆う第１
または第２の補助電極の長さより大きくする ことを特徴
とする電力変換装置。9. A power conversion device comprising a pair of DC terminals, AC terminals of the same number as the number of phases, and a semiconductor switching element connected between the DC terminal and the AC terminal. A first conductive type first semiconductor region having a pair of main surfaces, a surface in contact with one main surface side, and a second conductive type second semiconductor extending from the one main surface into the first semiconductor region. A plurality of second conductive type third semiconductor regions formed so as to surround the region and the second semiconductor region and extending from the one main surface into the first semiconductor region, and further surrounding the third semiconductor region. A fourth semiconductor region of a first conductivity type formed in such a manner as to extend from one main surface into the first semiconductor region, a first main electrode formed on the other main surface, and a second semiconductor region. Low resistance contact to the first through the insulating film
A second main electrode that covers the surface of the semiconductor region and a low resistance contact with the third semiconductor region, and on the surface of the first semiconductor region through the insulating film on the second and fourth semiconductor region sides. A plurality of first auxiliary electrodes for covering, a second auxiliary electrode having a low resistance contact with the fourth semiconductor region, and covering the surface of the first semiconductor region through an insulating film on the side of the third semiconductor region, And covering the surface of the first semiconductor region in contact with one of the main surfaces .
Of adjacent first auxiliary electrodes between the three semiconductor regions.
The length is ½ or more of the distance between the third semiconductor regions, and is adjacent to the surface of the first semiconductor region in contact with one main surface.
Between the third semiconductor region and the fourth semiconductor region which are in contact with each other
The total length of the first and second auxiliary electrodes is ½ or more of the distance between the third and fourth semiconductor regions, the distance between the third semiconductor regions and the adjacent third semiconductor. The distance between the region and the fourth semiconductor region is wider toward the fourth semiconductor region side, and the inner side is closer to the first semiconductor region on the second semiconductor region side.
The length of the first auxiliary electrode covering the surface of the region is
A first semiconductor layer covering the surface of the first semiconductor region on the body region side;
Alternatively, the power conversion device is characterized in that it is longer than the length of the second auxiliary electrode .
ング素子と、を備える電力変換装置において、 半導体スイッチング素子が、 一対の主表面と、 一方の主表面側に接する表面を持つ第１導電型の第１の
半導体領域と、 一方の主表面より第１の半導体領域内に延びる第２導電
型の第２の半導体領域と、 第２の半導体領域を囲むように形成され、一方の主表面
より第１の半導体領域内に延びる第２導電型の複数の第
３の半導体領域と、 他方の主表面に形成された第１の主電極と、 第２の半導体領域に低抵抗接触し、絶縁膜を介して第１
の半導体領域の表面を覆う第２の主電極と、 第３の半導体領域に低抵抗接触し、第２の半導体領域の
側及びその反対側において絶縁膜を介して第１の半導体
領域の表面上を覆う複数の補助電極と、を有し、 一方の主表面と接する第１の半導体領域の表面を覆う補
助電極の長さが、第３の半導体領域間の距離の１／２以
上であり、 第３の半導体領域間の距離が、周辺側ほど広く、 補助電極の第１の半導体領域の表面上の内側の長さが、
第３の半導体領域の第１の半導体領域内に延びた深さよ
り大きいことを特徴とする電力変換装置。10. A power conversion device comprising a pair of DC terminals, AC terminals of the same number as the number of phases, and a semiconductor switching element connected between the DC terminal and the AC terminal, wherein the semiconductor switching element comprises: A first conductive type first semiconductor region having a pair of main surfaces, a surface in contact with one main surface side, and a second conductive type second semiconductor extending from the one main surface into the first semiconductor region. A plurality of third conductive semiconductor regions of the second conductivity type, which are formed so as to surround the region and the second semiconductor region and extend from the one main surface into the first semiconductor region, and the other main surface. The first main electrode is in low resistance contact with the second semiconductor region, and the first main electrode and the second semiconductor region are in contact with each other through the insulating film.
And a second main electrode covering the surface of the semiconductor region of the first semiconductor region and the third semiconductor region in low resistance contact, and on the surface of the first semiconductor region through the insulating film on the second semiconductor region side and the opposite side. A length of the auxiliary electrode covering a surface of the first semiconductor region in contact with one of the main surfaces is ½ or more of a distance between the third semiconductor regions, The distance between the third semiconductor regions is wider toward the peripheral side, and the inner length of the auxiliary electrode on the surface of the first semiconductor region is
A power conversion device, wherein the depth of the third semiconductor region is greater than the depth of the third semiconductor region extending into the first semiconductor region.
ング素子と、を備える電力変換装置において、 半導体スイッチング素子が、 一対の主表面と、 一方の主表面側に接する表面を持つ第１導電型の第１の
半導体領域と、 一方の主表面より第１の半導体領域内に延びる第２導電
型の第２の半導体領域と、 第２の半導体領域を囲むように形成され、一方の主表面
より第１の半導体領域内に延びる第２導電型の複数の第
３の半導体領域と、 第３の半導体領域をさらに囲むように形成され、一方の
主表面より第１の半導体領域内に延びる第１導電型の第
４の半導体領域と、 他方の主表面に形成された第１の主電極と、 第２の半導体領域に低抵抗接触し、絶縁膜を介して第１
の半導体領域の表面を覆う第２の主電極と、 第３の半導体領域に低抵抗接触し、第２及び第４の半導
体領域の側において絶縁膜を介して第１の半導体領域の
表面上を覆う複数の第１の補助電極と、 第４の半導体領域に低抵抗接触し、第３の半導体領域側
において絶縁膜を介して第１の半導体領域の表面上を覆
う第２の補助電極と、を有し、 一方の主表面と接する第１の半導体領域の表面を覆う第
３の半導体領域間における、隣接する第１の補助電極の
長さが、第３の半導体領域間の距離の１／２以上であ
り、 一方の主表面と接する第１の半導体領域の表面を覆う隣
接する第３の半導体領域と第４の半導体領域の間におけ
る、第１及び第２の補助電極を合わせた長さが、第３及
び第４半導体領域間の距離の１／２以上であり、 第３の半導体領域間の距離及び隣接する第３の半導体領
域と第４の半導体領域の距離が、第４の半導体領域側ほ
ど広く、第１の補助電極の第１の半導体領域の表面上の第２の半
導体領域側の長さが、第３の半導体領域の第１の半導体
領域内に延びた深さより大きく、第１の補助電極の第１
の半導体領域の表面上の第４の半導体領域側の長さよ
り、第１の補助電極の第１の半導体領域の表面上の第２
の半導体領域側の長さが長い ことを特徴とする電力変換
装置。11. A power conversion device comprising a pair of DC terminals, AC terminals of the same number as the number of phases, and a semiconductor switching element connected between the DC terminal and the AC terminal. A first conductive type first semiconductor region having a pair of main surfaces, a surface in contact with one main surface side, and a second conductive type second semiconductor extending from the one main surface into the first semiconductor region. A plurality of second conductive type third semiconductor regions formed so as to surround the region and the second semiconductor region and extending from the one main surface into the first semiconductor region, and further surrounding the third semiconductor region. A fourth semiconductor region of a first conductivity type formed in such a manner as to extend from one main surface into the first semiconductor region, a first main electrode formed on the other main surface, and a second semiconductor region. Low resistance contact to the first through the insulating film
A second main electrode that covers the surface of the semiconductor region and a low resistance contact with the third semiconductor region, and on the surface of the first semiconductor region through the insulating film on the second and fourth semiconductor region sides. A plurality of first auxiliary electrodes for covering, a second auxiliary electrode having a low resistance contact with the fourth semiconductor region, and covering the surface of the first semiconductor region through an insulating film on the side of the third semiconductor region, And covering the surface of the first semiconductor region in contact with one of the main surfaces .
Of adjacent first auxiliary electrodes between the three semiconductor regions.
The length is ½ or more of the distance between the third semiconductor regions, and is adjacent to the surface of the first semiconductor region in contact with one main surface.
Between the third semiconductor region and the fourth semiconductor region which are in contact with each other
The total length of the first and second auxiliary electrodes is ½ or more of the distance between the third and fourth semiconductor regions, the distance between the third semiconductor regions and the adjacent third semiconductor. The distance between the region and the fourth semiconductor region is wider on the side of the fourth semiconductor region , and the second half on the surface of the first semiconductor region of the first auxiliary electrode is
The length of the conductor region side is the first semiconductor of the third semiconductor region.
A first auxiliary electrode having a depth greater than a depth extending into the region;
On the surface of the semiconductor region of the fourth semiconductor region side
A second auxiliary layer on the surface of the first semiconductor region of the first auxiliary electrode.
The power converter is characterized in that the length of the semiconductor region side is long .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000034311A JP3424635B2 (en) | 1994-09-20 | 2000-02-07 | Semiconductor device and power conversion device using the same |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06224747A JP3111827B2 (en) | 1994-09-20 | 1994-09-20 | Semiconductor device and power conversion device using the same |
| JP2000034311A JP3424635B2 (en) | 1994-09-20 | 2000-02-07 | Semiconductor device and power conversion device using the same |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06224747A Division JP3111827B2 (en) | 1994-09-20 | 1994-09-20 | Semiconductor device and power conversion device using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000208768A JP2000208768A (en) | 2000-07-28 |
| JP3424635B2 true JP3424635B2 (en) | 2003-07-07 |
Family
ID=27624562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000034311A Expired - Lifetime JP3424635B2 (en) | 1994-09-20 | 2000-02-07 | Semiconductor device and power conversion device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3424635B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3812353B2 (en) * | 2001-03-19 | 2006-08-23 | 株式会社日立製作所 | Semiconductor power converter |
| JP5162804B2 (en) * | 2001-09-12 | 2013-03-13 | 富士電機株式会社 | Semiconductor device |
| JP3701227B2 (en) | 2001-10-30 | 2005-09-28 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| DE102004017723B4 (en) | 2003-04-10 | 2011-12-08 | Fuji Electric Co., Ltd | Backward blocking semiconductor device and method of making the same |
| JP5052091B2 (en) * | 2006-10-20 | 2012-10-17 | 三菱電機株式会社 | Semiconductor device |
| CN102473721B (en) * | 2009-07-31 | 2015-05-06 | 富士电机株式会社 | Semiconductor apparatus |
| DE102010024257B4 (en) * | 2010-06-18 | 2020-04-30 | Semikron Elektronik Gmbh & Co. Kg | Power semiconductor component with two-stage doping profile |
| CN103222057A (en) * | 2011-11-17 | 2013-07-24 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| JP6897166B2 (en) * | 2017-03-03 | 2021-06-30 | 株式会社豊田中央研究所 | Semiconductor device |
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2000
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| JP2000208768A (en) | 2000-07-28 |
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