JP5145593B2 - 重ねられた要素から成る微細構造の集合的な製作方法 - Google Patents
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- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/0023—Packaging together an electronic processing unit die and a micromechanical structure die
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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Description
を含む。
:― 第二の板の下面は第一の板の上面と、それぞれの表面の主要部分にわたって接着さるが、第一の板の絶縁保護層におけるエッチングの窪みにより形成された「切り取りルート」と呼ばれる区域は接着せず、そして
― これらの板は、下部の板要素及び上部の板要素を含む二つの重ねられた要素から成る個々の構造に切り取られ、切り取り作業は、少なくとも切り取りルート内を通る第一の切断線に沿って、その上面側を経由した第二の板の要素の切り取り、及び同じ切り取りルート内を通るが、第一の切断線とは重ならない第二の切断線に沿って、下側を経由した第二の板の要素の下方に位置する第一の板の要素の切り取りを含み、二つの切断線の間にある下方の板要素の一部分が、第一の要素に接着された上部の板要素によって覆われないようにする。
― 二列のチップ間の切り取りルートを通る、第一の板の切断線に平行な(しかし重なっていない)一本の細い切断線に沿った切り取り、
― 又は二列のチップ間の切り取りルートを通る、第一のチップの切断線に平行な、しかし少なくともその内の一本は後者と重なっていない二本の平行な細い切断線に沿った切り取りである;この二番目の場合、第二の板の二本の切断線の間にある部分は、取り除かれて二つの重ねられた要素から成る最終構造の部分を形成しない無駄な部分である。
― あるいは、第一の板の細い切断線の幅よりも大きい切断線の幅を有する、第二の板の切り取りである。この場合、本発明によれば、この切断線は第一の板の切断線に対して横方向に偏位した少なくとも一つの縁を有すると考えられ、第一の板の切断線と重ならない第二の板の切断線を構成するのは、この縁である。ここで再び、切り取り後に、第一の板要素はそれに接着される第二の板要素によって覆われない部分を含む。この覆われない部分は少なくとも一つの外部接続端子を含む。
Claims (11)
- 第一要素および第二要素を含む重ね合わされた要素から成る構造物の集合的な製作のための方法であって、
前記第一要素は第一の板(10)に属しかつ電子回路素子と接触端子とを含み、前記電子回路素子は前記第一の板の上面上に形成される粗さの小さい平らな絶縁保護層によって保護され、前記平らな絶縁保護層は「切り取りルート」(ZDn)と呼ばれる窪み区域を有し、前記接触端子は前記窪み区域の中の前記第一の板に取り付けられ、
前記第二要素は粗さの小さい平らな下面を有する第二の板(40)に属し、
接着材料を用いずに分子付着によって前記第二の板(40)の平らな下面と前記第一の板(10)の上面とを互いに接着することで、前記下面と前記正面との間で付着が生じるが、前記窪み区域では付着が生じないようにし、
互いに接着された前記第一の板と前記第二の板から、重ね合わされた第一および第二要素から成る構造物を切り取り、前記切り取りは、
切り取りルートに沿って通る第一の切断線(LHn)に沿って、前記第二の板の上面側から前記第二の板の要素を切り取り、かつ、
第一の切断線(LHn)とは重ならない前記切り取りルートに沿って通る第二の切断線(LDn)に沿って、前記第一の板の下面側から前記第一の板の要素を切り取ることを含む方法により、
第一および第二の切断線の間にある前記第一の板の要素の一部分が、前記第二の板の要素によって覆われないようにする方法。 - 切り取り作業が、同じ切り取りルート(ZDn)を通るが、第一及び第二の切断線と重ならい第三の切断線(LH2n-1)に沿って上側を経由した第二の板の切り取りをさらに含み、第一と第三の切断線の間にある部分が、板の切り取りから生じる、二要素の重なる構造の部分を形成しないスクラップ(Rn)を構成することを特徴とする請求項1に記載の方法。
- 第二の板の切り取りが第一の板の第二の切断線の幅よりも大きい切断線の幅で行なわれ、より広い切断線の一つの縁が、第一の板の第二の切断線と重ならない第二の板の第一の切断線を構成することを特徴とする請求項1に記載の方法。
- 第二の板要素が下部の板要素を保護するための要素であることを特徴とする請求項1〜3のいずれか一項に記載の方法。
- 第二の板が透明板であることを特徴とする請求項1〜4のいずれか一項に記載の方法。
- 第二の板がガラスの板であることを特徴とする請求項5に記載の方法。
- 第二の板が溶融シリカの板であることを特徴とする請求項6に記載の方法。
- 第二の板が個々の光学素子の配列を含み、各光学素子が第一の板に形成されたそれぞれの集積回路チップに対応することを特徴とする請求項1〜7のいずれか一項に記載の方法。
- 第一の板要素がイメージセンサ又は画像ディスプレイであり、第二の板要素がこのセンサと組み合わされた光学構造であることを特徴とする請求項8に記載の方法。
- 二つの重ねられた要素から成る構造が放射線のイメージセンサであり、第二の板要素が、ファイバー・ウェーハ及び/又は、X線をイメージセンサにより検出できる光画像に変換するシンチレータ構造を含むことを特徴とする請求項9に記載の方法。
- 二つの重ねられた要素から成る構造が、電子的機能と機械的及び/又は 光学的機能を組み合わせるMEMS又はMOEMSタイプの微細加工構造であることを特徴とする請求項1〜10のいずれか一項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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FR0413345A FR2879183B1 (fr) | 2004-12-15 | 2004-12-15 | Procede de fabrication collective de microstructures a elements superposes |
FR0413345 | 2004-12-15 | ||
PCT/EP2005/056599 WO2006063961A1 (fr) | 2004-12-15 | 2005-12-08 | Procede de fabrication collective de microstructures a elements superposes |
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JP2008523999A JP2008523999A (ja) | 2008-07-10 |
JP5145593B2 true JP5145593B2 (ja) | 2013-02-20 |
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US (1) | US7737000B2 (ja) |
EP (1) | EP1825510B1 (ja) |
JP (1) | JP5145593B2 (ja) |
KR (1) | KR101197502B1 (ja) |
CN (1) | CN100541766C (ja) |
CA (1) | CA2587431C (ja) |
DE (1) | DE602005015483D1 (ja) |
FR (1) | FR2879183B1 (ja) |
WO (1) | WO2006063961A1 (ja) |
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KR101003568B1 (ko) * | 2007-11-14 | 2010-12-22 | 산요 세미컨덕터 컴퍼니 리미티드 | 반도체 모듈 및 촬상 장치 |
JP5164532B2 (ja) * | 2007-11-14 | 2013-03-21 | オンセミコンダクター・トレーディング・リミテッド | 半導体モジュールおよび撮像装置 |
JP2011224931A (ja) * | 2010-04-22 | 2011-11-10 | Disco Corp | 光デバイスウエーハの加工方法およびレーザー加工装置 |
KR101217697B1 (ko) * | 2010-08-16 | 2013-01-02 | 주식회사 이오테크닉스 | 웨이퍼 가공방법 |
FR2992465B1 (fr) * | 2012-06-22 | 2015-03-20 | Soitec Silicon On Insulator | Procede de fabrication collective de leds et structure pour la fabrication collective de leds |
US9481566B2 (en) | 2012-07-31 | 2016-11-01 | Soitec | Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices |
US9105485B2 (en) * | 2013-03-08 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding structures and methods of forming the same |
US9449876B2 (en) * | 2014-01-17 | 2016-09-20 | Infineon Technologies Ag | Singulation of semiconductor dies with contact metallization by electrical discharge machining |
US9466638B2 (en) * | 2014-10-07 | 2016-10-11 | Terapede Systems Inc. | Seemless tiling and high pixel density in a 3D high resolution x-ray sensor with integrated scintillator grid for low noise and high image quality |
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US10643860B2 (en) | 2018-03-26 | 2020-05-05 | Infineon Technologies Ag | Methods of thinning and structuring semiconductor wafers by electrical discharge machining |
US10967450B2 (en) | 2018-05-04 | 2021-04-06 | Infineon Technologies Ag | Slicing SiC material by wire electrical discharge machining |
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JP2000182915A (ja) * | 1998-12-16 | 2000-06-30 | Ricoh Co Ltd | 半導体装置およびその製造方法 |
DE19962231A1 (de) * | 1999-12-22 | 2001-07-12 | Infineon Technologies Ag | Verfahren zur Herstellung mikromechanischer Strukturen |
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- 2005-12-08 WO PCT/EP2005/056599 patent/WO2006063961A1/fr active Application Filing
- 2005-12-08 US US11/721,928 patent/US7737000B2/en active Active
- 2005-12-08 CA CA2587431A patent/CA2587431C/fr not_active Expired - Fee Related
- 2005-12-08 JP JP2007546026A patent/JP5145593B2/ja active Active
- 2005-12-08 KR KR1020077013453A patent/KR101197502B1/ko active IP Right Grant
- 2005-12-08 DE DE602005015483T patent/DE602005015483D1/de active Active
- 2005-12-08 CN CNB2005800465934A patent/CN100541766C/zh active Active
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Also Published As
Publication number | Publication date |
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FR2879183A1 (fr) | 2006-06-16 |
US7737000B2 (en) | 2010-06-15 |
EP1825510A1 (fr) | 2007-08-29 |
DE602005015483D1 (de) | 2009-08-27 |
CN100541766C (zh) | 2009-09-16 |
FR2879183B1 (fr) | 2007-04-27 |
JP2008523999A (ja) | 2008-07-10 |
CA2587431A1 (fr) | 2006-06-22 |
US20090275152A1 (en) | 2009-11-05 |
EP1825510B1 (fr) | 2009-07-15 |
KR101197502B1 (ko) | 2012-11-09 |
CA2587431C (fr) | 2014-06-10 |
KR20070110831A (ko) | 2007-11-20 |
WO2006063961A1 (fr) | 2006-06-22 |
CN101124673A (zh) | 2008-02-13 |
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