JP5070228B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5070228B2 JP5070228B2 JP2009010499A JP2009010499A JP5070228B2 JP 5070228 B2 JP5070228 B2 JP 5070228B2 JP 2009010499 A JP2009010499 A JP 2009010499A JP 2009010499 A JP2009010499 A JP 2009010499A JP 5070228 B2 JP5070228 B2 JP 5070228B2
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- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004891 communication Methods 0.000 claims description 90
- 230000001360 synchronised effect Effects 0.000 claims description 31
- 230000005540 biological transmission Effects 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 21
- 239000010703 silicon Substances 0.000 description 21
- 238000000034 method Methods 0.000 description 17
- 238000012545 processing Methods 0.000 description 17
- 230000000630 rising effect Effects 0.000 description 11
- 239000013078 crystal Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 101100421503 Arabidopsis thaliana SIGA gene Proteins 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 101100191136 Arabidopsis thaliana PCMP-A2 gene Proteins 0.000 description 3
- 101000691574 Homo sapiens Junction plakoglobin Proteins 0.000 description 3
- 102100026153 Junction plakoglobin Human genes 0.000 description 3
- 101100048260 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBX2 gene Proteins 0.000 description 3
- VJTAZCKMHINUKO-UHFFFAOYSA-M chloro(2-methoxyethyl)mercury Chemical compound [Cl-].COCC[Hg+] VJTAZCKMHINUKO-UHFFFAOYSA-M 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 102100036462 Delta-like protein 1 Human genes 0.000 description 1
- 101000928537 Homo sapiens Delta-like protein 1 Proteins 0.000 description 1
- 101150089655 Ins2 gene Proteins 0.000 description 1
- 101100072652 Xenopus laevis ins-b gene Proteins 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
- H03K5/15033—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of bistable devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Description
Claims (6)
- 第1クロック信号が供給される複数の第1フリップフロップと、前記複数の第1フリップフロップの間に接続される第1論理回路とを有する第1LSIと、
前記第1LSIとは異なるチップに形成され、第2クロック信号が供給される複数の第2フリップフロップと、前記複数の第2フリップフロップの間に接続される第2論理回路とを有する第2LSIとを具備し、
前記第1LSIと前記第2LSIは、一つの半導体パッケージ内に積層され、
前記第1LSIは、前記第1クロック信号に基づいて前記第2LSIにデータを送信し、
前記第2LSIは、前記第2クロック信号に基づいて前記第1LSIから送信されたデータを受信し、
前記第2クロック信号は、前記第1クロック信号と同期するように制御され、
前記第1LSIの前記第1クロック信号は、前記第2LSIを貫通して設けられ、前記第1、及び第2LSIを互いに電気的に接続するための第1貫通電極により、前記第2LSIに送信され、
前記第2LSIは、第1DLL回路を有し、前記第1DLL回路は、前記第1貫通電極を介して供給された前記第1クロック信号に基づいて前記第2クロック信号の位相を制御するものであり、
前記第1LSIは、前記第1LSIから前記第2LSIに対して送信する前記第1クロック信号を制御するクロックコントローラ回路を具備し、
前記クロックコントローラ回路は、前記第1LSIと前記第2LSIが通信を行うときのみ、前記第1クロック信号を送信することを特徴とする半導体装置。 - 請求項1において、
前記第2LSIの上方に配置され第3クロック信号が供給される複数の第3フリップフロップと、前記第3フリップフロップの間に接続される論理回路とを有する第3LSIを更に具備し、
前記第1貫通電極は、更に前記第3LSIを貫通し、前記第1、第2LSI及び第3LSIを互いに電気的に接続し、前記第1LSIの前記第1クロック信号は、前記第1貫通電極により、前記第2LSI及び第3LSIに送信され、
前記第3クロック信号は、前記第1クロック信号に同期するように制御されることを特徴とする半導体装置。 - 請求項1において、
前記第2LSIの上方に配置され、第3クロック信号が供給される複数の第3フリップフロップと、前記第3フリップフロップの間に接続される論理回路とを有する第3LSIと、
前記第2LSI及び第3LSIを貫通して設けられ、第2LSI及び第3LSIを互いに電気的に接続するための第2貫通電極とを更に具備し、
前記第2LSIの前記第2クロック信号は、前記第2貫通電極により、前記第3LSIに送信され、
前記第3クロック信号は、前記第2クロック信号に同期するように制御されることを特徴とする半導体装置。 - 請求項3記載において、
前記第1LSIから前記第3LSIへのデータ送信は、前記複数の第2フリップフロップの一部を介して行われることを特徴とする半導体装置。 - 請求項1において、
前記第1LSIは、前記第1クロック信号を送信する第1無線通信回路をさらに有し、
前記第2LSIは、前記第1クロック信号を受信する第2無線通信回路をさらに有することを特徴とする半導体装置。 - 請求項5において、
前記第2LSIは、前記第2クロック信号を送信する第3無線通信回路を更に有し、
前記第1無線通信回路は、前記第1クロック信号に対応した第1磁場を生成することで前記第1クロック信号を送信し、
前記第2無線通信回路は、前記第2クロック信号に対応した第2磁場を生成することで前記第2クロック信号を送信し、
前記第2無線通信回路は、前記第1磁場及び前記第2磁場の両方を受けて、誘導起電力信号を生成することで、前記第1クロック信号及び前記第2クロック信号の位相差を比較することを特徴とする半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009010499A JP5070228B2 (ja) | 2009-01-21 | 2009-01-21 | 半導体装置 |
US12/690,659 US7994822B2 (en) | 2009-01-21 | 2010-01-20 | Semiconductor device for synchronous communication between stacked LSI |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009010499A JP5070228B2 (ja) | 2009-01-21 | 2009-01-21 | 半導体装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010171092A JP2010171092A (ja) | 2010-08-05 |
JP2010171092A5 JP2010171092A5 (ja) | 2011-10-20 |
JP5070228B2 true JP5070228B2 (ja) | 2012-11-07 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009010499A Expired - Fee Related JP5070228B2 (ja) | 2009-01-21 | 2009-01-21 | 半導体装置 |
Country Status (2)
Country | Link |
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US (1) | US7994822B2 (ja) |
JP (1) | JP5070228B2 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8179173B2 (en) * | 2010-03-12 | 2012-05-15 | Raytheon Company | Digitally calibrated high speed clock distribution |
US8384435B2 (en) * | 2011-01-05 | 2013-02-26 | Texas Instruments Incorporated | Clock switching circuit with priority multiplexer |
JP5643665B2 (ja) * | 2011-01-24 | 2014-12-17 | 学校法人慶應義塾 | 積層型半導体集積回路装置 |
JP5643673B2 (ja) * | 2011-02-16 | 2014-12-17 | 学校法人慶應義塾 | 電子回路 |
US8786080B2 (en) * | 2011-03-11 | 2014-07-22 | Altera Corporation | Systems including an I/O stack and methods for fabricating such systems |
JP5807550B2 (ja) | 2012-01-10 | 2015-11-10 | 株式会社ソシオネクスト | 半導体装置 |
JP6312377B2 (ja) * | 2013-07-12 | 2018-04-18 | キヤノン株式会社 | 半導体装置 |
US9231603B2 (en) | 2014-03-31 | 2016-01-05 | International Business Machines Corporation | Distributed phase detection for clock synchronization in multi-layer 3D stacks |
KR20150141018A (ko) * | 2014-06-09 | 2015-12-17 | 에스케이하이닉스 주식회사 | 관통 비아를 통해 연결되는 적층 반도체 장치 및 모니터링 방법 |
US10147658B2 (en) | 2014-06-09 | 2018-12-04 | SK Hynix Inc. | Stacked semiconductor apparatus being electrically connected through through-via and monitoring method |
US9319829B1 (en) * | 2014-10-30 | 2016-04-19 | Hua Wen Hsu | Wireless inductive pointer clock |
JP2017163204A (ja) * | 2016-03-07 | 2017-09-14 | APRESIA Systems株式会社 | 通信装置 |
KR102605617B1 (ko) | 2016-11-10 | 2023-11-23 | 삼성전자주식회사 | 적층 반도체 패키지 |
Family Cites Families (10)
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JP4063392B2 (ja) * | 1998-03-26 | 2008-03-19 | 富士通株式会社 | 信号伝送システム |
JP3475857B2 (ja) * | 1999-06-03 | 2003-12-10 | 日本電気株式会社 | ソースシンクロナス転送方式 |
JP2001251283A (ja) * | 2000-03-06 | 2001-09-14 | Hitachi Ltd | インターフェース回路 |
US6331800B1 (en) * | 2000-07-21 | 2001-12-18 | Hewlett-Packard Company | Post-silicon methods for adjusting the rise/fall times of clock edges |
JP4752369B2 (ja) * | 2004-08-24 | 2011-08-17 | ソニー株式会社 | 半導体装置および基板 |
JP5063958B2 (ja) | 2006-08-18 | 2012-10-31 | 川崎マイクロエレクトロニクス株式会社 | 半導体集積回路および半導体集積回路の設計方法 |
JP5149554B2 (ja) * | 2007-07-17 | 2013-02-20 | 株式会社日立製作所 | 半導体装置 |
JP2009032857A (ja) * | 2007-07-26 | 2009-02-12 | Hitachi Ltd | 半導体集積回路および半導体装置 |
US8781053B2 (en) * | 2007-12-14 | 2014-07-15 | Conversant Intellectual Property Management Incorporated | Clock reproducing and timing method in a system having a plurality of devices |
JP5258343B2 (ja) * | 2008-03-27 | 2013-08-07 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体集積回路 |
-
2009
- 2009-01-21 JP JP2009010499A patent/JP5070228B2/ja not_active Expired - Fee Related
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2010
- 2010-01-20 US US12/690,659 patent/US7994822B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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US20100182046A1 (en) | 2010-07-22 |
US7994822B2 (en) | 2011-08-09 |
JP2010171092A (ja) | 2010-08-05 |
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