JP5019320B2 - 薄膜デバイスの形成方法、mosトランジスタの形成方法及び電子デバイス - Google Patents
薄膜デバイスの形成方法、mosトランジスタの形成方法及び電子デバイス Download PDFInfo
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- JP5019320B2 JP5019320B2 JP2007211891A JP2007211891A JP5019320B2 JP 5019320 B2 JP5019320 B2 JP 5019320B2 JP 2007211891 A JP2007211891 A JP 2007211891A JP 2007211891 A JP2007211891 A JP 2007211891A JP 5019320 B2 JP5019320 B2 JP 5019320B2
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- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
- ZMCWFMOZBTXGKI-UHFFFAOYSA-N tritert-butyl borate Chemical compound CC(C)(C)OB(OC(C)(C)C)OC(C)(C)C ZMCWFMOZBTXGKI-UHFFFAOYSA-N 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
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Description
[0015]図1〜図7を参照すると、典型的なプロセスの流れが示されている。図1は、その上に積層体及び/又は誘電体層20,25を有する基板10を示している。基板10は、一般に、電気的に不活性又は活性であってもよく且つ1つ以上の有利な及び/又は望ましい電気的特性及び/又は光学的特性を更に含みうる従来の機械的な支持構造を備えている。電気的に不活性な或いは非能動的な適した基板は、ガラス、セラミック、誘電体及び/又はプラスチックから成るプレート、ディスク、及び/又は、シートを備えていてもよい。或いは、導電性の適した基板は、半導体(例えばシリコン)及び/又は金属から成るウエハ、ディスク、シート、及び/又は、箔を備えていてもよい。基板が金属シート及び/又は箔を備えている場合、デバイスはインダクタ及び/又はキャパシタを更に備えていてもよく、また、方法は、金属基板からインダクタ及び/又はキャパシタを形成することを更に含んでいてもよい。しかしながら、任意のそのような導電性基板は、絶縁体上の構造体及び/又はデバイスから金属基板中に形成された構造体へと電気的接触が成されるべき場所を除き、当該導電性基板とその上に位置する電気的に活性な任意の層又は構造体との間に絶縁層(例えば、層20)を有していなければならない(例えば、EAS又はRFIDタグのためのインターポーザ、インダクタ、及び/又は、キャパシタから成る1つ以上の金属パッド;例えば、2004年7月6日、2005年4月11日、2005年10月3日にそれぞれ出願された米国特許出願第10/885,283号、第11/104,375号及び第11/243,460号[代理人整理番号 IDR0121号、IDR0312号、IDR0272号]参照)。基板は、シリコンウエハ、ガラスプレート、セラミックプレート又はディスク、プラスチックシート又はディスク、金属箔、金属シート又はディスク、及び、これらの積み重ねられた或いは層状の組み合わせから成るグループから選択される部材を備えていることが好ましく、それらの部材のうちの導電性部材は、一般に、その上にバリア層(例えばTiN)及び/又は絶縁層(例えば、対応する酸化物から成る層)を有している。特定の実施形態において、絶縁層は、約1μmの厚さを有するスピンオンガラスバリア層を備えていてもよい。同様に、ガラス基板及びプラスチック基板は、その上に位置され且つ基板の表面粗さを減少させるための平坦化層、その上に位置され且つ密着性を向上させ及び/又はその上に印刷又は堆積されるその後の材料(例えばインク)の拡散を制御する材料から成る表面エネルギ改質層(2007年3月20日に出願された米国仮出願第60/919,290号[代理人整理番号 IDR1091号]参照)、及び/又は、その上に位置されるバリア層を更に含んでいてもよい。
・無機オキソリン化合物及び酸(例えば、P2O3,P2O5,POCl3など);
・リンケイ酸塩;
・単量体、二量体及び/又はオリゴマーリン酸塩(例えば、メタポリリン酸塩及び/又はポリリン酸塩);
・ホスホン酸塩、ホスフィン酸塩及びホスフィン;
・有機オキソリン化合物及び酸(例えば、アルキル(アリール)リン酸塩、ホスホン酸塩、ホスフィン酸塩及びそれらの縮合生成物);
・アルキル−及び/又はアリールホスホン酸及び/又はホスフィン酸
・無機ホウ素化合物及び酸(例えば、ホウ酸、B2O3);
・ホウケイ酸塩、ボラゾール及びそのポリマー;
・ホウ素ハロゲン化物(例えば、BBr3);
・ボラン(例えば、B10H10)及びシラ−及び/又はアザボラン;
・有機ホウ素化合物及び酸(例えば、アルキル/アリールホウ酸、ホウ酸塩、ボロキシン、ボラゾール、ボラン付加錯体など)
・上記化合物のオキソ−及び/又はアザ類似物、例えばAs2O3やSb2O3;
・シクロ−As5(SiH3)5などのアルシノシラン
従来技術 本発明
1.N+マスキング インクジェットN+,P+ドーパント
2.N+注入 −−
3.アッシュ/ストリッピング −−
4.P+マスキング −−
5.P+注入 −−
6.アッシュ/ストリッピング −−
7.活性化 炉活性化
8.ILD堆積 −−
・低濃度にドープされた或いはドープされないシランを堆積させて、アモルファスSi薄膜アイランドを形成する。
・(随意)アモルファスSiの脱水素化を行う。
・低濃度にドープされた或いはドープされないアモルファスSiを結晶化する(例えば、エキシマレーザ処理又は炉内処理により)
・ゲート酸化物を堆積させ、成長させ、形成する。
・ゲート金属を堆積させる。
・(随意)ゲート酸化物の露出領域をエッチングする。
・ドープガラスを堆積させることによりソース・ドレイン領域を印刷し或いはパターニングする。
・ドーパントを活性化させ及び/又はソース・ドレイン領域中へ拡散させる(例えば、熱処理により)。
・コンタクトホールを開ける。
・金属間接続部を印刷する。
・従来のアニーリング。
・水素化(随意)
・検査(随意)
[0072]本発明は、信頼できる商業的に許容できる電気的特性(例えば、ON/OFF速度及び比率、キャリア移動度Vtなど)を有するドープ誘電体膜を使用するMOS又は薄膜集積回路の製造におけるソース/ドレイン(S/D)層への印刷アプローチのための低コストな方法を有利に提供する。印刷された及び/又は放射線形成された半導体構造(及び、随意的には、印刷された及び/又は放射線形成された導体構造)は、より従来的なアプローチで形成される構造に類似する結果を、従来のプロセス技術よりもかなり低コストで且つかなり高い生産性(数週間〜数ヶ月ではなく、数時間〜数日程度で)で与えることができるとともに、作業装置を製造するために使用される処理工具の数を減らすことができる。
Claims (18)
- 薄膜デバイスを形成する方法であって、
a)電気的に導電性の基板又は電気的に絶縁性の基板における実質的に水平で完全に露出した面上に複数の半導体アイランドを形成するステップと、
b)前記半導体アイランドの第1のサブセット上に或いはそれよりも上側に第1の誘電体層を印刷するとともに、前記半導体アイランドの第2のサブセット上に或いはそれよりも上側に第2の誘電体層を印刷するステップであって、前記第1及び第2の誘電体層が互いに横に隣接し、前記第1の誘電体層が第1のドーパントを含み、前記第2の誘電体層が前記第1のドーパントとは異なる第2のドーパントを含む、当該ステップと、
c)前記第1のドーパントを半導体アイランドの前記第1のサブセット中へ拡散させ且つ前記第2のドーパントを半導体アイランドの前記第2のサブセット中へ拡散させるように十分に前記第1及び第2の誘電体層、前記半導体アイランド及び前記基板をアニールするステップと、
を備える方法。 - 前記複数の半導体アイランドを形成する前記ステップが、半導体インクを印刷するステップを備える、請求項1に記載の方法。
- 前記半導体インクが、前記インクの1〜50重量%の量のシランと、前記シランが溶解できる溶媒とを含む、請求項2に記載の方法。
- 前記半導体インクが前記半導体アイランドの配列を形成するパターンで印刷され、前記第1の誘電体層が隣接する半導体アイランドの第1のグループ上に或いはそれよりも上側に印刷され、前記第2の誘電体層が隣接する半導体アイランドの第2のグループ上に或いはそれよりも上側に印刷される、請求項2に記載の方法。
- 前記複数の半導体アイランドの少なくとも1つのサブセット上に或いはそれよりも上側にゲート誘電体層を形成するステップを更に備える、請求項1に記載の方法。
- 前記各ゲート誘電体層上にゲート前駆インクを印刷するとともに、前記ゲート前駆物質からゲートを形成するステップを更に備える、請求項5に記載の方法。
- 前記アニールが、ソース/ドレイン端子を形成するのに十分な時間にわたって且つ温度で行われる、請求項1に記載の方法。
- 前記第1の誘電体層及び前記第2の誘電体層を印刷した後、前記第1の誘電体層中及び前記第2の誘電体層中にコンタクトホールを形成して、(i)ゲートの上面の少なくとも一部と、(ii)少なくとも部分的に露出されたゲートの両側にある半導体アイランドの一部とを露出させるステップを更に備える、請求項1に記載の方法。
- 前記第1及び第2の誘電体層上並びにゲート及び半導体アイランドの露出面上に金属インクを印刷し、印刷された金属インクから金属層を形成するステップを更に備える、請求項8に記載の方法。
- MOSトランジスタを形成する方法であって、
a)完全に露出したゲート誘電体層上に或いはそれよりも上側にトランジスタゲートを形成するステップであって、前記ゲート誘電体層が複数の半導体アイランドそれぞれ上にあり、前記複数の半導体アイランドそれぞれが基板における実質的に水平で完全に露出した面上にある、当該ステップと、
b)前記トランジスタゲートの第1のサブセット上に或いはそれよりも上側に第1の誘電体層を印刷するとともに、前記トランジスタゲートの第2のサブセット上に或いはそれよりも上側に第2の誘電体層を印刷するステップであって、前記第1及び第2の誘電体層が互いに横に隣接し、前記第1の誘電体層が第1のドーパントを含み、前記第2の誘電体層が前記第1のドーパントとは異なる第2のドーパントを含む、当該ステップと、
c)前記第1及び第2の誘電体層のそれぞれにコンタクトホールを形成して、前記各トランジスタゲートの上面を露出させるステップと、
d)前記コンタクトホールを広げるために十分に前記第1及び第2の誘電体層をエッチングするステップと、
を備える方法。 - コンタクトホールを形成する前記ステップが、前記第1の誘電体層及び前記第2の誘電体層の一部を除去するステップを備える、請求項10に記載の方法。
- 前記第1及び第2の誘電体層を印刷する前記ステップが、前記コンタクトホールを形成するステップを更に備える、請求項10に記載の方法。
- a)実質的に水平な面を有する基板と、
b)前記基板の実質的に水平な面上に設けられ、第1の拡散性ドーパントを含む複数の第1の印刷された半導体アイランドと、
c)前記基板の実質的に水平な面上に設けられ、前記複数の第1の印刷された半導体アイランドに隣接し、前記第1の拡散性ドーパントとは異なる第2の拡散性ドーパントを含む複数の第2の印刷された半導体アイランドと、
d)前記第1の印刷された半導体アイランド上に設けられ、前記第1の拡散性ドーパントを含む第1の誘電体膜と、
e)前記第2の印刷された半導体アイランド上に設けられ、前記第2の拡散性ドーパントを含み、前記第1の誘電体膜に横に隣接する第2の誘電体膜と、
f)前記第1の印刷された半導体アイランド及び前記第2の印刷された半導体アイランドと電気的に接触する金属層と、
を備える電子デバイス。 - 前記各半導体アイランドがIVA族元素を含む、請求項13に記載の電子デバイス。
- 前記IVA族元素がシリコンを含む、請求項14に記載の電子デバイス。
- 前記第1及び第2の複数の半導体アイランドのそれぞれの少なくとも1つのサブセット上上に或いはそれよりも上側に設けられたゲート誘電体層と、前記ゲート誘電体層上に設けられたゲートとを更に備えている、請求項13に記載の電子デバイス。
- 前記第1及び第2の誘電体層が重なり合う、請求項13に記載の電子デバイス。
- 前記第1及び第2の誘電体膜の少なくとも1つのサブセット上に設けられ、下側に位置するゲートの上面の少なくとも一部と少なくとも部分的に露出された各ゲートの両側の各半導体アイランドの一部とを露出させるコンタクトホールを更に備え、前記金属層が、露出されたゲートの前記上面と前記半導体アイランドの露出部分とに接触している、請求項13に記載の電子デバイス。
Applications Claiming Priority (6)
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US83812506P | 2006-08-15 | 2006-08-15 | |
US60/838,125 | 2006-08-15 | ||
US11/888,949 | 2007-08-03 | ||
US11/888,949 US7767520B2 (en) | 2006-08-15 | 2007-08-03 | Printed dopant layers |
US11/888,942 US7701011B2 (en) | 2006-08-15 | 2007-08-03 | Printed dopant layers |
US11/888,942 | 2007-08-03 |
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JP5019320B2 true JP5019320B2 (ja) | 2012-09-05 |
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EP (1) | EP1890322A3 (ja) |
JP (1) | JP5019320B2 (ja) |
KR (2) | KR100967586B1 (ja) |
CN (1) | CN101136366B (ja) |
TW (1) | TWI375280B (ja) |
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JP2010533983A (ja) * | 2007-07-17 | 2010-10-28 | コヴィオ インコーポレイテッド | シード印刷及びめっきによるコンタクト金属及び相互接続金属の印刷 |
EP2436037B1 (en) * | 2009-05-28 | 2020-04-15 | Thin Film Electronics ASA | Semiconductor devices on diffusion barrier coated substrates and methods of making the same |
JP5555469B2 (ja) * | 2009-10-05 | 2014-07-23 | 東京応化工業株式会社 | 拡散剤組成物、および不純物拡散層の形成方法 |
US8877546B2 (en) * | 2010-05-28 | 2014-11-04 | Corning Incorporated | Enhanced semiconductor devices employing photoactive organic materials and methods of manufacturing same |
JP5750727B2 (ja) * | 2010-09-16 | 2015-07-22 | 国立研究開発法人産業技術総合研究所 | ナノ結晶半導体材料及びその製造方法 |
JP5647881B2 (ja) * | 2010-12-17 | 2015-01-07 | スタンレー電気株式会社 | 酸化亜鉛系半導体の成長方法 |
JP5935255B2 (ja) * | 2011-07-22 | 2016-06-15 | 日立化成株式会社 | インクジェット用不純物拡散層形成組成物、不純物拡散層の製造方法、太陽電池素子の製造方法及び太陽電池の製造方法 |
JP2014045065A (ja) * | 2012-08-27 | 2014-03-13 | Dainippon Screen Mfg Co Ltd | 基板処理方法および基板処理装置 |
JP6333377B2 (ja) * | 2014-07-16 | 2018-05-30 | 株式会社Joled | トランジスタ、表示装置および電子機器 |
CN107293591B (zh) | 2016-04-11 | 2020-03-31 | 华邦电子股份有限公司 | 印刷线路、薄膜晶体管及其制造方法 |
TWI601454B (zh) * | 2016-04-11 | 2017-10-01 | 華邦電子股份有限公司 | 印刷線路、薄膜電晶體及其製造方法 |
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JPS63108082A (ja) | 1986-10-24 | 1988-05-12 | Hitachi Chem Co Ltd | 酸化ケイ素被膜形成用塗布液 |
JPH02224340A (ja) * | 1989-02-27 | 1990-09-06 | Seiko Epson Corp | 薄膜トランジスタの製造方法 |
KR970003834B1 (en) * | 1993-10-06 | 1997-03-22 | Lg Semicon Co Ltd | Manufacture for thin film transistor |
US5770490A (en) | 1996-08-29 | 1998-06-23 | International Business Machines Corporation | Method for producing dual work function CMOS device |
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JP2000277738A (ja) * | 1999-03-19 | 2000-10-06 | Fujitsu Ltd | 薄膜トランジスタおよびその製造方法 |
JP2003318119A (ja) * | 2002-04-22 | 2003-11-07 | Seiko Epson Corp | シリコン膜およびその形成方法、ならびに、液晶表示装置、有機el表示装置、電子機器および機器 |
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JP2004304022A (ja) | 2003-03-31 | 2004-10-28 | Seiko Epson Corp | トランジスタの製造方法、トランジスタ、トランジスタを用いた集積回路、電気光学装置及び電子機器 |
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JP4498715B2 (ja) * | 2003-09-26 | 2010-07-07 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
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JP2005228792A (ja) * | 2004-02-10 | 2005-08-25 | Seiko Epson Corp | ドープシリコン膜の形成方法及びデバイスの製造方法 |
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JP2005251982A (ja) * | 2004-03-04 | 2005-09-15 | Seiko Epson Corp | シリコン膜の形成方法、当該シリコン膜の形成方法を使用するデバイスの製造方法及び当該デバイスの製造方法を使用する電気光学機器の製造方法 |
JP4652718B2 (ja) * | 2004-04-30 | 2011-03-16 | ミクロ技研株式会社 | 液晶ディスプレイの製造方法 |
JP2006140335A (ja) | 2004-11-12 | 2006-06-01 | Seiko Epson Corp | 相補型トランジスタ回路、電気光学装置、電子デバイス、及び相補型トランジスタの製造方法 |
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2007
- 2007-08-13 EP EP07015916A patent/EP1890322A3/en not_active Withdrawn
- 2007-08-14 KR KR1020070081936A patent/KR100967586B1/ko not_active IP Right Cessation
- 2007-08-15 CN CN 200710142711 patent/CN101136366B/zh not_active Expired - Fee Related
- 2007-08-15 TW TW96130074A patent/TWI375280B/zh not_active IP Right Cessation
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JP2008103686A (ja) | 2008-05-01 |
TWI375280B (en) | 2012-10-21 |
CN101136366A (zh) | 2008-03-05 |
CN101136366B (zh) | 2012-02-15 |
EP1890322A2 (en) | 2008-02-20 |
EP1890322A3 (en) | 2012-02-15 |
TW200818337A (en) | 2008-04-16 |
KR20080015749A (ko) | 2008-02-20 |
KR100967586B1 (ko) | 2010-07-05 |
KR20100046116A (ko) | 2010-05-06 |
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