JP4942020B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4942020B2 JP4942020B2 JP2006133680A JP2006133680A JP4942020B2 JP 4942020 B2 JP4942020 B2 JP 4942020B2 JP 2006133680 A JP2006133680 A JP 2006133680A JP 2006133680 A JP2006133680 A JP 2006133680A JP 4942020 B2 JP4942020 B2 JP 4942020B2
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- semiconductor chip
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- main surface
- electrode pads
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Description
2 第2半導体チップ
3 モジュール基板
4 半導体装置
100、102、104、107 第1半導体チップの辺
101、103、105、106、108 第1半導体チップの電極パッド
200、202、204 第2半導体チップの辺
201、203、205 第2半導体チップの電極パッド
301、304、306、308 モジュール基板の辺
302、303、305、307、309 モジュール基板のボンディングリード
500、501、502、505、506、507、508 ボンディングワイヤ
CL1 モジュール基板の中心線
CL2 半導体チップの中心線
Claims (4)
- 平面形状が四角形から成る主面、前記主面に形成された複数のボンディングリード、及び前記主面とは反対側の裏面を有するモジュール基板と、
平面形状が四角形から成る第1主面、前記第1主面に形成された集積された第1回路、前記第1主面に形成され、かつ前記第1回路に接続する複数の第1電極パッド、前記第1主面に形成され、かつ前記第1回路に接続する複数の第2電極パッド、及び前記第1主面とは反対側の第1裏面を有し、前記モジュール基板の前記主面に搭載された第1半導体チップと、
平面形状が四角形から成る第2主面、前記第2主面に形成された集積された第2回路、前記第2主面に形成され、かつ前記第2回路に接続する複数の第3電極パッド、前記第2主面に形成され、かつ前記第2回路に接続する複数の第4電極パッド、及び前記第2主面とは反対側の第2裏面を有し、前記第1半導体チップの前記第1主面に搭載された第2半導体チップと、
前記第1電極パッドと前記複数のボンディングリードのうちの第1ボンディングリードとを電気的に接続する第1ワイヤと、
前記第3電極パッドと前記複数のボンディングリードのうちの第2ボンディングリードとを電気的に接続する第2ワイヤと、
前記複数の第2電極パッドのうちの第5電極パッドと前記複数のボンディングリードのうちの第3ボンディングリードとを電気的に接続する第3ワイヤと、
前記複数の第4電極パッドと前記複数の第2電極パッドのうちの第6電極パッドとを電気的に接続する第4ワイヤと、
前記第1半導体チップ、前記第2半導体チップ、前記第1ワイヤ、前記第2ワイヤ、前記第3ワイヤ、及び前記第4ワイヤを封止する封止体と、を含み、
前記モジュール基板の前記主面は、第1辺と、前記第1辺と対向する第2辺を有し、
前記第1ボンディングリードは、前記第1辺に沿って配置されており、
前記第2ボンディングリードは、前記第1辺と前記第1ボンディングリードとの間に前記第1辺に沿って配置されており、
前記第3ボンディングリードは、前記第2辺に沿って配置されており、
前記第1半導体チップは、前記第1ボンディングリードと前記第3ボンディングリードとの間に配置され、
前記第1半導体チップの前記第1主面は、前記モジュール基板の前記第1辺と並ぶ第3辺と、前記第3辺と対向する第4辺とを有し、
前記複数の第1電極パッドは、前記第3辺に沿って配置され、
前記複数の第2電極パッドは、前記第4辺に沿って配置され、
前記第2半導体チップは、前記複数の第1電極パッドと前記複数の第2電極パッドとの間に配置され、
前記第2半導体チップの前記第2主面は、前記第1半導体チップの前記第3辺と並ぶ第5辺と、前記第5辺と対向する第6辺とを有し、
前記複数の第3電極パッドは、前記第5辺に沿って配置され、
前記複数の第4電極パッドは、前記第6辺に沿って配置され、
断面視において、前記モジュール基板の前記第1辺と前記第1半導体チップの前記第3辺の間隔は、前記モジュール基板の前記第2辺と前記第1半導体チップの前記第4辺の間隔よりも大きく、
前記第4電極パッドは、前記第6辺の縁辺部分に集約され、
前記第6電極パッドは、前記第4辺の縁辺部分に集約され、
前記第4ワイヤを共有する前記第4電極パッドと前記第6電極パッドは相互に一方が出力端子であり、他方が入力端子であることを特徴とする半導体装置。 - 断面視において、前記第2半導体チップの中心部は、前記モジュール基板の前記第1辺よりも前記モジュール基板の中心部から前記モジュール基板の前記第2辺に向かって偏倚していることを特徴とする請求項1記載の半導体装置。
- 複数のボール電極が前記モジュール基板の前記裏面に形成されていることを特徴とする請求項1記載の半導体装置。
- 前記第1半導体チップは、CCDカメラの動作を制御するタイミング制御信号を生成するタイミング・コントローラであり、
前記第2半導体チップは、前記CCDカメラに駆動電圧を出力するドライバであることを特徴とする請求項1記載の半導体装置。
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JP2006133680A JP4942020B2 (ja) | 2006-05-12 | 2006-05-12 | 半導体装置 |
US11/734,973 US7745941B2 (en) | 2006-05-12 | 2007-04-13 | Semiconductor device having shifted stacked chips |
CN2007101022794A CN101071810B (zh) | 2006-05-12 | 2007-05-09 | 半导体器件 |
US12/780,395 US8138611B2 (en) | 2006-05-12 | 2010-05-14 | Semiconductor device having shifted stacked chips |
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JP2010177456A (ja) * | 2009-01-29 | 2010-08-12 | Toshiba Corp | 半導体デバイス |
JP5645371B2 (ja) * | 2009-05-15 | 2014-12-24 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
KR102379591B1 (ko) * | 2014-04-10 | 2022-03-30 | 삼성디스플레이 주식회사 | 전자부품, 이를 포함하는 전자기기 및 전자기기의 본딩 방법 |
US11457531B2 (en) | 2013-04-29 | 2022-09-27 | Samsung Display Co., Ltd. | Electronic component, electric device including the same, and bonding method thereof |
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US10777478B2 (en) | 2016-07-15 | 2020-09-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device for power device |
KR102571267B1 (ko) * | 2018-09-19 | 2023-08-29 | 에스케이하이닉스 주식회사 | 부분 중첩 반도체 다이 스택 패키지 |
TWI686924B (zh) * | 2018-10-18 | 2020-03-01 | 普誠科技股份有限公司 | 積體電路及其測試方法 |
CN112309875A (zh) * | 2020-11-02 | 2021-02-02 | 南方电网科学研究院有限责任公司 | 一种芯片封装方法 |
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JP2002043503A (ja) * | 2000-07-25 | 2002-02-08 | Nec Kyushu Ltd | 半導体装置 |
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JP4417150B2 (ja) * | 2004-03-23 | 2010-02-17 | 株式会社ルネサステクノロジ | 半導体装置 |
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US9275940B2 (en) | 2013-07-19 | 2016-03-01 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
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