CN112309875A - 一种芯片封装方法 - Google Patents
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Abstract
本发明公开了一种芯片封装方法,包括:1)准备一用于承载芯片的基板,在该基板的上表面形成上线路层、并在上线路层表面形成上焊罩层,在该基板的下表面形成下线路层、并在下线路层的表面形成下焊罩层;2)在上焊罩层的表面设置引线焊盘A和引线焊盘B;3)采用粘晶层覆盖于上焊罩层上,并采用芯片A压在粘晶层上形成芯片A与上焊罩层的连接;4)将芯片A上的焊盘分别与基板上表面的引线焊盘A通过金属导线连接;5)采用粘性薄膜层覆盖于芯片A上,并采用芯片B压在粘性薄膜层上形成芯片B与芯片A的连接;6)将芯片B上的焊盘分别与基板上表面的引线焊盘B通过金属导线连接;该芯片封装方法采用堆叠式进行封装,减少基板占用空间。
Description
技术领域
本发明涉及一种芯片封装方法。
背景技术
封装(Package)对于芯片来说是必须的,也是至关重要的。封装也可以说是指安装半导体集成电路芯片用的外壳,它不仅起着保护芯片和增强导热性能的作用,而且还是沟通芯片内部世界与外部电路的桥梁和规格通用功能的作用。封装的主要作用有:
(1)物理保护。因为芯片必须与外界隔离,以防止空气中的杂质对芯片电路的腐蚀而造成电气性能下降,保护芯片表面以及连接引线等,使相当柔嫩的芯片在电气或热物理等方面免受外力损害及外部环境的影响;同时通过封装使芯片的热膨胀系数与框架或基板的热膨胀系数相匹配,这样就能缓解由于热等外部环境的变化而产生的应力以及由于芯片发热而产生的应力,从而可防止芯片损坏失效。基于散热的要求,封装越薄越好,当芯片功耗大于2W时,在封装上需要增加散热片或热沉片,以增强其散热冷却功能;5~1OW时必须采取强制冷却手段。另一方面,封装后的芯片也更便于安装和运输。
(2)电气连接。封装的尺寸调整(间距变换)功能可由芯片的极细引线间距,调整到实装基板的尺寸间距,从而便于实装操作。例如从以亚微米(目前已达到0.1 3μm以下)为特征尺寸的芯片,到以10μm为单位的芯片焊点,再到以100μm为单位的外部引脚,最后剑以毫米为单位的印刷电路板,都是通过封装米实现的。封装在这里起着由小到大、由难到易、由复杂到简单的变换作用,从而可使操作费用及材料费用降低,而且能提高工作效率和可靠性,特别是通过实现布线长度和阻抗配比尽可能地降低连接电阻,寄生电容和电感来保证正确的信号波形和传输速度。
(3)标准规格化。规格通用功能是指封装的尺寸、形状、引脚数量、间距、长度等有标准规格,既便于加工,又便于与印刷电路板相配合,相关的生产线及生产设备都具有通用性。这对于封装用户、电路板厂家、半导体厂家都很方便,而且便于标准化。相比之下,裸芯片实装及倒装目前尚不具备这方面的优势。由于组装技术的好坏还直接影响到芯片自身性能的发挥和与之连接的印刷电路板(PCB)的设计和制造,对于很多集成电路产品而言,组装技术都是非常关键的一环。
现有针对于多个芯片集成于一基板上的封装方式多是采用各个芯片进行平行封装,而这种封装方式会导致基板的占用空间变大,影响其应用。
发明内容
针对现有技术中的不足,本发明的目的是提供一种采用堆叠式进行封装,减少基板占用空间的芯片封装方法。
本发明解决其技术问题所采用的技术方案是:
一种芯片封装方法,包括:
1)准备一用于承载芯片的基板,在该基板的上表面形成上线路层、并在上线路层表面形成上焊罩层,在该基板的下表面形成下线路层、并在下线路层的表面形成下焊罩层;
2)在上焊罩层的表面设置引线焊盘A和引线焊盘B;
3)采用粘晶层覆盖于上焊罩层上,并采用芯片A压在粘晶层上形成芯片A与上焊罩层的连接;
4)将芯片A上的焊盘分别与基板上表面的引线焊盘A通过金属导线连接;
5)采用粘性薄膜层覆盖于芯片A上,并采用芯片B压在粘性薄膜层上形成芯片B与芯片A的连接;
6)将芯片B上的焊盘分别与基板上表面的引线焊盘B通过金属导线连接;
7)对基板、芯片A和芯片B的整个器件进行模压,用高温下熔化的塑封胶充入模具中,在芯片上形成塑封胶。
作为优选,在步骤1)中,所述上焊罩层的厚度小于下焊罩层的厚度。
进一步的,在步骤3)中,所述粘晶层与上焊罩层的热膨胀系数相同。
更进一步的,在步骤3)中,所述引线焊盘A和引线焊盘B分别呈圆周式设置、且引线焊盘A的直径小于引线焊盘B的直径。
更进一步的,在步骤3)中,所述引线焊盘A和引线焊盘B组合呈一圆周式分布、且引线焊盘A的直径等于引线焊盘B的直径。
优选的,在步骤6)中,所述芯片B的尺寸小于芯片A的尺寸。
优选的,在步骤6)中,所述芯片B与芯片A的中心位置相对准。
本发明的有益效果是:
在本方案中,采用了芯片A与芯片B进行纵向堆叠的方式,搭配上粘晶层和粘性薄膜层来进行芯片与基板、芯片与芯片之间的连接配合,并搭配了不同位置的引线焊盘来实现芯片引脚的对接,以实现芯片的纵向堆叠封装,减少基板的占用空间。
具体实施方式
下面结合具体实施例对本发明作进一步说明,以使本领域技术人员可以更好的理解本发明并能予以实施,但所举实施例不作为对本发明的限定。
实施例1
一种芯片封装方法,包括:
1)准备一用于承载芯片的基板,在该基板的上表面形成上线路层、并在上线路层表面形成上焊罩层,在该基板的下表面形成下线路层、并在下线路层的表面形成下焊罩层;
2)在上焊罩层的表面设置引线焊盘A和引线焊盘B;
3)采用粘晶层覆盖于上焊罩层上,并采用芯片A压在粘晶层上形成芯片A与上焊罩层的连接;
4)将芯片A上的焊盘分别与基板上表面的引线焊盘A通过金属导线连接;
5)采用粘性薄膜层覆盖于芯片A上,并采用芯片B压在粘性薄膜层上形成芯片B与芯片A的连接;
6)将芯片B上的焊盘分别与基板上表面的引线焊盘B通过金属导线连接;
7)对基板、芯片A和芯片B的整个器件进行模压,用高温下熔化的塑封胶充入模具中,在芯片上形成塑封胶。
在步骤1)中,所述上焊罩层的厚度小于下焊罩层的厚度。
在步骤3)中,所述粘晶层与上焊罩层的热膨胀系数相同。
在步骤3)中,所述引线焊盘A和引线焊盘B分别呈圆周式设置、且引线焊盘A的直径小于引线焊盘B的直径。
在步骤6)中,所述芯片B的尺寸小于芯片A的尺寸。
在步骤6)中,所述芯片B与芯片A的中心位置相对准。
在该方案中,芯片A与芯片B呈金字塔状,其对应的金属导线呈内外交错分布。
实施例2
一种芯片封装方法,包括:
1)准备一用于承载芯片的基板,在该基板的上表面形成上线路层、并在上线路层表面形成上焊罩层,在该基板的下表面形成下线路层、并在下线路层的表面形成下焊罩层;
2)在上焊罩层的表面设置引线焊盘A和引线焊盘B;
3)采用粘晶层覆盖于上焊罩层上,并采用芯片A压在粘晶层上形成芯片A与上焊罩层的连接;
4)将芯片A上的焊盘分别与基板上表面的引线焊盘A通过金属导线连接;
5)采用粘性薄膜层覆盖于芯片A上,并采用芯片B压在粘性薄膜层上形成芯片B与芯片A的连接;
6)将芯片B上的焊盘分别与基板上表面的引线焊盘B通过金属导线连接;
7)对基板、芯片A和芯片B的整个器件进行模压,用高温下熔化的塑封胶充入模具中,在芯片上形成塑封胶。
在步骤1)中,所述上焊罩层的厚度小于下焊罩层的厚度。
在步骤3)中,所述粘晶层与上焊罩层的热膨胀系数相同。
在步骤3)中,所述引线焊盘A和引线焊盘B组合呈一圆周式分布、且引线焊盘A的直径等于引线焊盘B的直径。
在步骤6)中,所述芯片B的尺寸小于芯片A的尺寸。
在步骤6)中,所述芯片B与芯片A的中心位置相对准。
在该方案中,芯片A与芯片B呈金字塔状,其对应的金属导线呈左右侧互不干涉分布。
本发明的有益效果是:
在本方案中,采用了芯片A与芯片B进行纵向堆叠的方式,搭配上粘晶层和粘性薄膜层来进行芯片与基板、芯片与芯片之间的连接配合,并搭配了不同位置的引线焊盘来实现芯片引脚的对接,以实现芯片的纵向堆叠封装,减少基板的占用空间。
本发明的上述实施例并不是对本发明保护范围的限定,本发明的实施方式不限于此,凡此种种根据本发明的上述内容,按照本领域的普通技术知识和惯用手段,在不脱离本发明上述基本技术思想前提下,对本发明上述结构做出的其它多种形式的修改、替换或变更,均应落在本发明的保护范围之内。
Claims (7)
1.一种芯片封装方法,其特征在于,包括:
1)准备一用于承载芯片的基板,在该基板的上表面形成上线路层、并在上线路层表面形成上焊罩层,在该基板的下表面形成下线路层、并在下线路层的表面形成下焊罩层;
2)在上焊罩层的表面设置引线焊盘A和引线焊盘B;
3)采用粘晶层覆盖于上焊罩层上,并采用芯片A压在粘晶层上形成芯片A与上焊罩层的连接;
4)将芯片A上的焊盘分别与基板上表面的引线焊盘A通过金属导线连接;
5)采用粘性薄膜层覆盖于芯片A上,并采用芯片B压在粘性薄膜层上形成芯片B与芯片A的连接;
6)将芯片B上的焊盘分别与基板上表面的引线焊盘B通过金属导线连接;
7)对基板、芯片A和芯片B的整个器件进行模压,用高温下熔化的塑封胶充入模具中,在芯片上形成塑封胶。
2.根据权利要求1所述的一种芯片封装方法,其特征在于:在步骤1)中,所述上焊罩层的厚度小于下焊罩层的厚度。
3.根据权利要求2所述的一种芯片封装方法,其特征在于:在步骤3)中,所述粘晶层与上焊罩层的热膨胀系数相同。
4.根据权利要求3所述的一种芯片封装方法,其特征在于:在步骤3)中,所述引线焊盘A和引线焊盘B分别呈圆周式设置、且引线焊盘A的直径小于引线焊盘B的直径。
5.根据权利要求3所述的一种芯片封装方法,其特征在于:在步骤3)中,所述引线焊盘A和引线焊盘B组合呈一圆周式分布、且引线焊盘A的直径等于引线焊盘B的直径。
6.根据权利要求4或5所述的一种芯片封装方法,其特征在于:在步骤6)中,所述芯片B的尺寸小于芯片A的尺寸。
7.根据权利要求6所述的一种芯片封装方法,其特征在于:在步骤6)中,所述芯片B与芯片A的中心位置相对准。
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CN101071810A (zh) * | 2006-05-12 | 2007-11-14 | 株式会社瑞萨科技 | 半导体器件 |
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