JP4931211B2 - ハイブリッド結晶配向基板上の高性能cmossoiデバイス - Google Patents
ハイブリッド結晶配向基板上の高性能cmossoiデバイス Download PDFInfo
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- JP4931211B2 JP4931211B2 JP2006516124A JP2006516124A JP4931211B2 JP 4931211 B2 JP4931211 B2 JP 4931211B2 JP 2006516124 A JP2006516124 A JP 2006516124A JP 2006516124 A JP2006516124 A JP 2006516124A JP 4931211 B2 JP4931211 B2 JP 4931211B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Description
絶縁層によって分離された第1の結晶配向の少なくとも第1の半導体層と第2の結晶配向の第2の半導体層とを含み、第1の結晶配向が第2の結晶配向とは異なり、第1の半導体層が第2の半導体層上におかれている、結合された基板を用意するステップと、
結合された基板の一部が保護されて第1の領域が定められ、結合された基板の別の部分が保護されないまま残され、結合された基板の該保護されない部分が第2の領域を定めるようにするステップと、
結合された基板の保護されない部分をエッチングして、第2の半導体層の表面を露出するステップと、
第2の半導体層の露出された表面上に、第2の結晶配向と同じ結晶配向を有する半導体材料を再成長させるステップと、
半導体材料を含む結合された基板を平坦化して、第1の半導体層の上面が半導体材料の上面と実質的に平坦になるように、異なる結晶配向の少なくとも2つの平坦な領域を有するハイブリッド基板を与えるステップと、
第1の領域に少なくとも1つの第1半導体デバイスを形成し、第2の領域の半導体材料上に少なくとも1つの第2半導体デバイスを形成するステップと、
を含む。
第1の結晶配向を有する第1デバイス領域と第1の結晶配向とは異なる第2の結晶配向を有する第2デバイス領域とを含む結合された基板と、
第2デバイス領域から第1デバイス領域を分離する分離領域と、
第1デバイス領域に配置された少なくとも1つの第1半導体デバイス及び第2デバイス領域に配置された少なくとも1つの第2半導体デバイスと、
を含む。
Claims (16)
- ハイブリッド結晶配向基板上にCMOSデバイスを形成する方法であって、
第1の結晶配向の第1の半導体層と、絶縁層によって分離された第2の結晶配向の第2の半導体層とを少なくとも含む結合された基板を用意するステップであって、前記第1の結晶配向が前記第2の結晶配向とは異なり、前記第1の半導体層が前記第2の半導体層上におかれている、前記用意するステップと、
前記結合された基板の一部が保護されて、前記結合された基板の前記保護された部分が第1の領域を定めるように、前記結合された基板の別の部分が保護されないまま残され、前記結合された基板の前記保護されない部分が第2の領域を定めるようにするステップと、
前記結合された基板の前記保護されない部分をエッチングして、前記第2の半導体層の表面を露出するステップと、
前記エッチングによって露出された側壁上にスペーサを形成するステップと、
前記第2の半導体層の前記露出された表面上に、前記第2の結晶配向と同じ結晶配向を有する半導体材料を再成長させるステップと、
前記半導体材料を含む前記結合された基板を平坦化して、前記第1の半導体層の上面が前記半導体材料の上面と平坦になるようにするステップと、
平坦化された前記結合された基板にわたって材料スタックを形成し、そして前記第1の半導体層内の前記材料スタック中にトレンチ開口部を形成するステップであって、前記トレンチ開口部の形成は、前記スペーサの上部を除去し、且つ前記トレンチ開口部を前記絶縁層の頂部表面に伸張させる、前記形成するステップと、
前記トレンチ開口部を誘電材料で充填することによって少なくとも1つのトレンチ誘電部分を形成するステップであって、前記少なくとも1つのトレンチ誘電部分は、前記スペーサの残りの下部の頂部表面に垂直に接触し、それによって、少なくとも1つのトレンチ誘電部分が前記第1の領域を前記第2の領域から水平方向に分離する、前記形成するステップと、
前記第1の領域に少なくとも1つの第1半導体デバイスを形成し、前記第2の領域の前記半導体材料上に少なくとも1つの第2半導体デバイスを形成するステップと
を含む、前記方法。 - 前記結合された基板がさらに、前記第1の半導体の材料上に配置された表面誘電体層を含む、請求項1に記載の方法。
- 前記結合された基板が、2つのシリコン・オン・インシュレータ(SOI)ウェハ、SOIウェハとバルク半導体ウェハ、2つのバルク半導体ウェハ、又はSOIウェハと加熱後に間隙を形成するイオン打ち込み領域を含むバルク半導体ウェハとから形成される、請求項1に記載の方法。
- 前記結合された基板が、2つのウェハを互いに緊密に接触させ、接触させられたウェハを不活性雰囲気中で加熱することによって形成される、請求項1に記載の方法。
- 前記加熱は、200℃〜1050℃の温度で2〜20時間にわたって行われる、請求項4に記載の方法。
- 前記保護は、パターン形成されたマスクの使用を含む、請求項1に記載の方法。
- 前記パターン形成されたマスクは、パターン形成されたフォトレジスト、パターン形成された窒化物又はパターン形成された酸窒化物である、請求項6に記載の方法。
- 前記半導体材料は、選択的エピタキシャル成長法を用いて形成される、請求項1に記載の方法。
- 前記半導体材料は、Si、歪みSi、SiGe、SiC、SiGeC、及びこれらの組み合わせから選択されたSi含有半導体である、請求項1に記載の方法。
- 前記平坦化は、化学的機械的研磨又は研削である、請求項1に記載の方法。
- エッチングの後で、しかし少なくとも1つの半導体デバイスを形成する前に、分離領域を形成するステップをさらに含む、請求項1に記載の方法。
- 前記半導体デバイスがNFET又はPFETである、請求項1に記載の方法。
- 前記第1の半導体層が(110)結晶配向を有し、前記第2の半導体層及び前記半導体材料の両方が(100)結晶配向を有する、請求項1に記載の方法。
- 前記第1半導体デバイスがPFETであり、前記第2半導体デバイスがNFETである、請求項13に記載の方法。
- 前記半導体デバイスが、歪みSi層上に形成される、請求項1に記載の方法。
- 前記半導体材料が、緩和SiGe合金層の上に配置された歪みSi層を含む、請求項1に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US10/250,241 US7329923B2 (en) | 2003-06-17 | 2003-06-17 | High-performance CMOS devices on hybrid crystal oriented substrates |
US10/250,241 | 2003-06-17 | ||
PCT/EP2004/050946 WO2004114400A1 (en) | 2003-06-17 | 2004-05-27 | High-performance cmos soi device on hybrid crystal-oriented substrates |
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JP2006527915A JP2006527915A (ja) | 2006-12-07 |
JP4931211B2 true JP4931211B2 (ja) | 2012-05-16 |
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JP2006516124A Expired - Fee Related JP4931211B2 (ja) | 2003-06-17 | 2004-05-27 | ハイブリッド結晶配向基板上の高性能cmossoiデバイス |
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US (2) | US7329923B2 (ja) |
EP (1) | EP1639637A1 (ja) |
JP (1) | JP4931211B2 (ja) |
KR (1) | KR100843489B1 (ja) |
CN (1) | CN100407408C (ja) |
IL (1) | IL172517A0 (ja) |
TW (1) | TWI318785B (ja) |
WO (1) | WO2004114400A1 (ja) |
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US7713807B2 (en) | 2010-05-11 |
TWI318785B (en) | 2009-12-21 |
KR100843489B1 (ko) | 2008-07-04 |
US20040256700A1 (en) | 2004-12-23 |
EP1639637A1 (en) | 2006-03-29 |
CN1836323A (zh) | 2006-09-20 |
US20080096330A1 (en) | 2008-04-24 |
KR20060021314A (ko) | 2006-03-07 |
US7329923B2 (en) | 2008-02-12 |
WO2004114400A1 (en) | 2004-12-29 |
IL172517A0 (en) | 2006-04-10 |
CN100407408C (zh) | 2008-07-30 |
JP2006527915A (ja) | 2006-12-07 |
TW200503176A (en) | 2005-01-16 |
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