JP4892209B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4892209B2 JP4892209B2 JP2005239610A JP2005239610A JP4892209B2 JP 4892209 B2 JP4892209 B2 JP 4892209B2 JP 2005239610 A JP2005239610 A JP 2005239610A JP 2005239610 A JP2005239610 A JP 2005239610A JP 4892209 B2 JP4892209 B2 JP 4892209B2
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- plasma treatment
- semiconductor device
- resin film
- resistant resin
- nitrogen atom
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Classifications
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- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Treatments Of Macromolecular Shaped Articles (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
で示される繰り返し単位を有するポリイミド化合物であり、ポリイミド、ポリアミド、ポリアミドイミド、ポリベンゾオキサゾール、ポリベンゾイミダゾール、ベンゾシクロブテン及びそれらのコポリマーなどがあげられる。また、ポリアミド、ポリイミド、ポリアミドイミド、ポリベンゾオキサゾール、ポリベンゾイミダゾール及びベンゾシクロブテンから選択される少なくとも1種のポリマーの前駆体も使用できる。この時、予め感光性処理されたポリイミド、ポリベンゾオキサゾールなどを用いることも可能である。市販されている耐熱性樹脂化合物として、日立化成デュポンマイクロシステムズ(株)製のHD4000シリーズ、HD8800シリーズ、PIQシリーズ等があげられる。
自己接着性のポリイミド前駆体樹脂ワニス(日立化成デュポンマイクロシステムズ(株)製HD4000)を5インチシリコン基板上に約3g滴下し、3800回転30秒でスピンコートした。ポリイミド前駆体樹脂ワニスを塗布したシリコン基板は80℃と90℃に保持したホットプレート上でそれぞれ100秒加熱ベークして溶媒を蒸散せしめ、膜厚10μmのポリイミド前駆体塗膜を形成した。この基板を窒素雰囲気の炉体で375℃、60分加熱して脱水縮合反応を行い、膜厚約5μmのポリイミド樹脂膜付き基板を得た。表面改質処理は、初めに、実工程の残渣除去を想定して、得られたポリイミド樹脂膜付き基板を、日本真空(株)製のプラズマエッチング装置(CSE−1110)を用いて、真空引きの後、85%/15%容量比の酸素/四フッ化メタン混合ガスを総流量25cc/分で流しながら、系内圧力10Pa、高周波電力100Wで2分間プラズマ処理を行い、混合ガスを排気した後、大気中に戻した。次いで、同装置を用いて、真空引きの後、窒素100%容量比の窒素ガスを総流量25cc/分で流しながら、系内圧力10Pa、高周波電力100Wで2分間プラズマ処理を行った。ポリイミド樹脂膜付き基板は複数用意し、半数はプラズマ処理後のポリイミド膜表面の濡れ性測定に使用した。
実施例1と同様にして作製したプラズマ処理を終えたポリイミド樹脂膜付き基板を、室温大気中で6ヶ月放置したのち、実施例1と同様にして、サンプル片を作製し、接合強度の測定と破壊モードの観察を行った。結果を表1に示す。
窒素ガスに代えて、窒素と水素3〜10容量%の混合ガスであるフォーミングガス100%容量比のガスを用いたことを除いて、実施例1と同様にしてプラズマ処理を行い、サンプル片を作製し、接合強度の測定と破壊モードの評価、及び濡れ性評価を行った。結果を表1に示す。
実施例1と同様にして作製した膜厚約5μmのポリイミド樹脂膜付き基板に、残渣処理のためのプラズマ処理及び窒素原子含有ガス中でのプラズマ処理を行うことなくサンプル片を作製し、このサンプル片について、実施例1と同様にして、接合強度の測定と破壊モードの評価、及び濡れ性評価を行った。結果を表1に示す。
実施例1と同様にして作製した膜厚約5μmのポリイミド樹脂膜付き基板に、残渣処理のためのプラズマ処理を行った後に、窒素原子含有ガスでプラズマ処理を行うことなくサンプル片を作製し、このサンプル片について、実施例1と同様にして、接合強度の測定と破壊モードの評価、及び濡れ性評価を行った。結果を表1に示す。
実施例1と同様にして作製した膜厚約5μmのポリイミド樹脂膜付き基板に、残渣除去のためのプラズマ処理を行ったのち、ヤマト科学製酸素プラズマ装置(型番PC101A)を用いて、酸素100%容量比の酸素ガスを流量100cc/分で流しながら、系内圧力133Pa、高周波電力400Wで5分間プラズマ処理を行ったことを除いて、実施例1と同様にして、サンプル片を作製し、接合強度の測定と破壊モードの評価、及び濡れ性評価を行った。結果を表1に示す。
実施例1と同様にして作製した膜厚約5μmのポリイミド樹脂膜付き基板に、残渣除去のためのプラズマ処理を行ったのち、窒素ガスに代えて、四フッ化メタン100%容量比の四フッ化メタンガスを用いたことを除いて、実施例1と同様にしてプラズマ処理を行い、サンプル片を作製し、接合強度の測定と破壊モードの評価、及び濡れ性評価を行った。結果を表1に示す。
Claims (7)
- 半導体素子上に形成する耐熱性樹脂膜とその上に積層するエポキシ系樹脂化合物とを有する半導体装置において、エポキシ系樹脂化合物層を積層する耐熱性樹脂膜の表面を、窒素、アンモニア、ヒドラジンの少なくとも1種を含有する窒素原子含有ガスを用いて、バイアス電圧の存在下、200℃以下の基板温度でプラズマ処理を行うことを特徴とする半導体装置の製造方法であり、窒素原子含有ガスによるプラズマ処理の前に、耐熱性樹脂膜の表面を、酸素又は酸素/四フッ化炭素混合ガスを用いてプラズマ処理を行う工程、および窒素原子含有ガスによるプラズマ処理により、アミド(-NH-)またはアミン(-NH2)の官能基を耐熱性樹脂膜の表面に形成する工程を含有する、半導体装置の製造方法。
- 窒素原子含有ガスによるプラズマ処理を、窒素、アンモニア、ヒドラジンの少なくとも1種を含有する窒素原子含有ガスと水素又は不活性ガスとを含む混合ガス中で行う、請求項1記載の半導体装置の製造方法。
- 窒素原子含有ガスによるプラズマ処理を、窒素、アンモニア、ヒドラジンの少なくとも1種を含有する窒素原子含有ガスの比率が20〜100容量%であるガス中で行う、請求項1又は2記載の半導体装置の製造方法。
- 半導体素子上に形成する耐熱性樹脂膜が、ポリイミド、ポリアミド、ポリアミドイミド、ポリベンゾキサゾール、ポリベンゾイミダゾール、ベンゾシクロブテン、又はこれらのコポリマーから選択される化合物を1種以上含む膜である、請求項1〜3のいずれか1項記載の半導体装置の製造方法。
- 窒素原子含有ガスによるプラズマ処理を、半導体加工用に使用されるドライエッチング装置中で行う、請求項1〜4のいずれか1項記載の半導体装置の製造方法。
- ドライエッチング装置の系内の圧力が0.5Paから常圧の範囲である、請求項5記載の半導体装置の製造方法。
- 耐熱性樹脂膜上に積層するエポキシ系樹脂化合物層が、アンダーフィル材、フィルム材、接着材又は封止材である、請求項1〜6のいずれか1項記載の半導体装置の製造方法。
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KR1020137004220A KR20130035271A (ko) | 2005-08-22 | 2006-08-22 | 반도체 장치의 제조 방법 |
PCT/JP2006/316345 WO2007023773A1 (ja) | 2005-08-22 | 2006-08-22 | 半導体装置の製造方法 |
CN2006800306576A CN101248520B (zh) | 2005-08-22 | 2006-08-22 | 半导体装置的制造方法 |
US12/064,511 US8975192B2 (en) | 2005-08-22 | 2006-08-22 | Method for manufacturing semiconductor device |
KR1020087003171A KR101284512B1 (ko) | 2005-08-22 | 2006-08-22 | 반도체 장치의 제조 방법 |
EP06796608.5A EP1918987B1 (en) | 2005-08-22 | 2006-08-22 | Method for manufacturing semiconductor device |
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WO2016194431A1 (ja) * | 2015-05-29 | 2016-12-08 | リンテック株式会社 | 半導体装置の製造方法 |
CN104900548A (zh) * | 2015-06-05 | 2015-09-09 | 华进半导体封装先导技术研发中心有限公司 | 低成本微凸点的制备工艺 |
JP2023062213A (ja) * | 2020-03-23 | 2023-05-08 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置およびその製造方法 |
CN113540058A (zh) * | 2021-06-03 | 2021-10-22 | 华润微集成电路(无锡)有限公司 | 一种高耐压光耦封装产品及制作方法 |
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TW200741903A (en) | 2007-11-01 |
WO2007023773A1 (ja) | 2007-03-01 |
US20090137129A1 (en) | 2009-05-28 |
TWI412090B (zh) | 2013-10-11 |
EP1918987A1 (en) | 2008-05-07 |
EP1918987B1 (en) | 2014-11-12 |
CN101248520B (zh) | 2010-05-19 |
EP1918987A4 (en) | 2012-09-19 |
KR20080036191A (ko) | 2008-04-25 |
JP2007059440A (ja) | 2007-03-08 |
CN101248520A (zh) | 2008-08-20 |
KR101284512B1 (ko) | 2013-07-16 |
KR20130035271A (ko) | 2013-04-08 |
US8975192B2 (en) | 2015-03-10 |
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