JP4887170B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4887170B2 JP4887170B2 JP2007032719A JP2007032719A JP4887170B2 JP 4887170 B2 JP4887170 B2 JP 4887170B2 JP 2007032719 A JP2007032719 A JP 2007032719A JP 2007032719 A JP2007032719 A JP 2007032719A JP 4887170 B2 JP4887170 B2 JP 4887170B2
- Authority
- JP
- Japan
- Prior art keywords
- multilayer wiring
- semiconductor device
- manufacturing
- wiring board
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
次に、図5(A)および図5(B)に示すように、半導体チップ30の外部電極端子が設けられた表面をフェイスダウンにした状態で、外部電極端子に設けられた各はんだバンプ32とそれらに対応する多層配線基板20の上面のC4バンプ27とをはんだ付けすることにより、複数の半導体チップ30を多層配線基板20にフリップチップ実装する。なお、図5以下では、多層配線基板20の詳細な構造については簡略化する。はんだバンプ32とC4バンプ27との接合は、たとえば、周知のリフロー処理により行うことができる。
次に、図6(A)に示すように、トランスファーモールド法、ポッディングなどの樹脂封止方法を用いて、多層配線基板20の上に隣接する多層配線層を跨るように封止樹脂層40を成型する。これにより、多層配線基板20上の複数の領域にそれぞれ実装された半導体チップ30が一度に封止される。なお、封止樹脂層40を成型は、既存のモールド装置、金型等を用いることが可能であるため、製造コストの増加を防ぐことができる。
この他、リッドが設けられた半導体装置を製造する場合について説明する。上述した封止樹脂形成では、多層配線基板20の上面全体に封止樹脂層40が形成されている。これに対して、半導体装置にリッドを設ける場合には、図1〜図5を参照して説明した工程の後、図8(A)に示すように、所定の金型を用いて、金属基板100に構築された多層配線基板20の上に各半導体チップ30の周囲に離間した封止樹脂層40を設ける。封止樹脂層40の上面の位置は、各半導体チップ30の上面の位置と等しいか、各半導体チップ30の上面の位置からたとえば1〜3mm程度高い位置とする。
Claims (3)
- 金属基板の上の複数の領域に多層配線層をそれぞれ構築する工程と、
前記各多層配線層の上面にそれぞれ半導体チップを実装する工程と、
前記各多層配線層の上に封止樹脂を成型する工程と、
前記封止樹脂および前記半導体チップの上面に熱インターフェース材料を介して、放熱部材を設置する工程と、
前記金属基板を前記各多層配線層から除去する工程と、
前記各領域を切断し、前記各多層配線層および放熱部材を個片化する工程と、
を備えることを特徴とする半導体装置の製造方法。 - 前記封止樹脂を成型する工程において、前記半導体チップの周囲に離間して前記封止樹脂が形成されることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記金属基板を剥離した後、前記各多層配線層の下面にはんだボールを搭載する工程をさらに備えることを特徴とする請求項1または2に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007032719A JP4887170B2 (ja) | 2007-02-13 | 2007-02-13 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007032719A JP4887170B2 (ja) | 2007-02-13 | 2007-02-13 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008198805A JP2008198805A (ja) | 2008-08-28 |
JP4887170B2 true JP4887170B2 (ja) | 2012-02-29 |
Family
ID=39757489
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007032719A Active JP4887170B2 (ja) | 2007-02-13 | 2007-02-13 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4887170B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI474413B (zh) * | 2009-01-15 | 2015-02-21 | Chipmos Technologies Inc | 晶片封裝結構的製程 |
JP5249173B2 (ja) * | 2009-10-30 | 2013-07-31 | 新光電気工業株式会社 | 半導体素子実装配線基板及びその製造方法 |
JP2014011289A (ja) * | 2012-06-29 | 2014-01-20 | Ibiden Co Ltd | 電子部品及び電子部品の製造方法 |
TWI501363B (zh) * | 2014-01-10 | 2015-09-21 | Sfi Electronics Technology Inc | 一種小型化表面黏著型二極體封裝元件及其製法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3277996B2 (ja) * | 1999-06-07 | 2002-04-22 | 日本電気株式会社 | 回路装置、その製造方法 |
JP2002033411A (ja) * | 2000-07-13 | 2002-01-31 | Nec Corp | ヒートスプレッダ付き半導体装置及びその製造方法 |
JP4043872B2 (ja) * | 2002-07-11 | 2008-02-06 | 大日本印刷株式会社 | 多層配線基板の製造方法および樹脂封止型半導体装置の製造方法 |
JP2006186321A (ja) * | 2004-12-01 | 2006-07-13 | Shinko Electric Ind Co Ltd | 回路基板の製造方法及び電子部品実装構造体の製造方法 |
-
2007
- 2007-02-13 JP JP2007032719A patent/JP4887170B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2008198805A (ja) | 2008-08-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101715761B1 (ko) | 반도체 패키지 및 그 제조방법 | |
TWI497620B (zh) | 矽貫通孔晶粒及封裝 | |
US9040361B2 (en) | Chip scale package with electronic component received in encapsulant, and fabrication method thereof | |
TWI644403B (zh) | 封裝結構及其製造方法 | |
TWI677062B (zh) | 晶片埋入式印刷電路板及應用印刷電路板之半導體封裝及其製造方法 | |
TWI649845B (zh) | 半導體封裝結構及其製造方法 | |
US8580608B2 (en) | Fabrication method of package structure having embedded semiconductor component | |
US20110221069A1 (en) | Semiconductor device and method of manufacturing the same | |
US9903024B2 (en) | Substrate having electrical interconnection structures and fabrication method thereof | |
JP2005322858A (ja) | 半導体装置の製造方法 | |
JP6816964B2 (ja) | 配線基板、半導体装置及び配線基板の製造方法 | |
TWI495026B (zh) | 晶片封裝基板和結構及其製作方法 | |
JP2006295127A (ja) | フリップチップパッケージ構造及びその製作方法 | |
US9748197B2 (en) | Methods for packaging integrated circuits | |
JP2010239126A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2009033153A (ja) | 半導体素子パッケージ用の相互接続構造およびその方法 | |
US20170358557A1 (en) | Package-on-package structure and manufacturing method thereof | |
JP5404513B2 (ja) | 半導体装置の製造方法 | |
TWI702709B (zh) | 用以製造具有多層模製導電基板和結構之半導體封裝的方法 | |
JP2008210912A (ja) | 半導体装置及びその製造方法 | |
JP4963879B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP2008181977A (ja) | パッケージ、そのパッケージの製造方法、そのパッケージを用いた半導体装置、そのパッケージを用いた半導体装置の製造方法 | |
JP4494249B2 (ja) | 半導体装置 | |
JP4887170B2 (ja) | 半導体装置の製造方法 | |
JPWO2015198837A1 (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100430 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100511 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100622 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100720 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20101126 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101214 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20110127 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110719 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111206 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111212 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141216 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 4887170 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |