TWI677062B - 晶片埋入式印刷電路板及應用印刷電路板之半導體封裝及其製造方法 - Google Patents

晶片埋入式印刷電路板及應用印刷電路板之半導體封裝及其製造方法 Download PDF

Info

Publication number
TWI677062B
TWI677062B TW106124279A TW106124279A TWI677062B TW I677062 B TWI677062 B TW I677062B TW 106124279 A TW106124279 A TW 106124279A TW 106124279 A TW106124279 A TW 106124279A TW I677062 B TWI677062 B TW I677062B
Authority
TW
Taiwan
Prior art keywords
base substrate
heat sink
circuit board
electronic component
printed circuit
Prior art date
Application number
TW106124279A
Other languages
English (en)
Other versions
TW201735293A (zh
Inventor
洪錫昌
Suk Chang Hong
卞貞洙
Jung Soo Byun
朴相甲
Sang Kab Park
廉光燮
Kwang Seop Youm
Original Assignee
南韓商三星電機股份有限公司
Samsung Electro-Mechanics Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南韓商三星電機股份有限公司, Samsung Electro-Mechanics Co., Ltd. filed Critical 南韓商三星電機股份有限公司
Publication of TW201735293A publication Critical patent/TW201735293A/zh
Application granted granted Critical
Publication of TWI677062B publication Critical patent/TWI677062B/zh

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • H05K1/0209External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/24246Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009Pre-treatment of the connector or the bonding area
    • H01L2224/8203Reshaping, e.g. forming vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094Thermal management, e.g. cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1461Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469Circuit made after mounting or encapsulation of the components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

本發明係揭露一種晶片埋入式印刷電路板、與應用印刷電路板之半導體封裝以及晶片埋入式印刷電路板之製造方法。
利用晶片埋入式印刷電路板之半導體封裝係包括上與下半導體封裝,具有堆疊式封裝層疊結構,其中下半導體封裝包括基底基材,基底基材包括預定的電路圖案形成於其中;電子元件,電性連接於電路圖案且埋入於基底基材之中,使得電子元件之一表面曝露於基底基材之上表面;以及散熱體,設置於電子元件之曝露表面上,以消散由電子元件所產生的熱至外部。
本發明可製造出具有優異的散熱功能之半導體封裝,且可增加產品之可靠度。

Description

晶片埋入式印刷電路板及應用印刷電路板之半導體封裝 及其製造方法
本發明係有關於一種晶片埋入式(chip-embedded)印刷電路板(Printed Circuit Board,PCB),使用此印刷電路板之半導體封裝,以及印刷電路板之製造方法,且更特別地,係有關於一種晶片埋入式印刷電路板,在印刷電路板之一部分的表面上提供散熱單元,散熱單元對應於埋入印刷電路板中之晶片,以增強散熱功能,利用此印刷電路板之半導體封裝,以及晶片埋入式印刷電路板之製造方法。
由於電子產品(例如手機與類似者)已經變為多功能,連接性與溝通頻率已有所增加,並且雙核心、四核心、或類似者係應用於印刷電路板中,需解決應用處理器(Application Processor,AP)封裝之散熱問題。
第1圖繪示根據先前技術之一實施例的半導體封裝,其具有堆疊式封裝層疊(Package on package,PoP)結構。
如第1圖所繪示,先前技術之半導體封裝具有堆疊 式封裝層疊結構,其中電子元件(應用處理器晶片或類似者)112和122係被封裝材料(molding material)113和123或類似者所塗佈。並且,可利用基板111與121之中的樹脂(resin)埋入(buried)電子元件112與122。
因此,從電子元件112與122所產生的熱無法順利地消散,導致裝置故障或品質降低。在第1圖中,分別地,標號110表示上半導體封裝,標號120表示下半導體封裝。
本發明之目的係用以提供晶片埋入式印刷電路板、利用印刷電路板之半導體封裝與晶片埋入式印刷電路板之製造方法,此晶片埋入式印刷電路板係有效地消散由埋入於電路板中之晶片所產生的熱。
根據本發明之一實施例,提供晶片埋入式印刷電路板包括:基底基材,包括預定的電路圖案形成於其中;電子元件,電性連接於電路圖案並埋入基底基材中,使得電子元件之一表面曝露於基底基材之一上表面;以及散熱體,設置於電子元件之一曝露表面上,以消散由電子元件所產生的熱至外部。
基底基材可更包括導孔結構,此導孔結構形成於基底基材之中並連接電路圖案,且基底基材更包括球型焊墊,此球型焊墊形成於基底基材之上表面上,且連接於導孔結構,並作為另外的印刷電路板或半導體封裝之電性連接。
散熱體可由具有優異的導熱性與導電性之材料所製成。
可使用銅、鋁、或其合金作為散熱體之材料。
散熱體可由具有優異的散熱性質之金屬(例如鋁)所組成,且球型焊墊可由與散熱體不同之金屬(例如銅、金、鉑、或類似者)所組成,並具有優異的導電性。
散熱體可由鋁所組成,且球型焊墊可由銅、金、鉑之任一金屬所組成。
基底基材可更包括電路保護絕緣材料,此電路保護絕緣材料形成於電路圖案之間,並曝露於基底基材上與設置有散熱體之一表面相對的表面。
可使用抗焊劑作為電路保護絕緣材料。
根據本發明之另一實施例,使用晶片埋入式印刷電路板以提供半導體封裝,此半導體封裝包括:下半導體封裝,設置於具有堆疊式封裝層疊結構之半導體封裝之下部分中以作為基底;且上半導體封裝堆疊於下半導體封裝之上,以與下半導體封裝一起建構具有堆疊式封裝層疊結構之整體的單積體半導體封裝,其中下半導體封裝包括基底基材,此基底基材包括預定電路圖案形成於其中;電子元件電性連接於電路圖案且埋入於基底基材之中,使得電子元件之一表面曝露於基底基材之上表面;以及散熱體設置於電子元件之曝露表面上,以消散由電子元件所產生的熱至外部。
基底基材可更包括導孔結構,此導孔結構形成於基底基材之中並連接電路圖案,且基底基材更包括球型焊墊,此球型焊墊形成於基底基材之上表面上,且連接於導孔結構,並作為另外的印刷電路板或半導體封裝之電性連接。
散熱體可由具有優異的導熱性與導電性之材料所組成。
可使用銅、鋁、或其合金作為散熱體之材料。
散熱體可由具有優異的散熱性質之金屬(如鋁)所組成,且球型焊墊可由與散熱體不同之金屬(如銅、金、鉑、或其相似者)所組成,並具有優異的導電性。
散熱體可由鋁所組成,且球型焊墊可由銅、金、和鉑其中之任一金屬所組成。
基底基材可更包括電路保護絕緣材料,此電路保護絕緣材料形成於電路圖案之間,並曝露於基底基材上與設置有散熱體之表面相對的表面。
可使用抗焊劑作為電路保護絕緣材料。
根據本發明之另一實施例,提供製造晶片埋入式印刷電路板之方法,此製造方法包括:將電子元件結合至散熱體之一表面;在散熱體之一表面形成絕緣層,以埋入電子元件;形成電路圖案,電路圖案在絕緣層中電性連接電子元件;以及蝕刻散熱體以形成接觸於電子元件之散熱圖案。
形成絕緣層與電路圖案之步驟可執行複數次。
製造方法可更包括:形成球型焊墊,此球型焊墊電性連接於絕緣層上的電路圖案之至少一部分。
當散熱圖案形成時,可同時形成球型焊墊。
根據本發明之另一實施例,提供製造晶片埋入式印刷電路板之方法,包括:製備基底基材,此基底基材具有預定電路圖案形成於其中;部分移除基底基材之上部分以形成凹槽,經 由凹槽曝露電路圖案之一部分;將電子元件***於凹槽中,使得電子元件電性連接於電路圖案;在基底基材之上表面之上以及電子元件之曝露表面之上形成散熱體;且在電子元件之曝露表面上蝕刻散熱體以形成散熱圖案。
方法可更包括:形成球型焊墊,球型焊墊電性連接於基底基材上之電路圖案的至少一部分。
當形成散熱圖案時,同時形成球型焊墊。
110、310‧‧‧上半導體封裝
111、121、311‧‧‧基材
112、122‧‧‧電子元件
113、123‧‧‧封裝材料
120、320‧‧‧下半導體封裝
301‧‧‧散熱體
301p‧‧‧球型焊墊
302、312‧‧‧電子元件
303‧‧‧基底基材
303h‧‧‧導孔
303c‧‧‧凹槽
304‧‧‧電路圖案
305‧‧‧電路保護絕緣材料
313‧‧‧封裝體
第1圖繪示根據先前技術之具有堆疊式封裝層疊結構之半導體封裝之一實驗例的示意圖。
第2圖繪示根據本發明之一實施例之晶片埋入式印刷電路板之結構的示意圖。
第3圖繪示根據本發明之一實施例之使用晶片埋入式印刷電路板之半導體封裝之結構的示意圖。
第4圖繪示根據本發明之一實施例之製造晶片埋入式印刷電路板之方法之半導體封裝之製程流程圖。
第5A圖至第5K圖依序地繪示根據本發明之一實施例之依據製造晶片埋入式印刷電路板之方法之印刷電路板之製程示意圖。
第6圖繪示根據本發明之另一實施例之製造晶片埋入式印刷電路板之方法之製程流程圖。
第7A圖至第7K圖依序地繪示根據本發明之另一實施例之依據製造晶片埋入式印刷電路板之方法之製造印刷電路板之製 程示意圖。
本說明書和權利要求中所使用之術語和用語不應被解釋為一般或字典的含義,為了描述自己發明的最佳模式,基於本發明人能夠適當地定義術語概念的原則,而應該被理解為達成本發明的技術理念之意義與概念。
整篇說明書當中,除非有相反之明確描述,用語「包括(comprise)」與其變化應被理解為意指包括所述元件,而非排除其他元件。此外,本說明書所述之術語「模組」、與「單元」意指處理至少一功能與操作之單元,並可藉由硬體元件或軟體元件以及其之結合而實行。
本發明之實施例將參照附圖做詳細地描述。
第2圖係繪示根據本發明之一實施例之晶片埋入式印刷電路板之結構。
參閱第2圖,根據本發明之一實施例之晶片埋入式印刷電路板係包括基底基材303、電子元件302與散熱體301。
基底基材303包括在其中之預定的電路圖案304。基底基材303可具有單層結構或多層結構。
電子元件302可電性連接於電路圖案304,且可埋入基底基材303中,如此電子元件302之一表面係從基底基材303之上表面曝露出來。此處,電子元件302可以是半導體晶片、積體電路晶片或相似者。
散熱體301可設置於電子元件302所曝露出之表面,且消散由電子元件302所產生的熱至外部。
此處,基底基材303可更包括導孔結構(導孔結構係整體地連接於電路圖案304,故並沒有標示符號),導孔結構連接於電路圖案304,且基底基材303更包括球型焊墊301p,其形成於基底基材303之上表面之上並連接於導孔結構,且用以與另外的印刷電路板或半導體封裝電性連接。
並且,散熱體301可由具有優異的導熱性與導電性之材料所製成。
此處,可使用銅(Cu)、鋁(Al)、或其合金(alloy)作為散熱體301之材料。
並且,散熱體301可由具有優異的散熱性質之金屬(例如鋁)所製成,且球型焊墊301p可由金屬(例如銅、金、鉑、或相似者)所組成,此金屬不同於散熱體301之金屬,且具有優異的導電性。
此處,散熱體301可由鋁所組成,且球型焊墊301p可由銅、金、和鉑其中之任一金屬所組成。
並且,基底基材303可更包括電路保護絕緣材料(circuit protecting insulating material)305形成於電路圖案304之間,電路保護絕緣材料305曝露於基底基材303之一表面,此表面相對於基底基材303之上設置有散熱體301之表面。
此處,可利用抗焊劑(solder resist)作為電路保護絕 緣材料305。
第3圖係繪示根據本發明之一實施例之使用晶片埋入式印刷電路板之半導體封裝結構之示意圖。
參閱第3圖,根據本發明之一實施例之使用晶片埋入式印刷電路板之半導體封裝,包括下半導體封裝320與上半導體封裝310。
下半導體封裝320係設置於半導體封裝之下部分中作為基底,其中半導體封裝具有堆疊式封裝層疊結構。
上半導體封裝310係堆疊於下半導體封裝320之上,以與下半導體封裝320一同建構具有堆疊式封裝層疊結構之整體的積體半導體封裝(integrated semiconductor package)。
此處,下半導體封裝320包括基底基材303、電子元件302以及散熱體301,基底基材303包括預定電路圖案304形成於其中,電子元件302電性連接於電路圖案304且埋入基底基材303之中,如此電子元件302之一表面係曝露於基底基材303之上表面,散熱體301設置於曝露電子元件302的表面上,以消散由電子元件302所產生的熱至外部。
此處,基底基材303可更包括導孔結構(導孔結構係整體地連接於電路圖案304,但並未標示符號),連接於電路圖案304,且基底基材303更包括球型焊墊301p形成於基底基材303之上表面並連接於導孔結構,且作為另外的印刷電路板或半導體封裝之電性連結。
並且,散熱體301可由具優異的導熱性與導電性之材料製成。
此處,可利用銅、鋁、或其合金作為散熱體301之材料。
而且,散熱體301可由具有優異的散熱性質之金屬(例如鋁)製成,且球型焊墊301p可由金屬(例如銅、金、鉑、或相似者)所製成,此金屬不同於散熱體301所使用之金屬,且具有優異的導電性。
此處,散熱體301可由鋁所製成,且球型焊墊301p可由銅、金、和鉑其中之任一金屬所製成。
並且,基底基材303可更包括電路保護絕緣材料305形成於電路圖案304之間,電路保護絕緣材料305曝露於基底基材303之一表面,此表面係相對於基底基材303上方設置有散熱體301之表面。
此處,可利用抗焊劑作為電路保護絕緣材料305。
在第3圖中,分別地,標號311表示基材,標號312表示電子元件,以及標號313表示封裝體(molding member)。
在下文中,將描述根據本發明之一實施例的製造晶片埋入式印刷電路板之製程。
第4圖係為根據本發明之一實施例,繪示製造晶片埋入式印刷電路板之製程的流程圖。第5A圖至第5K圖係根據本發明之一實施例,依序地繪示依據晶片埋入式印刷電路板製造方 法之製程的示意圖。
參閱第4圖以及第5A圖至第5K圖,根據本發明之一實施例之晶片埋入式印刷電路板的製造方法,首先,將電子元件302結合於散熱體301之一表面(步驟S401、第5A圖、和第5B圖)。此處,為了結合電子元件302,可使用黏著劑(adhesive)、樹脂(resin)、或相似者。
當完成電子元件302之結合時,先將絕緣材料塗佈於結合電子元件302的散熱體301,以形成絕緣層303(此處,在基材製造完成之後,絕緣層在製造過程中形成基底基材,因此絕緣層與基底基材標示為相同標號303),如此電子元件302被埋入(buried),且此後在絕緣層303之中形成導孔303h,而使得電子元件302與散熱體301經由導孔而曝露(步驟S402、第5C圖)。
爾後,將導電材料填充於導孔303h,且形成電性連接於導孔303h(例如電性連接於電子元件302)之第一電路圖案304(步驟S403、第5D圖)。
此後,形成絕緣層303、形成導孔303h與填充導孔並形成電路圖案304之步驟係重複地以堆疊之方式執行(步驟S404、第5E圖至第5J圖)。
換言之,如第5E圖所繪示,第二次地將絕緣材料塗佈於絕緣層303與形成於其上之第一電路圖案304,以堆疊之方式形成絕緣層303。並且如第5F圖所繪示,在絕緣層303之中形成導孔303h(由於是相同之絕緣層故以相同之標號表示),而使 得第一電路圖案304經由導孔而曝露。
此後,如第5G圖中所繪示,在導孔303h中填充導電材料,並同時形成第二電路圖案304(由於係與第一電路圖案連接為一電路圖案,故以相同標號表示)。
此後,如第5H圖所示,第三次地將絕緣材料塗佈於絕緣層303,與包括形成於其中之第二電路圖案304,以堆疊之形式形成絕緣層303,使得第二電路圖案埋入其中。並且此後,如第5I圖中所繪示,在堆疊的絕緣層303中形成導孔303h,而經由導孔303h曝露出第二電路圖案304。
此後,如第5J圖所示,將導電材料塗佈於導孔303h,並同時形成第三電路圖案304。
此處,根據製造基材之說明,在本發明之一實施例中係重複地執行形成絕緣層、形成導孔與填充導孔且形成電路圖案之製程步驟。為了方便起見,假定重複地執行上述製程三次。
當完成第三電路圖案304,如第5K圖中所繪示,蝕刻散熱體301,以形成散熱圖案(例如:散熱體301直接與電子元件302接觸的部分)對應於電子元件302與導孔303h,以及形成球型焊墊301p(步驟S405)。此處,若散熱圖案與球型焊墊301p由相同材料所製成,則同時地圖案化散熱圖案與球型焊墊301p,若散熱圖案與球型焊墊301p由不同的材料所製成,則球型焊墊301p係與散熱圖案分開圖案化。
此處,較佳地,方法可更包括一步驟(S406),使用 電路保護絕緣材料305於絕緣層303曝露的表面,以保護電路圖案304。此處,可利用抗焊劑作為電路保護絕緣材料305。
此處,塗佈電路保護絕緣材料305之製程以及形成散熱圖案與球型焊墊301p之製程可同時執行,或者可先執行使用電路保護絕緣材料305之製程。
並且,可使用熱固性樹脂(thermosetting resin)作為用於形成絕緣層303之絕緣材料。
此處,熱固性樹脂包括環氧樹脂(epoxy resin)、氨基樹脂(amino resin)、酚樹脂(phenol resin)、尿素樹脂(urea resin)、三聚氰胺樹脂(melamine resin)、不飽和聚酯樹脂(unsaturated polyester resin)、聚氨酯樹脂(polyurethane resin)、聚醯亞胺樹脂(polyimide resin)、或類似者。
並且,可使用乾蝕刻(dry etching)形成導孔303h。
此處,可使用準分子雷測(excimer laser)或基於二氧化碳雷射之製程方法進行乾蝕刻。
並且,可使用金、鋁、銅、或其相似者作為導電材料,以用於填充導孔303h並形成電路圖案304。
並且,為了以導電材料填充導孔303h並形成電路圖案304,可使用電解電鍍法(electrolytic plating method)與利用光罩(mask)之光微影技術(photolithography)。
並且,可使用具有優異的導熱性與導電性之材料,以形成散熱體301。
此處,可利用銅、鋁、或其合金作為散熱體301之材料。
並且,散熱體301可利用具有優異的散熱性質之金屬(例如鋁)所製成,且球型焊墊301p可由金屬(例如銅、金、鉑、或類似者)所製成,此金屬不同於散熱體301之金屬,並具有優異的導電性。
在此例中,散熱體301可由鋁所製成,且球型焊墊301p可由銅、金、和鉑其中之任一金屬所製成。
第6圖係為根據本發明之另一實施例,繪示製造晶片埋入式印刷電路板之製程的流程圖。第7A圖至第7K圖係根據本發明之另一實施例,依序地繪示依據晶片埋入式印刷電路板製造方法之製程的示意圖。
參閱第6圖,根據本發明另一實施例之晶片埋入式印刷電路板的製造方法,首先,製備基底基材303(在製造基材之製程中對應於絕緣層303,故與絕緣層303標示為相同標號)基底基材303具有形成於其中之預定電路圖案304。此處,製備基底基材303與形成於其中之預定電路圖案304之製程將參照第7A圖至第7H圖進行詳細地描述。
首先,形成具有預定絕緣材料的第一絕緣層303,且形成第一導孔303h於第一絕緣層303中(步驟S601)。
接著,如第7B圖中所示,以導電材料填充導孔303h,且同時在絕緣層303之表面上形成電性連接於導孔之第一 電路圖案304(步驟S602)。
此後,形成絕緣層303、形成導孔303h與填充導孔並形成電路圖案304之步驟係以堆疊之方式重複地執行多次(步驟S603,第7C圖至第7H圖)。
換言之,如第7C圖所繪示,第二次地將絕緣材料施用於絕緣層303與形成於其上之第一電路圖案304,以堆疊之方式形成絕緣層303。並且如第7D圖所繪示,在絕緣層303之中形成導孔303h(由於是相同之絕緣層故以相同之標號表示),而使得第一電路圖案304經由導孔而曝露。
此後,如第7E圖中所繪示,在導孔303h中填充導電材料,並同時形成第二電路圖案304(由於係與第一電路圖案連接為一電路圖案,故以相同標號表示)。
此後,如第7F圖所示,第三次地將絕緣材料施用於絕緣層303與包括形成於其中之第二電路圖案304,以堆疊之形式形成絕緣層303,使得第二電路圖案304埋入其中。並且此後,如第7G圖中所繪示,在堆疊的絕緣層303中形成導孔303h,而經由導孔曝露出第二電路圖案304。
此後,如第7H圖所示,將導電材料填充於導孔303h,並同時地形成第三電路圖案304。
此處,如上述之案例(第5A圖至第5K圖),根據製造基材之說明,在本發明之實施例中係將形成絕緣層、形成導孔、與填充導孔且形成電路圖案之製程步驟重複地執行多次。為 了方便起見,假定重複地執行上述製程三次。
當完成第三電路圖案304之形成,部分移除基底基材303之上部分,以形成凹槽而曝露出電路圖案304之一部分。換言之,如第7I圖中所示,具有預定尺寸之凹槽303c係形成於絕緣層303之一表面中,使電子元件可***其中(步驟S604)。
此後,如第7J圖中所示,在凹槽303c中放置電子元件302,使得電子元件302電性連接於電路圖案304,以及此後,在絕緣層303之整個表面上形成散熱體301(例如,在基底基材303之上表面以及電子元件302曝露之表面之上)(步驟S605)。
此後,如第7K圖中所示,蝕刻散熱體301,以形成散熱圖案(例如:散熱體301直接與電子元件302接觸的部分)對應於電子元件302與導孔303h,以及形成球型焊墊301p(步驟S606)。此處,若散熱圖案與球型焊墊301p由相同材料所製成,則同時地圖案化散熱圖案與球型焊墊301p,若散熱圖案與球型焊墊301p由不同的材料所製成,則球型焊墊301p係與散熱圖案分開圖案化。
此處,較佳地,方法可更包括一步驟(S607),使用電路保護絕緣材料305於絕緣層303曝露的表面,以保護電路圖案304。
此處,可利用抗焊劑作為電路保護絕緣材料305。
並且,可使用熱固性樹脂作為用於形成絕緣層303之絕緣材料。
此處,熱固性樹脂包括環氧樹脂、氨基樹脂、酚樹脂、尿素樹脂、三聚氰胺樹脂、不飽和聚酯樹脂、聚氨酯樹脂、聚醯亞胺樹脂、或類似者。
並且,可使用乾蝕刻形成導孔303h。
此處,可使用準分子雷測或基於二氧化碳雷射之製程方法進行乾蝕刻。
並且,可使用金、鋁、銅、或其相似者作為導電材料,以用於填充導孔303h並形成電路圖案304。
並且,為了以導電材料填充導孔303h並形成電路圖案304,可使用電解電鍍法與利用光罩之光微影技術。
並且,可使用具有優異的導熱性與導電性之材料,以形成散熱體301。
此處,可利用銅、鋁、或其合金作為散熱體301之材料。
並且,散熱體301可利用具有優異的散熱性質之金屬(例如鋁)所製成,且球型焊墊301p可由金屬(例如銅、金、鉑、或類似者)所製成,該金屬不同於散熱體301之金屬,並具有優異的導電性。
在此例中,散熱體301可由鋁所製成,且球型焊墊301p可由銅、金、和鉑其中之任一金屬所製成。
根據本發明之實施例,在印刷電路板與半導體封裝之案例中,由於電子元件係埋入於印刷電路板中,使得電子元件 之一表面曝露於印刷電路板之外,以及設置散熱體,使散熱體直接接觸於埋入式電子元件之曝露表面,以有效地消散由電子元件產生的熱至外部。
並且,由於使用具有前述結構之半導體埋入式印刷電路板作為下半導體封裝,且於下半導體封裝之上堆疊上半導體封裝,以形成整體的單積體半導體封裝(integrated single semiconductor package)、可製造具有優異的散熱功能之半導體封裝,以增加產品之可靠度。
雖然已揭露本發明之實施例以說明用途,本發明所屬技術領域中之通常知識者,在不脫離所附之申請專利範圍中所揭露的本發明之精神和範圍內,當可作各種之修改、添加與替換。於是,該些修改、添加與替換應屬於本發明之範疇內。

Claims (13)

  1. 一種晶片埋入式印刷電路板,包括:一基底基材,包括預定的複數個電路圖案形成於其中;一電子元件,電性連接於該些電路圖案,且埋入該基底基材之中,使得該電子元件之一表面係曝露於該基底基材之一上表面;一散熱體,設置於該電子元件之一曝露表面上;以及複數個球型焊墊,形成於該基底基材之該上表面,其中該基底基材之該上表面是該晶片埋入式印刷電路板的一最外層,其中該散熱體是形成為在該電子元件之該曝露表面上延伸至該基底基材之該上表面,使得該散熱體之下表面接觸於該基底基材之該上表面,且該散熱體以及該些球型焊墊是形成在相同的高度上,如此使得該散熱體之一側表面係透過該些球型焊墊之間之間隙中曝露出。
  2. 如申請專利範圍第1項所述之晶片埋入式印刷電路板,其中該基底基材更具有一導孔結構,該導孔結構形成於該基底基材之中以相互連接該些電路圖案,且其中該導孔結構係連接於該些球型焊墊。
  3. 如申請專利範圍第1項所述之晶片埋入式印刷電路板,其中該散熱體係由具有優異的導熱性及導電性之材料所組成。
  4. 如申請專利範圍第3項所述之晶片埋入式印刷電路板,其中該散熱體係由銅、鋁、或其合金所組成。
  5. 如申請專利範圍第2項所述之晶片埋入式印刷電路板,其中該散熱體係由具有優異的散熱性質之金屬所組成,且該些球型焊墊係由與該散熱體不同之金屬所組成,並具有優異的導電性。
  6. 如申請專利範圍第5項所述之晶片埋入式印刷電路板,其中該散熱體係由鋁所組成,該些球型焊墊係由銅、金、鉑其中之任一金屬所組成。
  7. 如申請專利範圍第1項所述之晶片埋入式印刷電路板,其中該基底基材更高括一電路保護絕緣材料,該電路保護絕緣材料形成於該些電路圖案之間,並曝露於該基底基材上與設置有該散熱體之一表面相對的表面。
  8. 如申請專利範圍第7項所述之晶片埋入式印刷電路板,其中該電路保護絕緣材料係為抗焊劑(solder resist)。
  9. 一種晶片埋入式印刷電路板之製造方法,該製造方法包括:將一電子元件結合至一散熱體之一表面;形成一絕緣層於該散熱體之該表面上,以埋入該電子元件;形成複數個電路圖案,該些電路圖案在該絕緣層之中電性連接該電子元件;蝕刻該散熱體,以形成接觸於該電子元件之一散熱圖案;以及形成複數個球型焊墊於該絕緣層上,使得該些球型焊墊連接於至少一些的該些電路圖案,其中該絕緣層之一上表面是該晶片埋入式印刷電路板的一最外層,其中該散熱體是形成為在該電子元件之一接觸表面上延伸至該絕緣層之該上表面,使得該散熱體之下表面接觸於該絕緣層之該上表面,且該散熱體以及該些球型焊墊是形成在相同的高度上,如此使得該散熱體之一側表面係透過該些球型焊墊之間之間隙中曝露出。
  10. 如申請專利範圍第9項所述之製造方法,其中形成該絕緣層與該些電路圖案之步驟係執行複數次。
  11. 如申請專利範圍第9項所述之製造方法,其中當該散熱圖案形成時,同時形成該些球型焊墊。
  12. 一種晶片埋入式印刷電路板之製造方法,該製造方法包括:製備一基底基材,該基底基材具有預定的複數個電路圖案形成於其中;部分移除該基底基材之一上部分,以形成一凹槽,經由該凹槽曝露該些電路圖案之一部分;將一電子元件***該凹槽中,使得該電子元件電性連接於該些電路圖案;形成一散熱體於該基底基材之一上表面上與該電子元件之一曝露表面上;蝕刻該散熱體,以在該電子元件之該曝露表面之上形成一散熱圖案;以及形成複數個球型焊墊於該基底基材上,使得該些球型焊墊連接於至少一些的該些電路圖案,其中該基底基材之該上表面是該晶片埋入式印刷電路板的一最外層,其中該散熱體是形成為在該電子元件之該曝露表面上延伸至該基底基材之該上表面,使得該散熱體之下表面接觸於該基底基材之該上表面,且該散熱體以及該些球型焊墊是形成在相同的高度上,如此使得該散熱體之一側表面係透過該些球型焊墊之間之間隙中曝露出。
  13. 如申請專利範圍第12項所述之製造方法,其中當形成該散熱圖案時,同時形成該些球型焊墊。
TW106124279A 2012-12-11 2013-10-24 晶片埋入式印刷電路板及應用印刷電路板之半導體封裝及其製造方法 TWI677062B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2012-0143615 2012-12-11
KR1020120143615A KR102107038B1 (ko) 2012-12-11 2012-12-11 칩 내장형 인쇄회로기판과 그를 이용한 반도체 패키지 및 칩 내장형 인쇄회로기판의 제조방법

Publications (2)

Publication Number Publication Date
TW201735293A TW201735293A (zh) 2017-10-01
TWI677062B true TWI677062B (zh) 2019-11-11

Family

ID=50880065

Family Applications (2)

Application Number Title Priority Date Filing Date
TW106124279A TWI677062B (zh) 2012-12-11 2013-10-24 晶片埋入式印刷電路板及應用印刷電路板之半導體封裝及其製造方法
TW102138387A TWI602270B (zh) 2012-12-11 2013-10-24 晶片埋入式印刷電路板及應用印刷電路板之半導體封裝及其製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW102138387A TWI602270B (zh) 2012-12-11 2013-10-24 晶片埋入式印刷電路板及應用印刷電路板之半導體封裝及其製造方法

Country Status (4)

Country Link
US (1) US9392698B2 (zh)
JP (2) JP2014116602A (zh)
KR (1) KR102107038B1 (zh)
TW (2) TWI677062B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11901285B2 (en) 2020-05-29 2024-02-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Microelectronic arrangement and method for manufacturing the same

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102016475B1 (ko) * 2014-10-21 2019-09-02 삼성전기주식회사 반도체 패키지, 반도체 패키지의 제조 방법 및 이를 이용한 적층형 패키지
SG11201704256QA (en) * 2014-12-23 2017-07-28 Intel Corp Integrated package design with wire leads for package-on-package product
KR102265243B1 (ko) * 2015-01-08 2021-06-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP6501638B2 (ja) * 2015-06-11 2019-04-17 オムロンオートモーティブエレクトロニクス株式会社 電子装置
KR101709468B1 (ko) * 2015-06-19 2017-03-09 주식회사 심텍 Pop 구조용 인쇄회로기판, 그 제조 방법 및 이를 이용하는 소자 패키지
KR102479999B1 (ko) 2015-09-11 2022-12-22 삼성전자주식회사 패키지 기판
CN106971993B (zh) * 2016-01-14 2021-10-15 三星电子株式会社 半导体封装件
KR102595276B1 (ko) * 2016-01-14 2023-10-31 삼성전자주식회사 반도체 패키지
US9911700B2 (en) * 2016-01-26 2018-03-06 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Embedded packages
JP6764666B2 (ja) * 2016-03-18 2020-10-07 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
JP6791352B2 (ja) * 2017-03-14 2020-11-25 株式会社村田製作所 回路モジュールおよびその製造方法
KR102040493B1 (ko) * 2017-05-31 2019-11-05 (주)제이엠씨 인쇄회로기판용 방열장치 및 이의 제조방법
US10347574B2 (en) * 2017-09-28 2019-07-09 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packages
US10573618B1 (en) * 2018-07-31 2020-02-25 Delta Electronics, Inc. Package structures and methods for fabricating the same
KR20200055415A (ko) 2018-11-13 2020-05-21 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 패키지 구조물
KR102589684B1 (ko) 2018-12-14 2023-10-17 삼성전자주식회사 반도체 패키지
KR20210097855A (ko) 2020-01-30 2021-08-10 삼성전자주식회사 금속 베이스 배선 기판 및 전자소자 모듈
JP7012776B2 (ja) 2020-04-28 2022-01-28 レノボ・シンガポール・プライベート・リミテッド 熱輸送装置および電子機器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200627561A (en) * 2005-01-19 2006-08-01 Via Tech Inc Chip package
TW200742521A (en) * 2005-10-27 2007-11-01 Shinko Electric Ind Co Electronic-part built-in substrate and manufacturing method therefor
TW201208016A (en) * 2010-06-08 2012-02-16 Freescale Semiconductor Inc Method of assembling semiconductor device with heat spreader
TW201216426A (en) * 2010-10-06 2012-04-16 Siliconware Precision Industries Co Ltd Package of embedded chip and manufacturing method thereof
TW201234542A (en) * 2010-11-17 2012-08-16 Samsung Electronics Co Ltd Semiconductor package and method of forming the same

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05259614A (ja) * 1992-03-12 1993-10-08 Hitachi Chem Co Ltd プリント配線板の樹脂埋め法
JPH10135386A (ja) * 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd 半導体ベアチップの製造方法
JP2003060523A (ja) * 2001-08-09 2003-02-28 Tdk Corp 無線通信モジュール
JP3910045B2 (ja) * 2001-11-05 2007-04-25 シャープ株式会社 電子部品内装配線板の製造方法
TW546800B (en) * 2002-06-27 2003-08-11 Via Tech Inc Integrated moduled board embedded with IC chip and passive device and its manufacturing method
JP2004335641A (ja) * 2003-05-06 2004-11-25 Canon Inc 半導体素子内蔵基板の製造方法
DE10340438B4 (de) * 2003-09-02 2005-08-04 Epcos Ag Sendemodul mit verbesserter Wärmeabführung
JP4271590B2 (ja) * 2004-01-20 2009-06-03 新光電気工業株式会社 半導体装置及びその製造方法
JP2006165175A (ja) * 2004-12-06 2006-06-22 Alps Electric Co Ltd 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法
JP2006269594A (ja) * 2005-03-23 2006-10-05 Cmk Corp 半導体装置及びその製造方法
US8546929B2 (en) * 2006-04-19 2013-10-01 Stats Chippac Ltd. Embedded integrated circuit package-on-package system
JP2008124247A (ja) * 2006-11-13 2008-05-29 Toppan Printing Co Ltd 部品内蔵基板及びその製造方法
KR100865125B1 (ko) * 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
KR100965339B1 (ko) * 2008-06-04 2010-06-22 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
US8138587B2 (en) * 2008-09-30 2012-03-20 Infineon Technologies Ag Device including two mounting surfaces
TWI417993B (zh) * 2009-02-04 2013-12-01 Unimicron Technology Corp 具凹穴結構的封裝基板、半導體封裝體及其製作方法
KR101058621B1 (ko) * 2009-07-23 2011-08-22 삼성전기주식회사 반도체 패키지 및 이의 제조 방법
US8263434B2 (en) * 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US8901724B2 (en) * 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8299595B2 (en) * 2010-03-18 2012-10-30 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
JP2011222553A (ja) 2010-04-02 2011-11-04 Denso Corp 半導体チップ内蔵配線基板及びその製造方法
KR101678539B1 (ko) * 2010-07-21 2016-11-23 삼성전자 주식회사 적층 패키지, 반도체 패키지 및 적층 패키지의 제조 방법
JP5548855B2 (ja) * 2010-09-27 2014-07-16 日本電気株式会社 配線基板及びその製造方法
KR20120039163A (ko) * 2010-10-15 2012-04-25 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US8745860B2 (en) * 2011-03-11 2014-06-10 Ibiden Co., Ltd. Method for manufacturing printed wiring board
TWI446464B (zh) * 2011-05-20 2014-07-21 Subtron Technology Co Ltd 封裝結構及其製作方法
US20120299173A1 (en) * 2011-05-26 2012-11-29 Futurewei Technologies, Inc. Thermally Enhanced Stacked Package and Method
US20130093073A1 (en) * 2011-10-17 2013-04-18 Mediatek Inc. High thermal performance 3d package on package structure
US20130147026A1 (en) * 2011-12-12 2013-06-13 Ati Technologies Ulc Heatsink interposer
KR20130082298A (ko) * 2012-01-11 2013-07-19 삼성전자주식회사 패키지 온 패키지 장치의 제조 방법 및 이에 의해 제조된 장치
US20140133105A1 (en) * 2012-11-09 2014-05-15 Nvidia Corporation Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200627561A (en) * 2005-01-19 2006-08-01 Via Tech Inc Chip package
TW200742521A (en) * 2005-10-27 2007-11-01 Shinko Electric Ind Co Electronic-part built-in substrate and manufacturing method therefor
TW201208016A (en) * 2010-06-08 2012-02-16 Freescale Semiconductor Inc Method of assembling semiconductor device with heat spreader
TW201216426A (en) * 2010-10-06 2012-04-16 Siliconware Precision Industries Co Ltd Package of embedded chip and manufacturing method thereof
TW201234542A (en) * 2010-11-17 2012-08-16 Samsung Electronics Co Ltd Semiconductor package and method of forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11901285B2 (en) 2020-05-29 2024-02-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Microelectronic arrangement and method for manufacturing the same

Also Published As

Publication number Publication date
KR102107038B1 (ko) 2020-05-07
JP2019024101A (ja) 2019-02-14
KR20140075357A (ko) 2014-06-19
TW201735293A (zh) 2017-10-01
TW201428908A (zh) 2014-07-16
US20140159222A1 (en) 2014-06-12
TWI602270B (zh) 2017-10-11
JP2014116602A (ja) 2014-06-26
US9392698B2 (en) 2016-07-12

Similar Documents

Publication Publication Date Title
TWI677062B (zh) 晶片埋入式印刷電路板及應用印刷電路板之半導體封裝及其製造方法
US7839649B2 (en) Circuit board structure having embedded semiconductor element and fabrication method thereof
KR101058621B1 (ko) 반도체 패키지 및 이의 제조 방법
TWI467726B (zh) 堆疊封裝結構
US8115316B2 (en) Packaging board, semiconductor module, and portable apparatus
KR20070045929A (ko) 전자 부품 내장 기판 및 그 제조 방법
US20170018505A1 (en) Wiring board with embedded component and integrated stiffener and method of making the same
JP4730426B2 (ja) 実装基板及び半導体モジュール
US8994168B2 (en) Semiconductor package including radiation plate
KR20070010915A (ko) 방열층을 갖는 배선기판 및 그를 이용한 반도체 패키지
US7714451B2 (en) Semiconductor package system with thermal die bonding
JP2010239126A5 (ja) パッケージ基板および半導体装置の製造方法
JP2019075578A (ja) 半導体パッケージ及びその製造方法
JP2010287870A (ja) プリント基板及びそれを含んだ半導体装置、並びにプリント基板の製造方法
TWI531283B (zh) 連接基板及層疊封裝結構
JP4494249B2 (ja) 半導体装置
JP2011119481A (ja) 半導体装置および半導体装置の製造方法
TW200933831A (en) Integrated circuit package and the method for fabricating thereof
JP4887170B2 (ja) 半導体装置の製造方法
TWI613771B (zh) 半導體封裝
TWI435667B (zh) 印刷電路板組件
KR101109214B1 (ko) 패키지 기판 및 그 제조방법
US20160163624A1 (en) Package structure
JP5069879B2 (ja) 回路装置
JP2005183879A (ja) 高放熱型プラスチックパッケージ