JP4878030B2 - エッチング処理されたリードフレームを用いる再分散型ハンダパッド - Google Patents
エッチング処理されたリードフレームを用いる再分散型ハンダパッド Download PDFInfo
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- JP4878030B2 JP4878030B2 JP2007533624A JP2007533624A JP4878030B2 JP 4878030 B2 JP4878030 B2 JP 4878030B2 JP 2007533624 A JP2007533624 A JP 2007533624A JP 2007533624 A JP2007533624 A JP 2007533624A JP 4878030 B2 JP4878030 B2 JP 4878030B2
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Description
12 導電クリップ
14 半導体デバイス
16 第1の電極
18 第2の電極
20 制御電極
22 導電リードフレーム部材
24 凹部
26 MOSFET
30 絶縁材
32 ソース電極
34 ゲート電極
36 接点
38 ソーライン
Claims (15)
- 半導体デバイスであって、
内部空間と、この内部空間へ通じる開口を囲むフランジとを有する導電クリップと、
前記内部空間内に配置され、電気的かつ機械的に、前記導電クリップ内部の下面に固定されている上面電極と、前記内部空間内に配置されている下面電極とを有する半導体ダイと、
前記半導体ダイの外周の少なくとも一部と、前記導電クリップの内部壁との間に配置されている内部空隙と、
前記内部空隙を充填し、かつ前記下面電極と同一平面上にある底面を有する絶縁部材と、
前記下面電極に固定され、前記絶縁部材の底表面の少なくとも一部上に延在する少なくとも1つの接点と
を備え、
前記接点は、前記下面電極に対して位置および大きさが再配分されている半導体デバイス。 - 前記下面電極と離間し、かつこれと同一平面上にある、前記ダイの底部の第2の下面電極と、
前記少なくとも1つの接点から側方に離間する第2の接点と
を更に有し、
前記第2の接点は、前記第2の下面電極に固定され、少なくとも前記絶縁部材の前記底面の第2の部分上に延在し、前記第2の下面電極に対して位置および大きさが再配分されている請求項1に記載の半導体デバイス。 - 前記下面電極は、メッキされた銅であり、前記接点は、ハンダ付け可能である請求項1に記載の半導体デバイス。
- 前記内部空間は、約150ミクロン未満の深さを有し、前記ダイは、前記深さと同等の厚さを有することにより、前記下面電極と前記フランジ底部は、同一平面上となっている請求項1に記載の半導体デバイス。
- 半導体パッケージを製造するためのプロセスであって、
導電リードフレーム部材内に、底部が前記部材の表面と平行な面内に存在する浅い開口を形成するステップと、
下面電極が前記部材の表面と同一平面上にあり、周囲が前記開口の包囲壁から離間される前記半導体ダイにおける上面電極を、前記開口の底部に導電的及び機械的に固定するステップと、
前記ダイの周囲と絶縁材による前記開口の壁の間の環状空隙を充填し、かつ、前記絶縁材の露出面を前記部材の表面とともに平坦化し、前記ダイの下面電極を露出させるステップと、
前記開口の反対側の前記導電部材の表面を薄化するステップと
を有するプロセス。 - 前記下面電極、及び前記開口に隣接する前記導電部材の前記表面を銅メッキするステップを更に有する請求項5に記載のプロセス。
- 前記下面電極に対して、前記絶縁材の底面上に重なるよう、接点を形成するステップを更に有し、
前記接点は、前記下面電極に対して位置および大きさが再配分されるように形成される請求項5に記載のプロセス。 - 前記複数の浅い開口は、前記導電部材内において、側方において相互に変位し、前記開口のそれぞれは、個別に半導体ダイを受容し、前記絶縁材で充填されることにより、同時に複数のダイ及びパッケージ組立体を形成し、その後、前記ダイ及びパッケージ組立体を個片化する請求項5に記載のプロセス。
- 半導体デバイスであって、
内部空間と、この内部空間へ通じる開口を囲むフランジとを有する導電クリップと、
前記内部空間内に配置され、機械的に前記導電クリップ内部の下面に固定されている上面と、前記内部空間内に配置されている下面とを有する半導体ダイと、
前記ダイの前記下面に固定されている少なくとも1つの下面電極と、
前記半導体ダイ外周の少なくとも一部と前記導電クリップの内部壁との間に配置されている内部空間と、
前記内部空間を充填し、前記下面電極と同一平面上にある底面を有する絶縁部材と、
前記下面電極の少なくとも1つに固定され、前記絶縁部材の前記底面の少なくとも一部上に延在する少なくとも1つの接点と
を備え、
前記少なくとも1つの接点は、少なくとも1つの前記下面電極に対して位置および大きさが再配分されている半導体デバイス。 - 前記下面電極から離間し、かつ前記下面電極と同一平面上にある、前記ダイの前記下面の第2の下面電極と、
前記少なくとも1つの接点から側方に離間する第2の接点と
を更に有し、
前記第2の接点は、前記第2の下面電極に固定され、前記絶縁部材の前記底面の第2の部分の上に少なくとも延在し、前記第2の下面電極に対して位置および大きさが再配分されている請求項9に記載の半導体デバイス。 - 前記ダイは、ラテラル導通型半導体デバイスである請求項9に記載の半導体デバイス。
- マルチチップ型半導体デバイスであって、
内部空間と、前記内部空間へ通じる開口を囲むフランジとを有する導電クリップと、
前記導電クリップの内部に配置され、相互接続する第1及び第2の半導体ダイであって、前記第1及び第2の半導体ダイはそれぞれ、前記内部空間内に配置される上面及び下面を有し、電気的かつ機械的に、前記導電クリップの前記内部空間の下面に固定されている上面電極を有する前記第1及び第2の半導体ダイと、
前記第1及び第2のダイの下面の1つに固定されている少なくとも1つの下面電極と、
前記第1及び第2の半導体ダイ外周の少なくとも一部と前記導電クリップの内部壁との間に配置されている内部空間と、
前記内部空間を充填し、前記少なくとも1つの下面電極と同一平面上にある底面を有する絶縁部材と、
前記少なくとも1つの下面電極に固定され、前記絶縁部材の前記底表面の少なくとも一部上に延在する少なくとも1つの接点と
を備え、
前記少なくとも1つの接点は、前記少なくとも1つの下面電極に対して位置および大きさが再配分されている半導体デバイス。 - 前記少なくとも1つの下面電極と離間しかつこれと同一平面上にある、前記第1及び第2のダイの1つの前記下面上の第2の下面電極と、
前記少なくとも1つの接点から側方に離間する第2の接点と
を更に有し、
前記第2の接点は、前記第2の下面電極に固定され、少なくとも前記絶縁部材の底面の第2の部分上に延在し、前記第2の下面電極に対して位置および大きさが再配分されている請求項12に記載の半導体デバイス。 - 前記第1の半導体ダイは、ラテラル導通型半導体デバイスであり、前記第2の半導体ダイは、前記第1のダイ用の制御デバイスである請求項12に記載の半導体デバイス。
- 前記少なくとも1つの接点の少なくとも一部の上に配置され、基板実装プロセス中に前記少なくとも1つの接点から、他の露出された接点へのハンダのブリッジングを防止するソルダーマスクを更に備える請求項12に記載の半導体デバイス。
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US11/231,690 US7235877B2 (en) | 2004-09-23 | 2005-09-21 | Redistributed solder pads using etched lead frame |
US11/231,690 | 2005-09-21 | ||
PCT/US2005/033958 WO2006034393A2 (en) | 2004-09-23 | 2005-09-22 | Redistributed solder pads using etched lead frame |
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