JP4874305B2 - Circuit board with built-in electric / electronic components and manufacturing method thereof - Google Patents

Circuit board with built-in electric / electronic components and manufacturing method thereof Download PDF

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JP4874305B2
JP4874305B2 JP2008188843A JP2008188843A JP4874305B2 JP 4874305 B2 JP4874305 B2 JP 4874305B2 JP 2008188843 A JP2008188843 A JP 2008188843A JP 2008188843 A JP2008188843 A JP 2008188843A JP 4874305 B2 JP4874305 B2 JP 4874305B2
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electronic component
thin layer
electric
conductive thin
built
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JP2010027917A (en
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圭男 今村
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Meiko Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Description

本発明は電子部品内蔵回路基板とその製造方法に関し、更に詳しくは、それを用いて製造した多層回路基板を従来に増して薄型にすることができる電気・電子部品内蔵回路基板とその製造方法に関する。   The present invention relates to a circuit board with a built-in electronic component and a method for manufacturing the same, and more particularly, to a circuit board with a built-in electric / electronic component that can be made thinner than conventional multilayer circuit boards manufactured using the circuit board. .

最近、各種の電気・電子機器の小型化、薄型化、軽量化、多機能化が急速に進んでいる。とくに、携帯電話、ノートパソコン、デジタルカメラなどの分野では、多機能化と並んで小型化、薄型化の要求が強い。また、伝送信号の高周波化、高速化が進んでいるのであるが、このことに伴って発生してくる信号ノイズの増大への対応策も強い要求の１つである。   Recently, various electric and electronic devices are rapidly becoming smaller, thinner, lighter, and multifunctional. In particular, in the fields of mobile phones, notebook computers, digital cameras, etc., there is a strong demand for downsizing and thinning along with multi-functionalization. In addition, the frequency and speed of transmission signals are increasing, and countermeasures against the increase in signal noise that accompanies this increase are one of the strong demands.

このような全体の動向に対し、これら電気・電子機器に組み込まれる回路基板として、従来は基板表面に実装されていた各種の電気・電子部品を基板の絶縁層である絶縁基材に内蔵した構造の回路基板や、それを複数積層して成る多層回路基板が注目を集めている。
このような部品内蔵の回路基板の場合、配線長が短くなってノイズ低減を実現することができ、また、基板に実装する部品点数が同じであるならば、完成した基板全体としては薄型化・小型化を実現することができるからである。 In response to these overall trends, the circuit board that is built into these electrical and electronic devices is a structure that incorporates various electrical and electronic components that were previously mounted on the surface of the board in an insulating substrate that is the insulating layer of the board. The circuit board and multilayer circuit boards formed by stacking a plurality of such circuit boards are attracting attention.
In the case of such a circuit board with a built-in component, the wiring length can be shortened to reduce noise, and if the number of parts mounted on the board is the same, the completed board as a whole can be made thinner and thinner. This is because downsizing can be realized.

従来、このような部品内蔵型の回路基板は、概ね、次のようにして製造されている。
まず、絶縁基材の両面に例えば銅箔が貼着されている両面銅張積層板を出発素材として用意する。次いで、銅箔にフォトリソグラフィーとエッチング技術を適用して、当該銅箔を所定パターンの導体回路に加工して、絶縁基材ａの両面にパッド部を含む導体回路ｂが配線されている図１６で示すようなコア基板Ａ0を製造する。 Conventionally, such component-embedded circuit boards are generally manufactured as follows.
First, a double-sided copper-clad laminate in which, for example, copper foil is stuck on both sides of an insulating base material is prepared as a starting material. Then, by applying the Fotori Soviet Photography and etching techniques to a copper foil, by processing the copper foil to the conductive circuit having a predetermined pattern, the conductor circuit b including a pad portion on both surfaces of the insulating base material a is wired FIG A core substrate A 0 as shown at 16 is manufactured.

そしてコア基板Ａ0の導体回路ｂの所定箇所に例えばはんだリフロー処理によって所望する電気・電子部品ｃを表面実装し、ついで例えば未硬化樹脂から成る絶縁基材ｄで電気・電子部品ｃを埋設して、図１７で示した部品内蔵の単位回路基板Ａ’にする。
そして、この回路基板Ａ’を用いて多層回路基板を製造する場合には、絶縁基材ｄの上に銅箔を貼着し、更に絶縁基材を硬化したのち、その銅箔を導体回路にして、以後、公知のビルドアップ工法を適用して単位回路基板を順次積層していけばよい（特許文献１を参照）。
特開２００４−３２７６２４号公報 Then, a desired electrical / electronic component c is surface-mounted by a solder reflow process, for example, on a predetermined portion of the conductor circuit b of the core substrate A 0 , and then the electrical / electronic component c is embedded with an insulating base material d made of uncured resin, for example. Thus, the unit circuit board A ′ with built-in components shown in FIG.
And when manufacturing a multilayer circuit board using this circuit board A ', after sticking copper foil on the insulating base material d, and also hardening | curing an insulating base material, the copper foil is made into a conductor circuit. Thereafter, the unit circuit boards may be sequentially stacked by applying a known build-up method (see Patent Document 1).
JP 2004-327624 A

上記したような従来構造の部品内蔵の回路基板を製造するに際しては、その最初の工程においてコア基板Ａｏを製造することが必要である。したがって、完成した部品内蔵回路基板の全体の厚みにおいては、部品を内蔵する層ではないコア基板Ａｏの絶縁基材ａの厚み相当分が必ず含まれてくる。そのため、コア基板Ａｏを使用する限り、完成した部品内蔵回路基板の全体の厚みにおいてこの厚み相当分を薄くすることはできない。   When manufacturing a circuit board with built-in components having the conventional structure as described above, it is necessary to manufacture the core substrate Ao in the first step. Therefore, the entire thickness of the completed component-embedded circuit board always includes a portion corresponding to the thickness of the insulating base material a of the core substrate Ao that is not a layer in which the component is built-in. Therefore, as long as the core substrate Ao is used, it is not possible to reduce the thickness equivalent to the total thickness of the completed component built-in circuit board.

また、従来の部品内蔵回路基板の製造時に用いるコア基板の絶縁基材における例えば絶縁樹脂は硬化が完了していて寸法変化を起こしにくい状態にあるが、しかしコア基板の上に配置される絶縁基材の絶縁樹脂は未硬化または半硬化の状態にあり、硬化が完了しているコア基板の絶縁基材と対比して、硬化の過程で大きな寸法変化を起こす状態にある。そのため、完成した部品内蔵回路基板においては、反りの発生頻度が多くなってくる。   In addition, for example, the insulating resin in the insulating base material of the core substrate used in the manufacture of the conventional circuit board with built-in components is in a state where the curing is completed and the dimensional change is difficult to occur, but the insulating substrate disposed on the core substrate is The insulating resin of the material is in an uncured or semi-cured state, and is in a state of causing a large dimensional change during the curing process as compared with the insulating base material of the core substrate that has been cured. Therefore, the frequency of occurrence of warpage increases in the completed component-embedded circuit board.

本発明は、図１６で示したコア基板Ａｏを使用して製造する従来の部品内蔵回路基板における上記した問題を解決し、従来のようなコア基板Ａｏを使用することなく製造することができ、したがってコア基板Ａｏにおける絶縁基板ａの厚み相当分が薄くなっており、また反りの発生が低減されている新規な構造の電気・電子部品内蔵回路基板とその製造方法の提供を目的とする。   The present invention solves the above-described problems in the conventional component built-in circuit board manufactured using the core substrate Ao shown in FIG. 16, and can be manufactured without using the conventional core substrate Ao. Accordingly, it is an object of the present invention to provide a circuit board with a built-in electric / electronic component having a novel structure in which a portion corresponding to the thickness of the insulating substrate a in the core substrate Ao is thin and the occurrence of warpage is reduced, and a manufacturing method thereof.

上記した目的を達成するために、本発明においては、絶縁基材と、前記絶縁基材の一方の面にソルダーレジスト層を介在させて形成された第１導体回路及び前記絶縁基材の一方の面とは反対側の他方の面に形成された第２導体回路と、前記絶縁基材の中に埋設され、前記一方の面側に前記第１導体回路と電気的に接続されるべき端子を有する電気・電子部品とを備え、前記ソルダーレジスト層は、前記電気・電子部品の端子を個別に前記第１導体回路に向けて露出させる孔を有し、前記孔に充填されたソルダーペーストによって形成され、前記端子と前記第１導体回路とを電気的に接続する接続導電体を更に含むことを特徴とする電気・電子部品内蔵回路基板が提供される。
また、本発明においては、請求項１に記載の電気・電子部品内蔵回路基板の製造方法であって、支持基材と、前記支持基材に積層され、前記第１導体回路となるべき導電薄層とを含む２層構造の板状体を準備する準備工程と、前記導電薄層の前記支持基材と接触する第１面とは反対側の第２面に、前記導電薄層に至る前記孔を有するソルダーレジスト層を形成する工程と、前記孔にソルダーペーストを充填し、前記導電薄層に電気的に接続されたペーストポストを形成する工程と、前記ペーストポスト上に前記電気・電子部品の前記端子を介して前記電気・電子部品を配設した後、前記ペーストポストの加熱溶融処理を経て、前記ペーストポストを前記端子と前記導電薄層とを電気的に接続する前記接続導電体に形成し、前記電気・電子部品を前記板状体の前記導電薄層上に実装する実装工程と、前記電気・電子部品が実装された前記導電薄層上に前記電気・電子部品を前記ソルダーレジスト層とともに埋設する前記絶縁基材を形成するとともに、前記絶縁基材の前記導電薄層とは反対側の面に前記第２導体回路となるべき導電材料の箔を配置する積層工程と、前記板状体から前記支持基材を剥離して前記導電薄層の第１面を表出させる剥離工程と、前記導電薄層および前記箔を所定パターンに加工して前記第１及び第２導体回路にそれぞれ形成する導体回路形成工程とを備えていることを特徴とする電気・電子部品内蔵回路基板の製造方法が提供される。 In order to achieve the above object, in the present invention, an insulating base material, a first conductor circuit formed by interposing a solder resist layer on one surface of the insulating base material, and one of the insulating base material A second conductor circuit formed on the other surface opposite to the surface, and a terminal embedded in the insulating base material and electrically connected to the first conductor circuit on the one surface side. The solder resist layer has a hole that exposes the terminal of the electric / electronic component individually toward the first conductor circuit, and is formed by a solder paste filled in the hole. And a circuit board with a built-in electric / electronic component , further comprising a connection conductor for electrically connecting the terminal and the first conductor circuit .
According to the present invention, there is also provided a method of manufacturing an electric / electronic component built-in circuit board according to claim 1 , comprising: a supporting base material; A preparatory step of preparing a plate-shaped body having a two-layer structure including a layer, and the second surface of the conductive thin layer opposite to the first surface that contacts the support base, the conductive thin layer reaching the conductive thin layer A step of forming a solder resist layer having holes, a step of filling the holes with a solder paste and forming a paste post electrically connected to the conductive thin layer, and the electric / electronic component on the paste post After the electrical / electronic component is disposed through the terminal, the paste post is heated and melted, and the paste post is electrically connected to the terminal and the conductive thin layer. Forming and electric / electronic parts A mounting step of mounting on the conductive thin layer of the plate-like member, said insulating substrate to embed the electric and electronic parts together with the solder resist layer in the electrical and electronic components implemented the conductive thin layer Forming and laminating a conductive material foil to be the second conductor circuit on the surface of the insulating base opposite to the conductive thin layer, and peeling the support base from the plate A peeling step of exposing the first surface of the conductive thin layer, and a conductor circuit forming step of processing the conductive thin layer and the foil into a predetermined pattern to form the first and second conductor circuits, respectively. A method of manufacturing a circuit board with built-in electric / electronic parts is provided.

そして、前記準備工程は、前記板状体に含まれる前記導電薄層として第１の銅箔を用いるとともに前記支持基材として前記第１の銅箔より厚さが厚い肉厚銅箔を用いることが好ましい。
また、前記積層工程は、前記導電材料の箔として第２の銅箔を用いることが好ましい。 And the said preparatory process uses the thick copper foil whose thickness is thicker than the said 1st copper foil as said support base material while using the 1st copper foil as said electroconductive thin layer contained in the said plate-shaped object. Is preferred.
Moreover, it is preferable that the said lamination process uses 2nd copper foil as foil of the said electrically-conductive material .

本発明の電気・電子部品内蔵回路基板は、電気・電子部品を内蔵する絶縁基材の上面と下面に当該部品と接続する所定パターンの導体回路が配線されていて、従来のコア基板のように部品を内蔵していない絶縁基材の上面（または下面）に、電気・電子部品を内蔵する絶縁基材が積層されている構造ではないので、従来に比べて、部品を内蔵していない絶縁基材の厚み相当分が薄くなっている。   The circuit board with built-in electric / electronic components of the present invention has a predetermined pattern of conductor circuits connected to the upper and lower surfaces of the insulating base material containing the electric / electronic components. Insulating base that does not contain components compared to the conventional structure because the insulating base that contains electrical and electronic components is not laminated on the upper surface (or lower surface) of the insulating base that does not contain components. The material equivalent to the thickness is thin.

したがって、本発明の電気・電子部品内蔵回路基板は、搭載する部品点数が同数であれば従来に比べて全体の厚みを薄くすることができ、また全体の厚みが同じであれば、搭載できる部品点数は従来に比べて多くすることができる。
また、内蔵されている電気・電子部品と導体回路との配線長が短いので、伝送信号の高周波化、高速化に対してもノイズ低減を実現することができる。 Therefore, the electric / electronic component built-in circuit board according to the present invention can be reduced in overall thickness as long as the number of components to be mounted is the same, and can be mounted if the overall thickness is the same. The score can be increased as compared with the conventional one.
In addition, since the wiring length between the built-in electrical / electronic component and the conductor circuit is short, noise reduction can be realized even when the transmission signal is increased in frequency and speed.

本発明の電気・電子部品内蔵回路基板の基本構造を図１と図２に示す。図１の基板Ａは、後述する工程１において、内蔵する部品の端子部と導体回路とを接続するための接続端子部を導電薄層に形成する際に後述する工程１Ａを実施したときに得られる基板であり、図２の基板Ｂは工程１Ｂを実施したときに得られる基板である。
図１の基板Ａは、絶縁層である１枚の絶縁基材１と、その下面１ａと上面１ｂにそれぞれ所定パターンで配線された導体回路２ａ，３ａと、絶縁基材１に内蔵されている電気・電子部品４とで構成され、絶縁基材１の厚み方向には更に導体回路２ａと導体回路３ａの導通をとるためのスルーホール５が形成されている。 The basic structure of the circuit board with built-in electric / electronic parts of the present invention is shown in FIGS. The substrate A shown in FIG. 1 is obtained when Step 1A described later is performed when forming a connection terminal portion for connecting a terminal portion of a built-in component and a conductor circuit in a conductive thin layer in Step 1 described later. The substrate B in FIG. 2 is a substrate obtained when step 1B is performed.
The substrate A of FIG. 1 is built in the insulating base material 1, a single insulating base material 1 that is an insulating layer, conductor circuits 2 a and 3 a wired in a predetermined pattern on the lower surface 1 a and the upper surface 1 b, respectively. A through-hole 5 is formed in the thickness direction of the insulating base material 1 to further connect the conductor circuit 2a and the conductor circuit 3a.

なお、スルーホール５は、ここに例えばめっき銅や導電性ペーストなどを充填して柱状導体の状態になっていてもよい。
ここで、部品４の例えばランドのような端子部４ａは、後述する工程１Ａで形成される導電性ペーストから成る接続端子部６ａに接続されることにより、導体回路２ａと電気的に接続されている。 The through hole 5 may be in the state of a columnar conductor by filling it with, for example, plated copper or conductive paste.
Here, the terminal portion 4a such as a land of the component 4 is electrically connected to the conductor circuit 2a by being connected to the connection terminal portion 6a made of a conductive paste formed in step 1A described later. Yes.

図２の基板Ｂの場合は、絶縁基材１の下面と導体回路２ａの間に、厚みが接続端子部６ｂの高さと等値のソルダーレジストの層７が介在し、また接続端子部６ｂがソルダーペーストから成ることを除いては、前記した基板Ａの場合と同じ構造になっている。すなわち、この基板Ｂでは、基板Ａにおける１枚の絶縁基材１が絶縁基材１とソルダーレジスト層７の積層体になっている。   In the case of the substrate B of FIG. 2, a solder resist layer 7 having a thickness equal to the height of the connection terminal portion 6b is interposed between the lower surface of the insulating base 1 and the conductor circuit 2a, and the connection terminal portion 6b is The structure is the same as that of the substrate A described above except that it is made of a solder paste. That is, in this substrate B, one insulating base material 1 on the substrate A is a laminate of the insulating base material 1 and the solder resist layer 7.

これらの基板Ａ，基板Ｂのいずれにおいて、製造に当たっては、図３で示す板状体２を出発素材とする。
板状体２は、導電材料から成る導電薄層２Ａとこの薄層２Ａよりも厚い支持部材２Ｂを例えば剥離可能に貼着して積層した２層構造になっている。導電薄層２Ａは最終的には基板Ａ，基板Ｂの導体回路２ａに加工されるので、導電材料であることを必須条件とするが、支持部材２Ｂの方は、導電薄層２Ａを支持するための支持材であって、必ずしも導電材料である必要はなく、例えば樹脂フィルムなどであってもよい。 In the production of either of these substrates A and B, the plate-like body 2 shown in FIG. 3 is used as a starting material.
The plate-like body 2 has a two-layer structure in which a conductive thin layer 2A made of a conductive material and a support member 2B thicker than the thin layer 2A are detachably attached and laminated, for example. Since the conductive thin layer 2A is finally processed into the conductor circuit 2a of the substrate A and the substrate B, it is an essential condition that it is a conductive material, but the support member 2B supports the conductive thin layer 2A. For example, a resin film or the like may be used.

このような板状体２としては、導電薄層２Ａが銅箔であり、支持部材２Ｂも銅箔（当て箔と呼ばれる）であるものが例えば古河サーキットフォイル社製のキャリア銅箔などとして市販されている。
工程１。この工程は、板状体２の導電薄層２Ａの上に、基板Ａ，基板Ｂにおいて、内蔵部品４の端子部４ａと導体回路２ａとの間を接続するための接続端子部６ａ，６ｂを形成する工程である。 As such a plate-like body 2, the conductive thin layer 2 </ b> A is a copper foil, and the support member 2 </ b> B is also a copper foil (referred to as a contact foil), which is commercially available, for example, as a carrier copper foil manufactured by Furukawa Circuit Foil. ing.
Step 1. In this process, on the conductive thin layer 2A of the plate-like body 2, the connection terminal portions 6a and 6b for connecting the terminal portion 4a of the built-in component 4 and the conductor circuit 2a on the substrate A and the substrate B are provided. It is a process of forming.

そして工程１としては後述する工程１Ａまたは工程１Ｂを実施することができ、工程１Ａを実施すれば最終的に図１で示した構造の基板Ａが製造され、工程１Ｂを実施すれば最終的に基板Ｂが製造される。
最初に工程１Ａを採用した場合の製造方法について説明する。
工程１Ａにおいては、板状体２の導電薄層２Ａの上面に導電性ペーストを用いたスクリーン印刷を行って、図４で示したように、所定の位置に導電性ペーストから成るパッド部を含む接続端子部６ａを印刷して中間体Ａ1を製造する。 Then, as step 1, step 1A or step 1B, which will be described later, can be carried out. If step 1A is carried out, substrate A having the structure shown in FIG. 1 is finally produced, and step 1B is carried out. Substrate B is manufactured.
First, a manufacturing method in the case of adopting step 1A will be described.
In step 1A, screen printing using a conductive paste is performed on the upper surface of the conductive thin layer 2A of the plate-like body 2 to include a pad portion made of the conductive paste at a predetermined position as shown in FIG. to produce intermediate a 1 by printing a connection terminal portion 6a.

このときに用いる導電性ペーストとしては、例えばＸＨ９６２６−７（商品名、ナミックス社製のはんだ代替用導電性接着剤）などをあげることができる。
ついで、中間体Ａ1は工程２に移送される。
工程２。この工程は、工程１で得られた中間体Ａ1の接続端子部に内蔵すべき電気・電子部品４を実装する工程である。 Examples of the conductive paste used at this time include XH9626-7 (trade name, conductive adhesive for solder replacement manufactured by NAMICS).
The intermediate A 1 is then transferred to step 2.
Step 2. This step is a step of mounting the electrical / electronic component 4 to be incorporated in the connection terminal portion of the intermediate A 1 obtained in the step 1.

工程１Ａによって製造された中間体Ａ1の場合、図５で示したように、導電薄層２Ａの上面に突設されている接続端子部６ａに電気・電子部品４の端子部４ａを重ね合わせたのち、電気・電子部品４を軽く押圧しながら加熱する。
導電性ペーストから成る接続端子部６ａが端子部４ａと接着し、同時に導電性ペーストが熱硬化することにより、端子部４ａが接続端子部６ａに固着され、ここに接続端子部６ａに電気・電子部品４が実装されている中間体Ａ2が得られる。 In the case of the intermediate A 1 manufactured by the process 1A, as shown in FIG. 5, the terminal portion 4a of the electric / electronic component 4 is superimposed on the connection terminal portion 6a protruding from the upper surface of the conductive thin layer 2A. After that, the electric / electronic component 4 is heated while being lightly pressed.
The connection terminal portion 6a made of a conductive paste is bonded to the terminal portion 4a, and at the same time, the conductive paste is thermally cured, whereby the terminal portion 4a is fixed to the connection terminal portion 6a, and the connection terminal portion 6a is connected to the electric / electronic device. An intermediate A 2 on which the component 4 is mounted is obtained.

この、中間体Ａ2では、薄層２Ａに突設して形成された接続端子部６ｂに電気・電子部品４が実装されているので、電気・電子部品４と導電薄層２Ａの間に接続端子部６ａの高さとほぼ等しい厚みの微少クリアランスが形成されている。
工程３。この工程は、工程２によって得られた中間体Ａ2に対して実装された電気・電子部品を絶縁基材に埋設し、そしてこの絶縁基材の表面に導電材料の箔を貼着する工程である。 In the intermediate A 2 , since the electric / electronic component 4 is mounted on the connection terminal portion 6b formed to project from the thin layer 2A, the connection is made between the electric / electronic component 4 and the conductive thin layer 2A. A minute clearance having a thickness substantially equal to the height of the terminal portion 6a is formed.
Step 3. This step is a step of embedding the electric / electronic component mounted on the intermediate A 2 obtained in step 2 in an insulating base material, and sticking a conductive material foil on the surface of the insulating base material. is there.

絶縁基材としては、例えばガラスクロス、ガラス繊維、アラミド繊維などを補強剤とし、ここに未硬化のエポキシ樹脂、フェノール樹脂、不飽和ポリエステルのような絶縁樹脂を含浸した絶縁シートが好適である。また、含浸した樹脂を半硬化させたプリプレグ材であってもよい。
中間体Ａ2の場合、図６で示したように、電気・電子部品４と導電薄層２Ａの表面を覆って絶縁基材１を配置し、更にその上面全体を被覆して導電材料の箔３を配置し、全体を加熱しながら箔３を押圧する。箔３としては、通常、銅箔が用いられる。 The insulating substrate such as glass cloth, glass fiber, aramide fiber and reinforcing agents, wherein the uncured epoxy resin, phenol resin, insulating sheet impregnated with an insulating resin such as unsaturated polyester is preferable. Further, a prepreg material obtained by semi-curing the impregnated resin may be used.
In the case of the intermediate A 2 , as shown in FIG. 6, the insulating base material 1 is disposed so as to cover the surfaces of the electric / electronic component 4 and the conductive thin layer 2 A, and the entire upper surface thereof is covered to form a conductive material foil. 3 is arranged and the foil 3 is pressed while heating the whole. As the foil 3, a copper foil is usually used.

絶縁基材１の絶縁樹脂は一旦軟化し、導電薄層２Ａと電気・電子部品４の間の微小クリアランスにも絶縁樹脂が侵入して電気・電子部品４の全体を被覆し、その後熱硬化する。
その結果、電気・電子部品４が絶縁基材１に埋設され、同時に絶縁基材１と箔３が接着している中間体Ａ3が得られる。
工程４。この工程は、工程３で製造された中間体Ａ3から、出発素材である板状体２の支持部材２Ｂを除去する工程である。具体的には支持部材２Ｂを剥離除去する工程である。 The insulating resin of the insulating base 1 is once softened, and the insulating resin penetrates into the minute clearance between the conductive thin layer 2A and the electric / electronic component 4 so as to cover the entire electric / electronic component 4, and then thermally cured. .
As a result, electric and electronic component 4 is embedded in the insulating substrate 1, an intermediate A3 is obtained insulating substrate 1 and the foil 3 simultaneously is bonded.
Step 4. This process, from Intermediate A 3 produced in step 3 is a step of removing the support member 2B of the plate-like body 2 which is the starting material. Specifically, this is a step of peeling and removing the support member 2B.

この工程４を行うことにより、図７に示した中間体Ａ4が得られる。
得られた中間体Ａ4は、電気・電子部品４を埋設する絶縁基材１の下面と上面がそれぞれ導電薄層２Ａ、箔３で被覆された構造体になっている。
なお、出発素材の板状体２として、前記した市販品の古河サーキットフォイル社製のキャリア付き銅箔などを用いれば、工程４における支持部材２Ｂの除去は、支持部材２Ｂの剥離操作によって容易に行うことができる。 By performing this step 4, the intermediate A 4 shown in FIG. 7 is obtained.
The obtained intermediate A 4 has a structure in which the lower surface and the upper surface of the insulating base material 1 in which the electric / electronic component 4 is embedded are covered with the conductive thin layer 2A and the foil 3, respectively.
In addition, if the above-described commercially available copper foil with a carrier manufactured by Furukawa Circuit Foil Co., Ltd. is used as the plate-like body 2 as a starting material, the removal of the support member 2B in the step 4 can be easily performed by the peeling operation of the support member 2B. It can be carried out.

工程５。この工程は、中間体Ａ4の導電薄層２Ａと箔３に、常用のフォトリソグラフィーとエッチング技術を適用して、導電薄層２Ａを所定パターンの導体回路２ａに加工し、箔３を同じく所定パターンの導体回路３ａに加工する。あわせて、中間体Ａ4の厚み方向にスルーホール５を形成して、図１で示した電気・電子部品内蔵回路基板Ａにする。
次に工程１Ｂを採用した場合の製造方法について説明する。 Step 5. This step is the intermediate A conductive thin layer 2A and the foil 3 of 4, by applying the Fotori Soviet Photography and etching techniques conventional, processed conductive thin layer 2A on the conductor circuit 2a in a predetermined pattern, the foil 3 also The conductor circuit 3a having a predetermined pattern is processed. At the same time, a through hole 5 is formed in the thickness direction of the intermediate body A 4 to form the electric / electronic component built-in circuit board A shown in FIG.
Next, a manufacturing method when step 1B is employed will be described.

工程１Ｂの場合は、図８で示したように、まず、板状体2の導電薄層２Ａの上面全体に、形成すべき接続端子部の高さと同じ厚みでソルダーレジストを塗布して層７を形成する。
そして、このソルダーレジスト層７を被覆してフォトレジスト層８を形成したのち、ここにフォトリソグラフィーとエッチング技術を適用して、形成すべき接続端子部の位置にソルダーレジスト７にまで至る開口部８ａを形成する（図９）。 In the case of step 1B, as shown in FIG. 8, first, a layer 7 is formed by applying a solder resist to the entire upper surface of the conductive thin layer 2A of the plate-like body 2 with the same thickness as the height of the connection terminal portion to be formed. Form.
Then, after covering the solder resist layer 7 to form the photoresist layer 8, the photolithography and etching technique are applied thereto, and the opening 8a reaching the solder resist 7 at the position of the connection terminal portion to be formed. (FIG. 9).

ついで、エッチャントを用いて開口部８ａの下に位置するソルダーレジスト層７の部分をエッチング除去して、接続端子部を形成すべき箇所に導電薄層２Ａにまで至る凹孔７ａを形成したのち、フォトレジスト層８を除去する。
その結果、ソルダーレジスト層７には、図１０で示したように、底部からは導電薄層２Ａの表面が表出している凹孔７ａが形成されている板状体が得られる。 Next, the etchant is used to etch away the portion of the solder resist layer 7 located below the opening 8a to form the concave hole 7a reaching the conductive thin layer 2A at the location where the connection terminal portion is to be formed. The photoresist layer 8 is removed.
As a result, as shown in FIG. 10 , a plate-like body is obtained in the solder resist layer 7 in which a concave hole 7a in which the surface of the conductive thin layer 2A is exposed from the bottom is formed.

ついで、ソルダーレジスト層７にソルダーペーストを用いたスクリーン印刷を行って凹孔７ａにソルダーペーストを充填する。その結果、図１１で示したように、ソルダーレジスト層７の所定箇所には、導電薄層２Ａの表面と接続するソルダーペースト６ｂから成る接続端子部が形成されている中間体Ｂ1が得られる。
得られた中間体Ｂ1は工程２に移送され、そこで導電薄層２Ａに形成されている接続端子部６ｂに電気・電子部品４の端子部４ａを重ね合わせたのち、全体を所定温度のリフロー炉に通し、ついで室温まで冷却する。 Next, screen printing using a solder paste is performed on the solder resist layer 7 to fill the concave holes 7a with the solder paste. As a result, as shown in FIG. 11, an intermediate B 1 is obtained in which a connection terminal portion made of a solder paste 6b connected to the surface of the conductive thin layer 2A is formed at a predetermined location of the solder resist layer 7. .
The obtained intermediate B 1 is transferred to step 2, where the terminal portion 4a of the electric / electronic component 4 is superimposed on the connection terminal portion 6b formed in the conductive thin layer 2A, and the whole is reflowed at a predetermined temperature. Pass through furnace and then cool to room temperature.

ソルダーペーストから成る接続端子部６ｂは、リフロー処理時にいったん溶融して端子部４ａと接合したのち冷却されることにより、端子部４ａが接続端子部６ｂに固着され、ここに接続端子部６ｂに電気・電子部品４が実装されている中間体Ｂ2が得られる（図１２）。
この中間体Ｂ2の場合は、前記した中間体Ａ2の場合と異なり、中間体Ａ2で形成されていた電気・電子部品４と導電薄層２Ａの間の微小クリアランスがソルダーレジスト層７で埋設された構造になっている。 The connection terminal portion 6b made of solder paste is once melted at the time of reflow processing, joined to the terminal portion 4a, and then cooled, whereby the terminal portion 4a is fixed to the connection terminal portion 6b, and the connection terminal portion 6b is electrically connected thereto. An intermediate B 2 on which the electronic component 4 is mounted is obtained (FIG. 12).
In the case of the intermediate B 2 , unlike the case of the intermediate A 2 described above, the fine clearance between the electrical / electronic component 4 and the conductive thin layer 2 A formed by the intermediate A 2 is caused by the solder resist layer 7. It has a buried structure.

中間体Ｂ2は工程３に移送され、そこで、実装された電気・電子部品が絶縁基材で埋設され、そしてこの絶縁基材の表面に導電材料の箔が貼着される。
その結果、図１３で示した中間体Ｂ３が得られる。
この中間体Ｂ３は工程４に移送され、そこで、板状体２の支持部材２Ｂを剥離除去して、下面と上面がそれぞれ導電薄層２Ａ、箔３で被覆されている中間体Ｂ４を得る（図１４）。 The intermediate B 2 is transferred to step 3, where the mounted electrical / electronic component is embedded with an insulating base material, and a foil of a conductive material is attached to the surface of the insulating base material.
As a result, the intermediate B 3 shown in FIG. 13 is obtained.
This intermediate body B 3 is transferred to step 4, where the support member 2B of the plate-like body 2 is peeled off and the intermediate body B 4 whose lower surface and upper surface are respectively covered with the conductive thin layer 2A and the foil 3 is obtained. Obtain (FIG. 14).

そして、中間体Ｂ4は工程５に移送され、そこで、導電薄層２Ａと箔３に、常用のフォトリソグラフィーとエッチング技術を適用して、導電薄層２Ａを所定パターンの導体回路２ａに加工し、箔３を同じく所定パターンの導体回路３ａに加工する。あわせて、中間体Ｂ4の厚み方向にスルーホール５を形成して、図２で示した電気・電子部品内蔵回路基板Ｂにする。 The Intermediate B 4 is transferred to step 5, where, in the conductive thin layer 2A and the foil 3, by applying the Fotori Soviet Photography and etching techniques conventional, the conductive thin layer 2A on the conductor circuit 2a in a predetermined pattern processing Then, the foil 3 is similarly processed into a conductor circuit 3a having a predetermined pattern. At the same time, a through hole 5 is formed in the thickness direction of the intermediate body B 4 to form the electric / electronic component built-in circuit board B shown in FIG.

この部品内蔵回路基板は、例えば、マザーボードに搭載するモジュール基板として使用することができ、またビルドアップ工法で部品内蔵多層回路基板を製造するときのコア基板としても使用することができる。
例えば、図１５は、本発明の部品内蔵回路基板Ｂをコア基板として用い、ビルドアップ工法で製造した部品内蔵３層回路基板の１例を示す断面図である。 This component built-in circuit board can be used, for example, as a module substrate mounted on a mother board, and can also be used as a core substrate when manufacturing a component built-in multilayer circuit board by a build-up method.
For example, FIG. 15 is a cross-sectional view showing an example of a component built-in three-layer circuit board manufactured by a buildup method using the component built-in circuit board B of the present invention as a core substrate.

この部品内蔵３層回路基板と、図１６のコア基板Ａ０を用いて製造した従来構造の部品内蔵３層回路基板Ａ’（図１７）とを対比して明らかなように、両社は同じ３層構造であるが、モジュール基板Ｂを用いた方が内蔵されている部品点数が多くなる。逆に言えば、内蔵する部品点数が同じであれば、基板全体の厚みが薄くなる。   As is clear from comparison between this component built-in three-layer circuit board and the component built-in three-layer circuit board A ′ (FIG. 17) of the conventional structure manufactured by using the core substrate A0 of FIG. Although it is a structure, the number of components incorporated is increased when the module substrate B is used. In other words, if the number of built-in components is the same, the thickness of the entire substrate is reduced.

本発明の回路基板Ａ，Ｂは以上の工程を経由して製造されるので、１層の絶縁基板と、そこに内蔵されている電気・電子部品と、絶縁基板の上面と下面に配線された導体回路と、その導体回路と電気・電子部品を接続し、かつ絶縁基材に内蔵されている接続端子部とを備えた構造になっていて、全体の表面には導体回路のみが配線されている。
このようなことから、この回路基板は、例えばマザーボードに搭載するモジュール基板として使用することができ、また、ビルドアップ工法で多層回路基板を製造するときのいわゆるコア基板としても使用することができる。 Since the circuit boards A and B according to the present invention are manufactured through the above-described steps, they are wired on the insulating substrate of one layer, the electric / electronic components incorporated therein, and the upper and lower surfaces of the insulating substrate. It has a structure that includes a conductor circuit and a connection terminal part that connects the conductor circuit and electrical / electronic components and is built in an insulating base material. Only the conductor circuit is wired on the entire surface. Yes.
For this reason, this circuit board can be used, for example, as a module board mounted on a mother board, and can also be used as a so-called core board when a multilayer circuit board is manufactured by a build-up method.

工程１Ａを経て製造した本発明の電気・電子部品内蔵回路基板Ａを示す断面図である。It is sectional drawing which shows the electric / electronic component built-in circuit board A of this invention manufactured through the process 1A. 工程１Ｂを経て製造した本発明の電気・電子部品内蔵回路基板Ｂを示す断面図である。It is sectional drawing which shows the electric / electronic component built-in circuit board B of this invention manufactured through the process 1B. 本発明の電気・電子部品内蔵回路基板を製造する際の出発素材である板状体を示す断面図である。It is sectional drawing which shows the plate-shaped body which is a starting material at the time of manufacturing the electric / electronic component built-in circuit board of this invention. 導電薄層の上に接続端子部が突設された中間体Ａ1を示す断面図である。Connection terminal portion on the conductive thin layer is a cross-sectional view showing an intermediate A 1 that protrudes. 中間体Ａ1に電気・電子部品が実装されている中間体Ａ2を示す断面図である。Is a sectional view showing an intermediate A 2 of electrical and electronic components Intermediate A 1 is mounted. 電気・電子部品が絶縁基材に埋設されている中間体Ａ3を示す断面図である。It is a sectional view showing an intermediate A 3 which electric and electronic components are embedded in the insulating substrate. 中間体Ａ3の板状体の支持部材を除去した中間体Ａ4を示す断面図である。It is a sectional view showing an intermediate A 4 removing the supporting member of the plate-like body of the intermediate A 3. 板状体の薄層の上面にソルダーレジスト層を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the soldering resist layer on the upper surface of the thin layer of a plate-shaped object. ソルダーレジスト層の上にフォトレジスト層を形成し、そこに開口部を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the photoresist layer on the soldering resist layer, and formed the opening part there. ソルダーレジスト層に凹孔を形成した状態を示す断面図である。It is sectional drawing which shows the state which formed the concave hole in the soldering resist layer. 工程１Ｂによって製造された中間体Ｂ1を示す断面図である。Is a sectional view showing an intermediate B 1 produced by the process 1B. 中間体Ｂ1に電気・電子部品が実装されている中間体Ｂ2を示す断面図である。Is a sectional view showing an intermediate B 2 of electrical and electronic components Intermediate B 1 is being implemented. 電気・電子部品が絶縁基材に埋設されている中間体Ｂ3を示す断面図である。Is a sectional view showing an intermediate B 3 of electric and electronic components are embedded in the insulating substrate. 中間体Ｂ3の板状体の支持部材を除去した中間体Ｂ4を示す断面図である。Is a sectional view showing an intermediate B 4 obtained by removing the supporting member of the plate-like body of Intermediate B 3. 本発明の回路基板Ｂを用いて製造した電気・電子部品内蔵３層回路基板の例を示す断面図である。It is sectional drawing which shows the example of the electrical / electronic component built-in 3 layer circuit board manufactured using the circuit board B of this invention. 従来のコア基板を示す断面図である。It is sectional drawing which shows the conventional core board | substrate. 図１６のコア基板を用いて製造した従来の電気・電子部品内蔵回路基板の例Ａ’を示す断面図である。FIG. 17 is a cross-sectional view illustrating an example A ′ of a conventional circuit board with built-in electric / electronic components manufactured using the core substrate of FIG. 16.

符号の説明Explanation of symbols

１ 絶縁基材
１ａ 絶縁基材１の上面
１ｂ 絶縁基材１の下面
２ 板状体
２Ａ 導電薄層
２Ｂ 支持部材
２ａ，３ａ 導体回路
３ 導電材料の箔
４ 電気・電子部品
４ａ 電気・電子部品４の端子部
５ スルーホール
６ａ，６ｂ 接続端子部
７ ソルダーレジスト
７ａ 凹孔
８ フォトレジスト層
８ａ 開口部 DESCRIPTION OF SYMBOLS 1 Insulating base material 1a Upper surface of insulating base material 1b Lower surface of insulating base material 2 Plate-like body 2A Conductive thin layer 2B Support member 2a, 3a Conductor circuit 3 Conductive material foil 4 Electrical / electronic component 4a Electrical / electronic component 4 Terminal part 5 Through hole 6a, 6b Connection terminal part 7 Solder resist 7a Concave hole 8 Photoresist layer 8a Opening part

Claims (4)

絶縁基材と、
前記絶縁基材の一方の面にソルダーレジスト層を介在させて形成された第１導体回路及び前記絶縁基材の一方の面とは反対側の他方の面に形成された第２導体回路と、
前記絶縁基材の中に埋設され、前記一方の面側に前記第１導体回路と電気的に接続されるべき端子を有する電気・電子部品と
を備え、
前記ソルダーレジスト層は、
前記電気・電子部品の端子を個別に前記第１導体回路に向けて露出させる孔を有し、
前記孔に充填されたソルダーペーストによって形成され、前記端子と前記第１導体回路とを電気的に接続する接続導電体を更に含む
ことを特徴とする電気・電子部品内蔵回路基板。 An insulating substrate;
A first conductor circuit formed by interposing a solder resist layer on one surface of the insulating substrate and a second conductor circuit formed on the other surface opposite to the one surface of the insulating substrate ;
An electrical / electronic component embedded in the insulating substrate and having a terminal to be electrically connected to the first conductor circuit on the one surface side ;
The solder resist layer is
A hole for exposing the terminal of the electrical / electronic component individually toward the first conductor circuit;
A circuit board with a built-in electric / electronic component , further comprising a connection conductor formed by a solder paste filled in the hole and electrically connecting the terminal and the first conductor circuit . 請求項１に記載の電気・電子部品内蔵回路基板の製造方法であって、
支持基材と、前記支持基材に積層され、前記第１導体回路となるべき導電薄層とを含む２層構造の板状体を準備する準備工程と、
前記導電薄層の前記支持基材と接触する第１面とは反対側の第２面に、前記導電薄層に至る前記孔を有するソルダーレジスト層を形成する工程と、
前記孔にソルダーペーストを充填し、前記導電薄層に電気的に接続されたペーストポストを形成する工程と、
前記ペーストポスト上に前記電気・電子部品の前記端子を介して前記電気・電子部品を配設した後、前記ペーストポストの加熱溶融処理を経て、前記ペーストポストを前記端子と前記導電薄層とを電気的に接続する前記接続導電体に形成し、前記電気・電子部品を前記板状体の前記導電薄層上に実装する実装工程と、
前記電気・電子部品が実装された前記導電薄層上に前記電気・電子部品を前記ソルダーレジスト層とともに埋設する前記絶縁基材を形成するとともに、前記絶縁基材の前記導電薄層とは反対側の面に前記第２導体回路となるべき導電材料の箔を配置する積層工程と、
前記板状体から前記支持基材を剥離して前記導電薄層の第１面を表出させる剥離工程と、
前記導電薄層および前記箔を所定パターンに加工して前記第１及び第２導体回路にそれぞれ形成する導体回路形成工程と
を備えていることを特徴とする電気・電子部品内蔵回路基板の製造方法。 A method for manufacturing an electric / electronic component built-in circuit board according to claim 1,
A preparatory step of preparing a plate-shaped body having a two-layer structure including a support base material and a conductive thin layer that is laminated on the support base material and is to be the first conductor circuit ;
Forming a solder resist layer having the holes reaching the conductive thin layer on a second surface opposite to the first surface contacting the support base of the conductive thin layer;
Filling the holes with a solder paste and forming paste posts electrically connected to the conductive thin layer;
After the electric / electronic component is disposed on the paste post via the terminal of the electric / electronic component, the paste post is heated and melted to form the paste post with the terminal and the conductive thin layer. A mounting step of forming the connection conductor to be electrically connected and mounting the electrical / electronic component on the conductive thin layer of the plate-like body,
Forming the insulating base material for embedding the electric / electronic component together with the solder resist layer on the conductive thin layer on which the electric / electronic component is mounted, and the opposite side of the insulating base material from the conductive thin layer A laminating step of disposing a foil of a conductive material to be the second conductor circuit on the surface of
A peeling step of peeling the support substrate from the plate-like body to expose the first surface of the conductive thin layer;
A circuit for forming an electric / electronic component , comprising: a conductive circuit forming step of forming the conductive thin layer and the foil into a predetermined pattern to form the first and second conductive circuits, respectively. A method for manufacturing a substrate. 前記準備工程は、
前記板状体に含まれる前記導電薄層として第１の銅箔を用いるとともに前記支持基材として前記第１の銅箔より厚さが厚い肉厚銅箔を用いることを特徴とする請求項２に記載の電気・電子部品内蔵回路基板の製造方法。 The preparation step includes
The first copper foil is used as the conductive thin layer contained in the plate-like body, and a thick copper foil having a thickness greater than that of the first copper foil is used as the support base. The manufacturing method of the circuit board with a built-in electric / electronic component of description . 前記積層工程は、
前記導電材料の箔として第２の銅箔を用いることを特徴とする請求項２又は３に記載の電気・電子部品内蔵回路基板の製造方法。 The laminating step includes
4. The method of manufacturing a circuit board with built-in electric / electronic components according to claim 2, wherein a second copper foil is used as the conductive material foil .
JP2008188843A 2008-07-22 2008-07-22 Circuit board with built-in electric / electronic components and manufacturing method thereof Expired - Fee Related JP4874305B2 (en)

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