JP4830265B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4830265B2
JP4830265B2 JP2004138122A JP2004138122A JP4830265B2 JP 4830265 B2 JP4830265 B2 JP 4830265B2 JP 2004138122 A JP2004138122 A JP 2004138122A JP 2004138122 A JP2004138122 A JP 2004138122A JP 4830265 B2 JP4830265 B2 JP 4830265B2
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将伸 岩谷
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Fuji Electric Co Ltd
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この発明は、特に、スイッチング電源用ＩＣ，自動車パワー部品駆動用ＩＣ、フラットパネルディスプレイ用駆動用ＩＣなど高耐圧で高電流を制御するＩＣに用いられる低オン抵抗の絶縁ゲート型トランジスタを含む半導体装置の製造方法に関し、特にトレンチを主要構成部として備えるトレンチ横型ＭＯＳＦＥＴと、気相成長法により成膜される上層下層導電膜により誘電体層が挟まれてなる積層構造を主要基本構成とするキャパシタとを同一半導体基板上に備える半導体装置の製造方法に関する。   The present invention particularly relates to a semiconductor device including a low on-resistance insulated gate transistor used in an IC for controlling a high current with a high breakdown voltage, such as a switching power supply IC, an automotive power component driving IC, and a flat panel display driving IC. In particular, a trench lateral MOSFET having a trench as a main component, and a capacitor having a multilayer structure in which a dielectric layer is sandwiched between upper and lower conductive films formed by vapor deposition as a main basic component, The present invention relates to a method for manufacturing a semiconductor device provided on the same semiconductor substrate.

近年、携帯機器の急速な普及や通信技術の高度化などに伴い、パワーＭＯＳＦＥＴを内蔵したパワーＩＣの重要性が高まっている。最近、このようなパワーＭＯＳＦＥＴとしては、低オン低抵抗が得られ、高集積化が可能なトレンチ横型ＭＯＳＦＥＴ（以降、ＴＬＰＭと略す）が注目されている。一方、Ｐ型シリコン基板を用いて、ポリシリコンからなる二層の電極膜間に誘電体膜を挟持する構成からなるキャパシタの製造方法についても、それ自体はよく知られているところである。
前記ＴＬＰＭについては、よく知られているようにトレンチ底部にドレインコンタクトを設けるタイプのＴＬＰＭ（以下、ＴＬＰＭ／Ｄとする）と、トレンチ底部にソースコンタクトを設けるタイプのＴＬＰＭ（以下、ＴＬＰＭ／Ｓとする）がある。これらのＴＬＰＭでは、ＭＯＳＦＥＴとしての機能電流を駆動する領域（以下、活性領域とする）、および基板表面にゲート電極膜となるゲートポリシリコンを引き出す領域（以下、ゲート領域とする）のいずれにおいても、前記トレンチの中央部には、デバイス表面のドレイン電極膜とトレンチ底部のドレイン領域（ＴＬＰＭ／Ｄの場合）、またはデバイス表面のソース電極膜とトレンチ底部のソース領域（ＴＬＰＭ／Ｓの場合）とを電気的に接続するポリシリコンなどの導電体が、前記トレンチを埋める層間絶縁膜中に形成された開口部に埋設された状態で配置されている（特許文献１または２参照。）。 In recent years, with the rapid spread of portable devices and the advancement of communication technology, the importance of power ICs incorporating power MOSFETs has increased. Recently, as such a power MOSFET, a trench lateral MOSFET (hereinafter abbreviated as TLPM), which has a low on-low resistance and can be highly integrated, has attracted attention. On the other hand, a method for manufacturing a capacitor having a configuration in which a dielectric film is sandwiched between two electrode films made of polysilicon using a P-type silicon substrate is well known.
As is well known, the TLPM is a type of TLPM having a drain contact at the bottom of the trench (hereinafter referred to as TLPM / D) and a type of TLPM having a source contact at the bottom of the trench (hereinafter referred to as TLPM / S). There is). In these TLPMs, in any of a region for driving a functional current as a MOSFET (hereinafter referred to as an active region) and a region for extracting gate polysilicon serving as a gate electrode film on the substrate surface (hereinafter referred to as a gate region). The drain electrode film on the device surface and the drain region at the bottom of the trench (in the case of TLPM / D) or the source electrode film on the device surface and the source region at the bottom of the trench (in the case of TLPM / S) A conductor such as polysilicon that electrically connects is buried in an opening formed in an interlayer insulating film that fills the trench (see Patent Document 1 or 2).

前述したＴＬＰＭとキャパシタとを同一基板上に集積化した半導体装置の製造方法について以下説明する。ＴＬＰＭとしては、前述のようにトレンチの底がドレインとなるＮチャネルＴＬＰＭ／Ｄの場合で説明する。図５に示すように、Ｐ型シリコン基板（Ｐ―ｓｕｂ）５０に選択的にＰウェル領域（図５の表示範囲では選択的ではなく全面となっている）５１を形成する。図６に示すように、ＴＬＰＭを形成する領域部分に所定のパターン加工された熱酸化膜、ＣＶＤ酸化膜等の酸化膜５２をマスクとして、異方性エッチングによりトレンチ５３を形成する。続いて、イオン注入法を用いて、トレンチ５３の底面だけに選択的にＮドレイン領域５４を形成する。図７に示すように、キャパシタを形成する領域に、キャパシタを前記ＴＬＰＭその他の半導体素子から素子分離するためのＬＯＣＯＳ酸化膜５６を形成する。次に、図８に示すように、ゲート酸化膜５７を熱酸化法により形成し、さらに、トレンチ５３内壁面を含む全面にポリシリコン膜をＣＶＤ法により形成した後、フォトレジスト膜（図示せず）を全面に塗布し、第一電極膜６０の形成部分の上だけ残すように前記フォトレジスト膜をパターニング加工し、この加工により得られたフォトレジスト膜をマスクとして異方性エッチングにより前記ポリシリコン膜をエッチングして、第一電極膜６０とゲート電極膜５９を形成する。このとき、前記ゲート電極膜５９の形成は異方性エッチングで行なわれるため、トレンチ５３の側壁に形成されていたポリシリコン膜の表面には、前記フォトレジスト膜がマスクとして形成されていなくても、エッチングされずゲート電極膜５９として残ることにより形成される。   A method for manufacturing a semiconductor device in which the above-described TLPM and capacitor are integrated on the same substrate will be described below. The TLPM will be described in the case of the N-channel TLPM / D in which the bottom of the trench is the drain as described above. As shown in FIG. 5, a P-well region 51 (which is not selective in the display range of FIG. 5 but the entire surface) 51 is selectively formed on a P-type silicon substrate (P-sub) 50. As shown in FIG. 6, a trench 53 is formed by anisotropic etching using an oxide film 52 such as a thermal oxide film and a CVD oxide film patterned in a predetermined pattern in a region where a TLPM is to be formed. Subsequently, an N drain region 54 is selectively formed only on the bottom surface of the trench 53 by ion implantation. As shown in FIG. 7, a LOCOS oxide film 56 for isolating the capacitor from the TLPM and other semiconductor elements is formed in a region where the capacitor is to be formed. Next, as shown in FIG. 8, a gate oxide film 57 is formed by a thermal oxidation method, a polysilicon film is formed on the entire surface including the inner wall surface of the trench 53 by a CVD method, and then a photoresist film (not shown) is formed. ) Is applied to the entire surface, and the photoresist film is patterned so as to remain only on the portion where the first electrode film 60 is formed. The polysilicon film is anisotropically etched using the photoresist film obtained by this process as a mask. The film is etched to form the first electrode film 60 and the gate electrode film 59. At this time, since the gate electrode film 59 is formed by anisotropic etching, even if the photoresist film is not formed on the surface of the polysilicon film formed on the side wall of the trench 53 as a mask. The gate electrode film 59 is left without being etched.

次に、イオン注入により、Ｎソース領域５８を形成し、さらにキャパシタの誘電体膜６１として利用することになるシリコン酸化膜を形成する。このシリコン酸化膜に対して、第一電極膜６０の上に対応する部分を残すようにフォトエッチングしてキャパシタの誘電体膜６１を形成する。次に、全面にポリシリコン膜を形成した後、前述の第一電極膜６０の形成と同様な方法で、前記ポリシリコン膜をパターンエッチングすることにより、第二電極膜６２を、第一電極膜６０と誘電体膜６１の上に形成する。次に、トレンチ５３内を埋める層間絶縁膜５５をＣＶＤ法により形成した後、層間絶縁膜５５表面の凹凸を平坦化するために、化学機械研磨（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ以下ＣＭＰと略す）法により研磨する。ＴＬＰＭ領域６３とキャパシタ領域６４のそれぞれの各電極膜位置に、開口部６５、６６、６７、６８をフォトリソグラフ技術により形成し、前記開口部にバリアメタル６９、７０、７１、７２と、埋め込み金属プラグ７３、７４、７５、７６と、金属電極膜７７、７８、７９、８０とをこの順に形成すると、図１０に示すようなＴＬＰＭとキャパシタとを同一半導体基板上に備える半導体装置ができる。前記バリアメタルとしては、ＴｉまたはＴｉ−Ｎ膜、埋め込み金属プラグとしてはタングステン、前記金属電極膜としたは、アルミニウムなどの金属が用いられる。   Next, an N source region 58 is formed by ion implantation, and a silicon oxide film to be used as the dielectric film 61 of the capacitor is formed. The dielectric film 61 of the capacitor is formed by photoetching the silicon oxide film so as to leave a corresponding portion on the first electrode film 60. Next, after a polysilicon film is formed on the entire surface, the polysilicon film is subjected to pattern etching in the same manner as the formation of the first electrode film 60 described above, whereby the second electrode film 62 is changed to the first electrode film. 60 and the dielectric film 61 are formed. Next, an interlayer insulating film 55 filling the trench 53 is formed by a CVD method, and then polished by a chemical mechanical polishing (hereinafter abbreviated as CMP) method in order to flatten the unevenness on the surface of the interlayer insulating film 55. . Openings 65, 66, 67, 68 are formed at respective electrode film positions of the TLPM region 63 and the capacitor region 64 by photolithography, and barrier metals 69, 70, 71, 72 and buried metal are formed in the openings. When plugs 73, 74, 75, and 76 and metal electrode films 77, 78, 79, and 80 are formed in this order, a semiconductor device having a TLPM and a capacitor as shown in FIG. 10 on the same semiconductor substrate can be obtained. The barrier metal is a Ti or Ti-N film, the buried metal plug is tungsten, and the metal electrode film is a metal such as aluminum.

他方、前述した半導体装置とは集積される素子が異なるパワーＩＣ用の横型パワーＭＯＳＦＥＴに関する内容であるが、デバイスピッチが小さく、単位面積当たりのオン抵抗を小さくすることができる発明が知られている（特許文献３−段落００２９）。この特許文献では、ポリシリコン膜を全面に形成後、異方性エッチングによりトレンチ内の側壁にのみゲート電極膜となるポリシリコン膜を残すという開示がある。
特開２００３−５１５９４号公報 特開２００２−３５３４４７号公報 特開２００２−２８０５４９号公報 On the other hand, the content relates to a lateral power MOSFET for a power IC that is different from the semiconductor device described above, but an invention is known in which the device pitch is small and the on-resistance per unit area can be reduced. (Patent Document 3-Paragraph 0029). This patent document discloses that after a polysilicon film is formed on the entire surface, a polysilicon film that becomes a gate electrode film is left only on the side wall in the trench by anisotropic etching.
JP 2003-51594 A JP 2002-353447 A JP 2002-280549 A

しかしながら、前記図１０に示す半導体装置はＴＬＰＭの電気特性に関する不良発生率が高いという問題が発生した。そこで、前述のＴＬＰＭの電気特性不良が高いという問題点について、鋭意調べた結果、前述のキャパシタの第二電極膜６２を形成する際、この第二電極膜６２についても、前記第一電極膜６０の形成の場合と同様に全面に形成したポリシリコン膜の異方性エッチングにより所定のパターンが形成されるので、前記ポリシリコンゲート電極膜５９がトレンチ５３の内壁に形成されるのと同様に、トレンチ５３の内壁にポリシリコン膜６２ａが残ってしまい、層間絶縁膜５５の絶縁性不良となり易いためであることが、前述の不良発生率の高い原因であることを突き止めた。
本発明は、以上、説明した点に鑑みてなされたものであり、本発明の目的は、トレンチ型絶縁ゲート型トランジスタとを同一半導体基板上に備える半導体装置の製造方法において、絶縁ゲート型トランジスタの電気特性不良の発生を少なくすることのできる半導体装置の製造方法を提供することである。 However, the semiconductor device shown in FIG. 10 has a problem that the defect occurrence rate related to the electrical characteristics of TLPM is high. Therefore, as a result of intensive investigation on the problem that the electrical characteristic failure of the TLPM is high, when the second electrode film 62 of the capacitor is formed, the second electrode film 62 is also the first electrode film 60. Since a predetermined pattern is formed by anisotropic etching of the polysilicon film formed on the entire surface in the same manner as in the case of forming the above, as in the case where the polysilicon gate electrode film 59 is formed on the inner wall of the trench 53, The fact that the polysilicon film 62a remains on the inner wall of the trench 53 and easily causes an insulation failure of the interlayer insulating film 55 has been found to be the cause of the high occurrence rate of the aforementioned failure.
The present invention has been made in view of the above-described points. An object of the present invention is to provide a method for manufacturing a semiconductor device including a trench type insulated gate transistor on the same semiconductor substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce the occurrence of electrical characteristic defects.

特許請求の範囲の請求項１記載の本発明によれば、半導体基板に形成されるトレンチの側壁に絶縁膜を介してゲート電極膜が形成される絶縁ゲート型トランジスタと、前記半導体基板上に素子分離領域を介して順次積層される第一電極膜、第二電極膜および該第一電極膜と第二電極膜とに挟持される誘電体膜とからなるキャパシタを備える半導体装置の製造方法において、順次処理される、前記トレンチを形成する工程と、前記素子分離領域を前記トレンチに対し離間させて形成する工程と、前記トレンチの側壁に前記絶縁膜を形成する工程、前記半導体基板表面およびトレンチ内面に第一電極膜形成用導電膜を形成する工程と、前記第一電極膜形成領域上の前記第一電極膜形成用導電膜にマスクを形成する工程と、前記第一電極膜形成用導電膜を異方性エッチングすることにより、前記第一電極膜および前記ゲート電極膜を形成する工程と、前記半導体基板表面および前記トレンチの側壁および底面に前記ゲート電極膜の表面を覆うように前記誘電体膜を形成する工程と、前記半導体基板表面および前記トレンチの側壁および底面に前記誘電体膜の表面を覆うように第二電極膜形成用導電膜を形成する工程と、該第二電極膜形成用導電膜上の前記第二電極膜形成領域上にマスクを形成する工程と、前記第二電極膜形成用導電膜を等方性エッチングして第二電極膜を形成する工程と、前記トレンチを層間絶縁膜で埋める工程と、を備える半導体装置の製造方法とすることにより、上記目的は達成される。
また、特許請求の範囲の請求項２に記載の本発明によれば、請求項１の製造方法において、前記トレンチを層間絶縁膜で埋める工程の後に、該層間絶縁膜に前記トレンチ底部の一部を露出する開口部を形成する工程と、前記開口部に金属プラグを埋める工程と、を備える製造方法とすることにより達成される。 According to the first aspect of the present invention, an insulated gate transistor in which a gate electrode film is formed on a sidewall of a trench formed in a semiconductor substrate via an insulating film, and an element on the semiconductor substrate In a method of manufacturing a semiconductor device including a capacitor including a first electrode film, a second electrode film, and a dielectric film sandwiched between the first electrode film and the second electrode film, which are sequentially stacked via an isolation region, The step of forming the trench, the step of forming the element isolation region apart from the trench, the step of forming the insulating film on the side wall of the trench, the surface of the semiconductor substrate and the inner surface of the trench, which are sequentially processed Forming a first electrode film forming conductive film on the first electrode film forming region; forming a mask on the first electrode film forming conductive film on the first electrode film forming region; and By anisotropic etching of the film, said forming a first electrode film and the gate electrode film, said to cover the semiconductor substrate surface and the surface of the gate electrode film on the side walls and bottom surface of said trench dielectric forming a body layer, and forming a second electrode film formation conductive film so as to cover the surface of the dielectric film on the side walls and bottom surface of the semiconductor substrate surface and the trench, wherein the second electrode film formed Forming a mask on the second electrode film forming region on the conductive film, forming a second electrode film by isotropically etching the second electrode film forming conductive film, and forming the trench The above object is achieved by a method for manufacturing a semiconductor device comprising a step of filling with an interlayer insulating film.
According to the present invention of claim 2, in the manufacturing method of claim 1, after the step of filling the trench with an interlayer insulating film, a part of the bottom of the trench is formed on the interlayer insulating film. This is achieved by a manufacturing method comprising a step of forming an opening exposing the metal and a step of filling a metal plug in the opening.

特許請求の範囲の請求項３記載の本発明によれば、前記第一電極膜と前記第二電極膜がポリシリコンを主要成分とする特許請求の範囲の請求項１または２に記載の半導体装置の製造方法とすることが好ましい。
特許請求の範囲の請求項４記載の本発明によれば、前記等方性エッチングが気相エッチングである請求項１乃至３のいずれか一項に記載の半導体装置の製造方法とすることが望ましい。 According to the present invention as set forth in claim 3, the semiconductor device according to claim 1 or 2 , wherein the first electrode film and the second electrode film are mainly composed of polysilicon. It is preferable to use this manufacturing method.
According to the present invention as set forth in claim 4, it is preferable that the method for manufacturing a semiconductor device according to claim 1, wherein the isotropic etching is vapor phase etching. .

本発明によれば、トレンチ型絶縁ゲート型トランジスタとキャパシタとを同一半導体基板上に備える半導体装置の製造方法において、絶縁ゲート型トランジスタの電気特性不良の発生を少なくすることのできる半導体装置の製造方法を提供することができる。   According to the present invention, in a method of manufacturing a semiconductor device including a trench type insulated gate transistor and a capacitor on the same semiconductor substrate, the method of manufacturing a semiconductor device capable of reducing the occurrence of electrical characteristic defects of the insulated gate transistor. Can be provided.

以下、本発明にかかる一実施例について、図面を用いて詳細に説明する。以下の実施例ではトレンチ型絶縁ゲートトランジスタとして、ＴＬＰＭ／Ｄの場合について説明するが、ＴＬＰＭ／Ｓの場合についても同様に本発明にかかる半導体基板の製造方法により作ることができることは言うまでもない。本発明の要旨を超えない限り、本発明は以下説明する実施例の記載に限定されるものではない。   Hereinafter, an embodiment according to the present invention will be described in detail with reference to the drawings. In the following embodiments, the case of TLPM / D will be described as a trench-type insulated gate transistor, but it goes without saying that the case of TLPM / S can be similarly produced by the method for manufacturing a semiconductor substrate according to the present invention. As long as the gist of the present invention is not exceeded, the present invention is not limited to the description of the examples described below.

図１は、この発明の半導体装置の製造方法により作られた半導体装置の一実施例を示すものであり、ＴＬＰＭとキャパシタとが同一半導体基板上に形成されたことを示す模式的断面図である。図２、３、４は、それぞれ本発明にかかる前記図１に示す半導体装置を製造する際の各製造工程に対応する各半導体基板の模式的断面図である。図２、３は、前述した従来の製造工程にかかる図８、９にそれぞれ対応する。図２に至るまでの製造工程は、前述の図５〜図７における従来の製造工程とほぼ同じであるから、ここでは詳細な説明を省略する。
本発明にかかる半導体装置の製造方法について説明する。図２において、Ｐ型Ｓｉ基板１にＰウェル層２、トレンチ３、Ｎドレイン層４およびＬＯＣＯＳ酸化膜６等を周知の技術により形成後、ゲート酸化膜７を熱酸化法により形成し、全面にポリシリコン膜（図示せず）をＣＶＤ法により成膜した後、その上にフォトレジスト膜（図示せず）を全面に塗布し、第一電極膜部分の上だけを残すようにフォトレジスト膜をパターニング（図示せず）し、このフォトレジスト膜をマスクとしてＲＩＥなどの異方性エッチングによりポリシリコン膜をパターニング加工し、第一電極膜１０とゲート電極膜９とを形成する。トレンチ３の側壁に形成されていたポリシリコン膜の表面には、前記フォトレジスト膜がマスクとして形成されていなくても、エッチングされずゲート電極膜９として残る。このように、マスクなしでもゲート電極がエッチングされずに残った理由は、異方性エッチングが用いられたため、トレンチ３の内面に形成されているポリシリコン膜は底部のみエッチングされ、側壁のポリシリコン膜はエッチングされず残るからである。次にイオン注入により、Ｎソース領域８を形成した後、キャパシタの誘電体膜に加工されることになるシリコン酸化膜（図示せず）を全面に形成する。このシリコン酸化膜のうち、第一電極膜１０の上に形成された部分がキャパシタの誘電体膜１１となる。次に、全面にポリシリコン膜を形成した後、フォトレジスト膜（図示せず）を全面に塗布し、第二電極膜１２となる部分のみ残すようにフォトレジスト膜をパターニングし、このフォトレジスト膜をマスクとして、ＣＤＥ（ケミカル ドライ エッチング）等の等方性エッチングによりポリシリコン膜をエッチングして第二電極膜１２を形成する。 FIG. 1 shows an embodiment of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention, and is a schematic cross-sectional view showing that a TLPM and a capacitor are formed on the same semiconductor substrate. . 2, 3, and 4 are schematic cross-sectional views of each semiconductor substrate corresponding to each manufacturing process when manufacturing the semiconductor device shown in FIG. 1 according to the present invention. 2 and 3 respectively correspond to FIGS. 8 and 9 relating to the above-described conventional manufacturing process. Since the manufacturing process up to FIG. 2 is almost the same as the conventional manufacturing process in FIGS. 5 to 7 described above, detailed description thereof is omitted here.
A method for manufacturing a semiconductor device according to the present invention will be described. In FIG. 2, a P well layer 2, a trench 3, an N drain layer 4, a LOCOS oxide film 6 and the like are formed on a P type Si substrate 1 by a known technique, and then a gate oxide film 7 is formed by a thermal oxidation method. After a polysilicon film (not shown) is formed by CVD, a photoresist film (not shown) is applied over the entire surface, and a photoresist film is formed so as to leave only the first electrode film portion. Patterning (not shown) is performed, and the polysilicon film is patterned by anisotropic etching such as RIE using the photoresist film as a mask to form the first electrode film 10 and the gate electrode film 9. Even if the photoresist film is not formed as a mask, it is not etched and remains as the gate electrode film 9 on the surface of the polysilicon film formed on the sidewall of the trench 3. As described above, the reason why the gate electrode remains without being etched even without the mask is that anisotropic etching is used, so that the polysilicon film formed on the inner surface of the trench 3 is etched only at the bottom, and the polysilicon on the side wall is etched. This is because the film remains without being etched. Next, after an N source region 8 is formed by ion implantation, a silicon oxide film (not shown) to be processed into a capacitor dielectric film is formed on the entire surface. Of this silicon oxide film, the portion formed on the first electrode film 10 becomes the dielectric film 11 of the capacitor. Next, after a polysilicon film is formed on the entire surface, a photoresist film (not shown) is applied to the entire surface, and the photoresist film is patterned so as to leave only a portion to become the second electrode film 12, and this photoresist film Is used as a mask to etch the polysilicon film by isotropic etching such as CDE (Chemical Dry Etching) to form the second electrode film 12.

この際に本発明では前記第二電極膜１２へのパターニング加工を従来とは異なり、ＲＩＥエッチング等の異方性エッチングではなく、等方性エッチングを用いる点に特長がある。この等方性エッチングにより、前記図１０に示す従来の製造方法により得られる半導体装置のように、トレンチ内壁にポリシリコン膜６２ａが残ることが無くなる。このように、トレンチ内壁にポリシリコン膜６２ａが残らないので、このポリシリコン膜６２ａと、タングステンプラグ等の金属が埋め込まれた開口部１７との絶縁不良を少なくすることができ、ＴＬＰＭの電気不良を減らすことができるのである。前記等方性エッチングとしては、ＣＦ4＋Ｏ2の混合ガスをプラズマ化した気体を利用したＣＤＥや液相でのフッ硝酸系エッチングがあるが、制御の容易性や作業性の点から気相でのＣＤＥが好ましい。次に、従来と同様にトレンチ３内を埋める層間絶縁膜５をＣＶＤ法により形成した後、層間絶縁膜５表面の凹凸を平坦化するために、ＣＭＰ法により研磨する。ＴＬＰＭ領域１３とキャパシタ領域１４のそれぞれの各電極位置に対応するように、開口部１５、１６、１７、１８をフォトリソグラフ技術により形成し、前記開口部にＴｉ−ＴｉＮ膜などのバリアメタル１９、２０、２１、２２、タングステンなどの埋め込み金属プラグ２３、２４、２５、２６およびアルミニウム膜などの金属電極膜２７、２８、２９、３０をこの順に形成すると、図１に示す半導体装置が完成する。 At this time, the present invention is characterized in that isotropic etching is used instead of anisotropic etching such as RIE etching, unlike the conventional patterning process on the second electrode film 12. By this isotropic etching, the polysilicon film 62a does not remain on the inner wall of the trench as in the semiconductor device obtained by the conventional manufacturing method shown in FIG. As described above, since the polysilicon film 62a does not remain on the inner wall of the trench, it is possible to reduce the insulation failure between the polysilicon film 62a and the opening 17 in which a metal such as a tungsten plug is embedded, and the electrical failure of the TLPM. Can be reduced. Examples of the isotropic etching include CDE using a gas obtained by converting a mixed gas of CF 4 + O 2 into plasma, and hydrofluoric acid-based etching in a liquid phase, but in the gas phase in terms of ease of control and workability. CDE is preferred. Next, an interlayer insulating film 5 filling the trench 3 is formed by the CVD method as in the prior art, and then polished by the CMP method in order to flatten the irregularities on the surface of the interlayer insulating film 5. Openings 15, 16, 17 and 18 are formed by photolithography so as to correspond to the respective electrode positions of the TLPM region 13 and the capacitor region 14, and a barrier metal 19 such as a Ti-TiN film is formed in the opening. When the buried metal plugs 23, 24, 25, and 26 such as tungsten and the metal electrode films 27, 28, 29, and 30 such as aluminum films are formed in this order, the semiconductor device shown in FIG. 1 is completed.

前記タングステンプラグは次のようにして形成される。まず、前記Ｔｉ−ＴｉＮ膜上に、六フッ化タングステンとモノシランを用いた還元反応によるタングステンの核生成後、六フッ化タングステンと水素を用いた還元反応により前記開口部１５、１６、１７、１８を埋めるの厚さ以上のタングステン膜を形成する。次にドライエッチングにより、前記開口部１５、１６、１７、１８以外のタングステン膜をエッチバックして除去して前記タングステンプラグを形成する。   The tungsten plug is formed as follows. First, after nucleation of tungsten by a reduction reaction using tungsten hexafluoride and monosilane on the Ti—TiN film, the openings 15, 16, 17, 18 by a reduction reaction using tungsten hexafluoride and hydrogen. Form a tungsten film that is thicker than the fill. Next, by dry etching, the tungsten film other than the openings 15, 16, 17, and 18 is etched back and removed to form the tungsten plug.

本発明の半導体装置の製造方法により作られる半導体装置の模式的断面図Schematic sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device of the present invention 本発明の半導体装置の製造方法にかかる製造工程における一ステップの半導体基板の要部断面図Sectional drawing of the principal part of the semiconductor substrate of one step in the manufacturing process concerning the manufacturing method of the semiconductor device of this invention 本発明の半導体装置の製造方法にかかる製造工程における一ステップの半導体基板の要部断面図Sectional drawing of the principal part of the semiconductor substrate of one step in the manufacturing process concerning the manufacturing method of the semiconductor device of this invention 本発明の半導体装置の製造方法にかかる製造工程における一ステップの半導体基板の要部断面図Sectional drawing of the principal part of the semiconductor substrate of one step in the manufacturing process concerning the manufacturing method of the semiconductor device of this invention 従来の半導体装置の製造方法にかかる製造工程における一ステップの半導体基板の要部断面図Sectional drawing of the principal part of the semiconductor substrate of one step in the manufacturing process concerning the manufacturing method of the conventional semiconductor device 従来の半導体装置の製造方法にかかる製造工程における一ステップの半導体基板の要部断面図Sectional drawing of the principal part of the semiconductor substrate of one step in the manufacturing process concerning the manufacturing method of the conventional semiconductor device 従来の半導体装置の製造方法にかかる製造工程における一ステップの半導体基板の要部断面図Sectional drawing of the principal part of the semiconductor substrate of one step in the manufacturing process concerning the manufacturing method of the conventional semiconductor device 従来の半導体装置の製造方法にかかる製造工程における一ステップの半導体基板の要部断面図Sectional drawing of the principal part of the semiconductor substrate of one step in the manufacturing process concerning the manufacturing method of the conventional semiconductor device 従来の半導体装置の製造方法にかかる製造工程における一ステップの半導体基板の要部断面図Sectional drawing of the principal part of the semiconductor substrate of one step in the manufacturing process concerning the manufacturing method of the conventional semiconductor device 従来の半導体装置の製造方法により作られる半導体装置の模式的断面図Schematic cross-sectional view of a semiconductor device manufactured by a conventional method for manufacturing a semiconductor device

符号の説明Explanation of symbols

１ Ｐ型Ｓｉ基板
２ Ｐウェル領域
４ Ｎドレイン領域
５ 層間絶縁膜
６ ＬＯＣＯＳ酸化膜（素子分離酸化膜）
７ ゲート酸化膜
８ Ｎソース領域
９ ゲート電極膜
１０ 第一電極膜
１１ 誘電体膜
１２ 第二電極膜
１３ 絶縁ゲート型トランジスタ領域、ＴＬＰＭ（トレンチ横型ＭＯＳＦＥＴ）領域
１４ キャパシタ領域。
1 P-type Si substrate 2 P well region 4 N drain region 5 Interlayer insulating film 6 LOCOS oxide film (element isolation oxide film)
7 Gate oxide film 8 N source region 9 Gate electrode film 10 First electrode film 11 Dielectric film 12 Second electrode film 13 Insulated gate transistor region, TLPM (trench lateral MOSFET) region 14 Capacitor region

Claims (4)

半導体基板に形成されるトレンチの側壁に絶縁膜を介してゲート電極膜が形成される絶縁ゲート型トランジスタと、前記半導体基板上に素子分離領域を介して順次積層される第一電極膜、第二電極膜および該第一電極膜と第二電極膜とに挟持される誘電体膜とからなるキャパシタを備える半導体装置の製造方法において、順次処理される、前記トレンチを形成する工程と、前記素子分離領域を前記トレンチに対し離間させて形成する工程と、前記トレンチの側壁に前記絶縁膜を形成する工程、前記半導体基板表面およびトレンチ内面に第一電極膜形成用導電膜を形成する工程と、前記第一電極膜形成領域上の前記第一電極膜形成用導電膜にマスクを形成する工程と、前記第一電極膜形成用導電膜を異方性エッチングすることにより、前記第一電極膜および前記ゲート電極膜を形成する工程と、前記半導体基板表面および前記トレンチの側壁および底面に前記ゲート電極膜の表面を覆うように前記誘電体膜を形成する工程と、前記半導体基板表面および前記トレンチの側壁および底面に前記誘電体膜の表面を覆うように第二電極膜形成用導電膜を形成する工程と、該第二電極膜形成用導電膜上の前記第二電極膜形成領域上にマスクを形成する工程と、前記第二電極膜形成用導電膜を等方性エッチングして第二電極膜を形成する工程と、前記トレンチを層間絶縁膜で埋める工程と、を備えることを特徴とする半導体装置の製造方法。 An insulated gate transistor in which a gate electrode film is formed on an insulating film on a sidewall of a trench formed in a semiconductor substrate, and a first electrode film and a second electrode sequentially stacked on the semiconductor substrate through an element isolation region In a manufacturing method of a semiconductor device including a capacitor including an electrode film and a dielectric film sandwiched between the first electrode film and the second electrode film, the step of forming the trench, which is sequentially processed, and the element isolation Forming a region apart from the trench; forming the insulating film on a sidewall of the trench; forming a conductive film for forming a first electrode film on the semiconductor substrate surface and the trench inner surface; Forming a mask on the first electrode film-forming conductive film on the first electrode film-forming region, and anisotropically etching the first electrode film-forming conductive film, Forming a electrode film and the gate electrode film, and forming the dielectric film so as to cover the surface of the gate electrode film on the side walls and bottom surface of the semiconductor substrate surface and the trench, the semiconductor substrate surface and the dielectric and forming the second electrode film formation conductive film so as to cover the surface of the membrane, said second electrode film on the formation conductive film said second electrode film formation region on the sidewalls and bottom surface of the trench Forming a mask, forming a second electrode film by isotropically etching the conductive film for forming the second electrode film, and filling the trench with an interlayer insulating film. A method for manufacturing a semiconductor device. 前記トレンチを層間絶縁膜で埋める工程の後に、前記層間絶縁膜に前記トレンチ底部の一部を露出する開口部を形成する工程と、前記開口部に金属プラグを埋める工程と、を有することを特徴とする請求項１に記載の半導体装置の製造方法。   After the step of filling the trench with an interlayer insulating film, the method includes a step of forming an opening exposing a part of the bottom of the trench in the interlayer insulating film, and a step of filling a metal plug in the opening. A method for manufacturing a semiconductor device according to claim 1. 前記第一電極膜および前記第二電極膜がポリシリコンを主要成分とすることを特徴とする請求項１または２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first electrode film and the second electrode film contain polysilicon as a main component. 前記等方性エッチングが気相エッチングであることを特徴とする請求項１乃至３のいずれか一項に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein the isotropic etching is vapor phase etching.
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