CN105762187B

CN105762187B - Semiconductor device and method for manufacturing the same

Info

Publication number: CN105762187B
Application number: CN201410790105.1A
Authority: CN
Inventors: 钟汇才; 罗军; 赵劼; 赵超; 朱慧珑
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2014-12-17
Filing date: 2014-12-17
Publication date: 2020-01-03
Anticipated expiration: 2034-12-17
Also published as: CN105762187A

Abstract

A semiconductor device, comprising: a plurality of fins extending in a first direction on the substrate; a plurality of gate stacks and a plurality of contact lines extending in a second direction on the substrate and spanning the plurality of fins; the insulating layer is filled between the plurality of grid stacks and the plurality of contact lines; source and drain regions distributed in the plurality of fins and on two sides of the plurality of gate stacks; one or more contact lines are arranged between two adjacent grid electrode stacks, and the contact lines form source and drain contacts on the source and drain regions. According to the semiconductor device and the manufacturing method thereof, the sacrificial grid electrode lines and the sacrificial source drain contact lines which are arranged at intervals are formed by crossing the fin structure through the double patterning process, and the final grid electrode lines and the final source drain contact lines are filled by respectively and sequentially removing the sacrificial grid electrode lines and the sacrificial source drain contact lines through selective etching, so that the reliability of the source drain contact is improved.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a self-aligned source-drain contact FinFET and a method for manufacturing the same.

Background

As device dimensions scale down to 22nm technology and beyond, three-dimensional multi-gate devices such as fin field effect transistors (finfets) and tri-gate (tri-gate) devices have become one of the most promising new device technologies, these structures enhance gate control capability, suppress leakage and short channel effects.

For conventional processes, CMOS devices including FinFET, tri-gate devices are gate patterned and contacts are formed to achieve isolated functional devices by:

1. patterning the gate using a wire-and-cut (line-and-cut) dual-lithographic patterning technique and subsequently etching the gate stack;

2. printing parallel lines for gate patterning in one direction with uniform feature size and pitch (pitch);

3. arranging gate line ends (tips) only at predetermined mesh nodes;

4. conductive contact holes for the gate electrode and the source/drain electrodes of the device are formed by photolithography and etching after forming the inter-device insulating dielectric layer.

The above method has some advantages:

1. the photoetching suitable for a special illumination mode is simplified;

2. many proximity effects that complicate lithography, etching and OPC are eliminated.

Finfets and tri-gate devices are three-dimensional (3D) devices, unlike planar CMOS devices. Typically, semiconductor fins are formed on a bulk or SOI substrate by selective dry or wet etching, and then gate stacks are formed across the fins. The three-dimensional tri-gate transistor forms a conductive channel on all three sides of the vertical fin structure, thereby providing a "fully depleted" mode of operation. The tri-gate transistor may also have multiple fins connected together to increase the total drive capability for higher performance.

However, as FinFET devices enter 22nm technology nodes and shrink further, it is difficult to form self-aligned source and drain contacts on nanometer sized fin source and drain regions for 3D finfets, especially for SOI finfets, the spacing between the contacts and the gate is difficult to control accurately, device interconnection errors are easily caused, resulting in device failure and reduced reliability.

Disclosure of Invention

In view of the above, the present invention is directed to overcoming the above technical difficulties and improving the reliability of FinFET source-drain contact.

To this end, the present invention provides a semiconductor device comprising: a plurality of fins extending in a first direction on the substrate; a plurality of gate stacks and a plurality of contact lines extending in a second direction on the substrate and spanning the plurality of fins; the insulating layer is filled between the plurality of grid stacks and the plurality of contact lines; source and drain regions distributed in the plurality of fins and on two sides of the plurality of gate stacks; one or more contact lines are arranged between two adjacent grid electrode stacks, and the contact lines form source and drain contacts on the source and drain regions.

Wherein the substrate is a thick substrate or an SOI substrate.

Wherein each of the plurality of gate stacks comprises a gate insulation layer of a high-k material and a gate conductive layer of a metal material.

Wherein, the source and drain regions comprise metal silicide.

Wherein the plurality of gate stacks and the plurality of contact lines have the same pitch and size.

Wherein, the starting positions and/or the lengths of the plurality of gate stacks and the plurality of contact lines along the second direction are the same.

Two sides of each of the plurality of gate stacks are one of a source region or a drain region, and two sides of the plurality of contact lines are the same source region or the same drain region.

The invention also provides a semiconductor device manufacturing method, which comprises the following steps: forming a plurality of fins extending in a first direction on a substrate; forming a plurality of sacrificial gate stacks and a plurality of sacrificial contact stacks extending in a second direction on the substrate, spanning the plurality of fins; forming source and drain regions in the plurality of fins and on two sides of the plurality of sacrificial gate stacks; forming an insulating layer between the plurality of sacrificial gate stacks and the plurality of sacrificial contact stacks; selectively etching to remove the sacrificial gate stacks, leaving a first opening in the insulating layer, and filling the gate stacks in the first opening; and selectively etching to remove the sacrificial contact stacks, leaving a second opening in the insulating layer, and filling the second opening with a plurality of contact lines.

Wherein the step of forming a plurality of sacrificial gate stacks and a plurality of sacrificial contact stacks further comprises: forming a sacrificial stack on the substrate, wherein the sacrificial stack comprises a liner layer, a sacrificial layer and a cover layer, and spans and covers the fins; forming a plurality of gate masks extending in a second direction on the sacrificial stack; etching the sacrificial stack until the sacrificial layer is exposed, and leaving a plurality of cover layer lines extending along the second direction; forming one or more contact masks between the plurality of cap layer lines; the sacrificial stack is etched until the plurality of fins are exposed, leaving a plurality of sacrificial gate stacks comprised of a liner layer, a sacrificial layer, and a cap layer that are conformal to the plurality of gate masks, and a plurality of sacrificial contact stacks comprised of a liner layer and a sacrificial layer that are conformal to the contact masks.

Wherein the liner layer comprises silicon oxide, the sacrificial layer comprises amorphous silicon, polysilicon, amorphous germanium, amorphous carbon, diamond-like amorphous carbon (DLC), and combinations thereof, and the cap layer comprises silicon nitride, silicon oxynitride, and combinations thereof.

Wherein the plurality of sacrificial gate stacks and the plurality of sacrificial contact stacks have the same pitch and size, and the start positions and/or lengths along the second direction are the same.

And forming a lightly doped source drain region and/or a heavily doped source drain region by ion implantation.

Wherein the insulating layer is formed using a conformal deposition process.

Wherein the step of leaving the first opening in the insulating layer further comprises: and selectively etching the cover layer, the sacrificial layer and the liner layer of the sacrificial gate stacks in sequence until the fins are exposed, wherein the sacrificial contact stacks are protected from etching by the insulating layer.

Wherein the step of leaving the second opening in the insulating layer further comprises: and planarizing the insulating layer by CMP until the sacrificial layers of the sacrificial contact stacks are exposed, and selectively etching the sacrificial layers and the liner layers of the sacrificial contact stacks in sequence until the fins are exposed.

Wherein filling the plurality of contact lines in the second opening further comprises: forming metal silicide on the source drain region; forming a barrier layer on the metal silicide; and forming source and drain contacts on the barrier layer.

The etching process for removing the cover layer, the sacrificial layer and the liner layer by etching is selective dry etching or wet etching.

According to the semiconductor device and the manufacturing method thereof, the sacrificial grid electrode lines and the sacrificial source drain contact lines which are arranged at intervals are formed by crossing the fin structure through the double patterning process, and the final grid electrode lines and the final source drain contact lines are filled by respectively and sequentially removing the sacrificial grid electrode lines and the sacrificial source drain contact lines through selective etching, so that the reliability of the source drain contact is improved.

Drawings

The technical solution of the present invention is explained in detail below with reference to the accompanying drawings, in which:

fig. 1 to 13 are schematic views of steps of a method of manufacturing a semiconductor device according to the present invention.

Detailed Description

The features and technical effects of the technical scheme of the invention are described in detail below with reference to the accompanying drawings and in combination with exemplary embodiments, and a FinFET with improved source-drain contact reliability and a manufacturing method thereof are disclosed. It is noted that like reference numerals refer to like structures and that the terms "first", "second", "upper", "lower", and the like as used herein may be used to modify various device structures or fabrication processes. Such modifications do not imply a spatial, sequential, or hierarchical relationship to the structure or fabrication process of the modified device unless specifically stated.

It is noted that in fig. 1-13 below, the left portion of each figure shows a top view of the device, and the right portion shows a cross-sectional view taken along a section line a-a '(a section line perpendicular to the first direction in which the fins extend, i.e., along the second direction, through the gate stack) or a section line B-B' (a section line parallel to the first direction in which the fins extend, and through one fin) in the top view.

As shown in fig. 1, a semiconductor layer 2 is provided on a substrate 1. The substrate 1 is preferably an insulating substrate, for example, an insulating electrically isolating substrate such as plastic, resin, ceramic, glass, etc., and preferably has good thermal conductivity, for example, an electrically insulating, thermally conductive substrate having a heat sink or a bumped heat sink fin structure on its back surface. The semiconductor layer 2 is formed on the insulating substrate 1 by a process of PECVD, HDPCVD, MBE, ALD, evaporation, sputtering, or the like, or is attached to the insulating substrate 1 by being surface-peeled from other temporary supporting substrate (not shown) by a wafer peeling technique. The material of the semiconductor layer 2 is, for example, crystalline silicon (Si), single crystal germanium (Ge), Strained Si, silicon germanium (SiGe), SOI, GeOI, or a compound semiconductor material such as gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and a carbon-based semiconductor such as graphene, SiC, carbon nanotube, etc. The semiconductor layer 2 is preferably bulk Si/Ge or SOI/GeOI for compatibility with CMOS processes. In a preferred embodiment of the present invention, the insulating substrate 1 and the semiconductor layer 2 are and/or form part of an SOI or GeOI substrate, i.e. the insulating substrate 1 is a thin (e.g. 10-100 nm) oxide layer (buried oxide BOX) on the surface of a thick Si/Ge substrate (not shown) and the semiconductor layer 2 is a thinner top semiconductor layer (top Si layer or top Ge layer, e.g. 5-40 nm thick) on top of the oxide layer. As shown in fig. 1, at the beginning of the entire process, the semiconductor layer 2 completely covers the top surface of the insulating substrate 1. In another embodiment of the invention, the substrate 1 is a thick bulk Si substrate, such as a Si wafer, and the semiconductor layer 2 is a Si layer on the surface of the Si substrate.

As shown in fig. 2, the semiconductor layer 2 is patterned leaving a plurality of fin structures 2F parallel to each other on the substrate 1. Preferably, a hard mask layer (not shown) is formed on the semiconductor layer 2 by conventional processes of LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, etc., and the material thereof may be selected from silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, diamond-like amorphous carbon (DLC), etc., and combinations thereof. And forming photoresist of a polymer material on the hard mask layer by processes of spin coating, spray coating, screen printing and the like, and then exposing and developing by adopting a preset template to obtain a plurality of parallel photoresist lines. The hard mask layer is dry etched using the photoresist lines as a mask to form a plurality of parallel insulating material lines (extending in a first direction) on the semiconductor layer 2. For example, the length/width of the hard mask lines themselves (along the direction A-A' in the figure, i.e. along the extension direction of the final device gate stack or referred to as the second direction) is set according to the device driving capability requirement, and the pitch and the spacing between the parallel lines is 50-100 nm. Although the periodic lines are shown in the drawings, the width and pitch of the lines can be reasonably set according to the layout design requirement, that is, the line layout can be discrete and discrete. Then, using the hard mask layer pattern as a mask, the semiconductor layer 2 is anisotropically etched and stopped on the substrate 1, and a plurality of trenches distributed in parallel along the first direction and a fin 2F made of the remaining material of the semiconductor layer 2 between the trenches are formed in the semiconductor layer 2. The aspect ratio of the trench, or the aspect ratio of the fin 2F, is preferably greater than 5: 1. In an embodiment of the present invention, the etching process may be wet etching, and for the semiconductor layer 2 made of Si (single crystal Si or SOI), the etchant of the wet etching is tetramethylammonium hydroxide (TMAH) or KOH solution, and for other materials (SiGe, Ge, GaN, etc.), a combination of strong acid (e.g. sulfuric acid, nitric acid) and strong oxidant (e.g. hydrogen peroxide, deionized water containing ozone) may be used. In another embodiment of the present invention, the etching process is, for example, plasma dry etching or reactive ion etching, and the reactive gas may be a fluorocarbon-based etching gas or other halogen-based etching gas (e.g., chlorine gas, hydrogen chloride, bromine vapor, hydrogen bromide, etc.). In a preferred embodiment of the present invention, the plurality of fins 2F have the same pitch (pitch) and fin size (e.g., three-dimensional size of width, height, length, etc.). In the case that the substrate 1 is a buried oxide layer BOX in an SOI substrate, fins 2F composed of a plurality of semiconductor layers 2 are isolated and insulated from each other by the buried oxide layer 1 at the bottom; in the case where the substrate 1 is a monocrystalline silicon substrate, a silicon oxide or silicon nitride dielectric layer may additionally be deposited between the fins 2F and etched back to partially expose the fins 2F, leaving shallow trench isolation structures STI (not shown) on the substrate 1.

As shown in fig. 3, a sacrificial stack 3A is formed on the entire substrate 1, covering the surface of the substrate 1, the top surface and the sidewalls of the fin 2F, and spanning all and/or a portion of the plurality of fin structures 2F, and a plurality of gate masks 3B are formed on the sacrificial stack 3A and distributed to extend in a second direction (preferably perpendicular to the first direction). A liner layer 3A1, a sacrificial layer 3A2, and a cap layer 3A3 are sequentially formed on the substrate 1 by LPCVD, PECVD, HDPCVD, MBE, ALD, evaporation, sputtering, or the like, thereby forming a sacrificial stack 3A. A spacer layer 3a1, such as silicon oxide, is used to protect substrate 1 during subsequent etching to reduce interface defects, and preferably covers not only the surface of substrate 1, the top surface of fin 2F, but also the sidewalls of fin 2F. A sacrificial layer 3a2, such as amorphous silicon, polysilicon, amorphous germanium, amorphous carbon, diamond-like amorphous carbon (DLC), or the like, that completely fills the trenches between fins 2F, serves to define the pattern of the sacrificial lines and improve the etch selectivity to the adjacent material. The cap layer 3A3 is made of a hard material such as silicon nitride or silicon oxynitride, and is used to protect the sacrificial layer 3a2 from erosion during the subsequent etching or planarization process, so as to achieve the desired selective etching effect, and preferably planarize the cap layer. Subsequently, a plurality of gate masks 3B extending in a second direction, for example, soft masks of photoresist material formed by processes of spin coating, spray coating, screen printing, stamping, etc., are formed on top of the sacrificial stack 3A, particularly the capping layer 3A3, and then patterned into a plurality of gate mask lines 3B by DUV or EUV exposure, development; or a hard mask formed by depositing an insulating layer (preferably of a different material than the capping layer 3a3, such as amorphous silicon, amorphous carbon, silicon oxide, etc. to improve etch selectivity) and photolithography (e.g., DUV, EUV lithography)/etching. The plurality of gate masks 3B have the same line pitch and size, for example, the same width and pitch in the first direction and the same length and start position in the second direction.

As shown in fig. 4, the exposed sacrificial stack 3A is etched using the plurality of gate masks 3B as masks, removing the cap layer 3A3 not covered by the gate masks 3B. Preferably, an anisotropic dry etching process is used, for example, the fluorocarbon ratio and flow rate of the fluorocarbon-based etching gas are adjusted, the vertical etching rate and the etching selectivity (difference in etching rates of different materials) of the adjacent materials are controlled, the etching of the cap layer 3A3 made of silicon nitride and silicon oxynitride is improved, a part of the cap layer 3A3 not covered by the mask 3B is removed, and the lower sacrificial layer 3a2 is exposed for the subsequent double patterning process. Subsequently, the mask 3B is stripped by a dry (oxygen plasma etching) or wet (etching with a mixture of strong oxidizer and strong acid or base, adding organic solvent) process, leaving the cap line 3a3 conformal to the mask 3B below the original gate mask 3B as the top cap layer of the subsequent sacrificial gate stack.

As shown in fig. 5, a double patterning process is performed to form one or more contact masks 3C in parallel (i.e., extending in the second direction) between the cap layer lines 3a 3. The contact mask 3C may be a photoresist or a hard mask, similar to the gate mask 3B process and material. In a preferred embodiment of the invention, the contact mask 3C is spaced and dimensioned the same as the gate mask 3B/remaining cap layer line 3a3, e.g. equal in width and spacing in the first direction and equal in length and starting position in the second direction. The lengths of the contact mask 3C and the cap layer lines 3a3 along the second direction may be the same or very close, for example typically between 20 and 50nm, preferably 30-40 nm. It is noted that the right sides of fig. 1 to 4 are all cross-sectional views along the second direction AA, and the right sides of fig. 5 to 13 are all cross-sectional views along the first direction BB and through the fin 2F.

As shown in fig. 6, using the cap layer line 3A3 and the contact mask 3C as masks, the sacrificial layer 3a2 and the liner layer 3a1 below are sequentially etched until the fin 2F is exposed, and a sacrificial gate stack (including the cap layer line 3A3 and the sacrificial layer 3a2 and the liner layer 3a1 below and conformal thereto) and a sacrificial contact stack (including the sacrificial layer 3a2 and the liner layer 3a1 below and conformal thereto of the contact mask 3C) are formed. The etching is preferably anisotropic dry etching, such as plasma dry etching or Reactive Ion Etching (RIE) for adjusting the carbon-fluorine ratio and flow rate, or wet etching mixed with the sacrificial layer material, such as TMAH for polysilicon and amorphous silicon, or oxygen plasma dry etching for the sacrificial layer made of amorphous carbon and DLC, and the like. Since the contact mask 3C is made of a different material, such as a soft photoresist pattern, from the capping layer 3A3, the sacrificial layer 3a2, and the pad layer 3a1, the contact mask 3C is not etched during the etching process, but is stripped by a dry or wet process after the etching is completed, so that the sacrificial contact stack does not include the contact mask 3C.

As shown in fig. 7, ion implantation is performed using the plurality of sacrificial gate stacks and the plurality of sacrificial contact stacks as masks to form source and drain regions of the device in the exposed fin structure 2F of fig. 6 on both sides of the sacrificial gate stack (3A3/3a2/3a 1). Preferably, lightly doped ion implantation is performed to form lightly doped source and drain extension regions (ESD, not shown) with a small junction depth in the fin, and then heavily doped ion implantation is performed to form heavily doped source and

drain regions

2S and 2D with a large junction depth in the fin. Further, the ion implantation may be performed followed by annealing to activate the implanted impurities. The implanted ions are of the opposite type to those contained in the semiconductor layer 2 and the fin structure 2F, for example, if the substrate 1 and the semiconductor layer 2 are n-, the source and drain regions are p, p +, and vice versa. In the embodiment of the present invention, one of the source and drain regions on both sides of the sacrificial gate stack is used as a source region, the other is used as a drain region, and the source and drain regions on both sides of the sacrificial contact stack are both used as a source region or a drain region (at this time, due to activation annealing, vertically implanted impurity ions will diffuse in the fin and enter below the sacrificial contact stack and are preferably connected, as shown in the right side of fig. 7).

As shown in fig. 8, an insulating layer 4 is formed on the entire device, covering the surface of the substrate 1, the top surface and the side wall of the sacrificial gate stack (3A3/3a2/3a1), and the top surface and the side wall of the sacrificial contact stack (3a2/3a1), completely filling the gap between the two. In an embodiment of the present invention, a deposition process with a high step coverage rate, such as PECVD, HDPCVD, MBE, ALD, etc., is used to deposit an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, and parameters of the deposition process are controlled such that the insulating layer 4 is a conformally deposited layer, i.e., the insulating layer 4 completely fills the gap between the sacrificial gate stack and the sacrificial contact stack without leaving a hole. Low-k materials include, but are not limited to, organic low-k materials (e.g., aryl or multi-ring containing organic polymers), inorganic low-k materials (e.g., amorphous carbon nitride films, polycrystalline boron nitride films, fluorosilicone glass, BSG, PSG, BPSG), porous low-k materials (e.g., disiloxane (SSQ) -based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymers). After the insulating layer 4 is deposited, the insulating layer 4 is planarized using a planarization process such as CMP or etchback until the sacrificial gate stack (e.g., the cap layer 3a3 on top of it) is exposed, at which time the sacrificial contact stack is not exposed but is completely covered by the insulating layer 4. The deposition step of the insulating layer 4 is similar to the process of forming a device side wall and forming a device interlayer dielectric layer (ILD), but different from the traditional devices, the FinFET disclosed by the invention does not need an additional device side wall, and the insulating layer 4 plays a role in electrical isolation between the side surface of the grid and the contact of the source and the drain besides limiting the position of a final grid stacking line and the position of a source and drain contact line to enable the final grid stacking line and the source and drain contact line to be formed in a self-alignment manner, so that the process steps are saved, and the manufacturing precision of the device is.

As shown in fig. 9, the etching removes the plurality of sacrificial gate stacks, leaving first openings or trenches 4T1 in insulating layer 4 until fin 2F is exposed. First, the exposed cap layer 3A3 on the top of the multiple sacrificial gate stacks 3A is selectively etched away, for example, the proportion and flow rate of etching gas in plasma dry etching or RIE are adjusted, so that the etching selectivity of each layer of material is high (the etching rate is at least 5 times higher than that of other adjacent materials), or wet etching is selected for each layer of material, for example, a mixed solution of hot phosphoric acid for silicon nitride, a strong oxidant (deionized water containing ozone) and hydrogen peroxide (hydrofluoric acid, hydrochloric acid) for silicon oxynitride and the like, KOH, TMAH for polysilicon, amorphous silicon and the like, oxygen plasma dry etching is used for a sacrificial layer of amorphous carbon and DLC, and HF and BOE etching are used for a liner layer of silicon oxide. In the etching step shown in fig. 9, since the tops of the plurality of sacrificial contact stacks are not exposed but covered and protected by the insulating layer 4, the sacrificial layers 3a2 and the pad layers 3a1 of the sacrificial contact lines are not eroded.

As shown in fig. 10, a final gate stack 5G is formed in the first opening or trench 4T 1. The gate stack 5G, including the gate insulation 5G1 and the gate conductive layer 5G2, is conformally deposited by PECVD, HDPCVD, MBE, ALD, magnetron sputtering, or like processes. The gate insulating layer 5G1 is preferably silicon oxide, nitrogen-doped silicon oxide, silicon nitride, or other high-K material including, but not limited to, materials including materials selected from HfO₂、HfSiO_x、HfSiON、HfAlO_x、HfTaO_x、HfLaO_x、HfAlSiO_x、HfLaSiO_xThe hafnium-based material (wherein each material has a reasonable oxygen atom content x, such as 1-6 and not limited to an integer, according to the distribution ratio and chemical valence of the multi-metal component), or comprises ZrO₂、La₂O₃、LaAlO₃、TiO₂、Y₂O₃Or a rare earth based high-K dielectric material of (2), or including Al₂O₃And a composite layer of the above materials. The gate conductive layer 5G2 can be polysilicon, poly SiGe,Or a metal, wherein the metal may include a simple metal such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, or an alloy of these metals, or a nitride of these metals, and the gate conductive layer 5G2 may be further doped with an element such as C, F, N, O, B, P, As to adjust a work function. A nitride barrier layer (not shown) is preferably formed between the gate conductive layer 5G2 and the gate insulating layer 5G1 by PVD, CVD, ALD, or other conventional methods, and the barrier layer is preferably M_xN_y、M_xSi_yN_z、M_xAl_yN_z、M_aAl_xSi_yN_zWherein M is Ta, Ti, Hf, Zr, Mo, W or other elements. More preferably, the gate conductive layer 5G2 and the barrier layer are not only stacked in a multi-layer structure, but also mixed implantation doping layer structure, that is, the materials constituting the gate conductive layer 5G2 and the barrier layer are deposited on the gate insulating layer 5G1 at the same time, so that the gate conductive layer includes the materials of the barrier layer. As shown in fig. 10, the gate insulating layer 5G1 surrounds the bottom and sidewalls of the gate conductive layer 5G 2. Preferably, the gate stack 5G is planarized using CMP, etch back, etc. until the top of the insulating layer 4 is exposed.

As shown in fig. 11, the device is planarized until the sacrificial layer 3a2 of the sacrificial contact stack is exposed.

As shown in fig. 12, the sacrificial contact stacks, i.e., the sacrificial layer 3a2 and the liner layer 3a1, are selectively etched away until the source/drain regions 2S/2D in the fin 2F are exposed. The sacrificial layer 3B2 and the pad layer 3B1 are removed in this order by dry etching or wet etching, leaving a second opening 4T2 serving as a source-drain contact opening, the same as or similar to the step shown in fig. 9. In a preferred embodiment of the present invention, the sacrificial layer 3a2 of polysilicon or amorphous silicon is removed by KOH or TMAH wet etching, and the pad layer 3a1 of silicon oxide is removed by HF or BOE etching.

As shown in fig. 13, similarly to fig. 10, the second opening 4T2 is filled with metal to form a contact line 6C. Preferably, a thin metal layer is deposited on the surface of the source and drain regions and annealed to form metal silicide 6C1, so as to reduce the contact resistance of the source and the drain. Then, optionally, a barrier layer or adhesion layer (not shown) selected from Ti, Ta, TiN, TaN and combinations thereof is formed on the metal silicide 6C1 by PECVD, MOCVD, MBE, ALD, evaporation, sputtering for blocking diffusion of upper layer metal (e.g., Al, etc.) into the source and drain regions from affecting device performance and simultaneously enhancing adhesion with the metal silicide 6C 1. Next, a metal, metal alloy or metal nitride is formed in the remaining portions of opening 4T2 to form source drain contact 6C2, wherein the metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, etc., and combinations thereof. Preferably, CMP is performed to planarize the contact 6C2 until the top of the insulating layer 4 is exposed. As shown in the left side of fig. 13, metal is formed on the substrate 1 as well as filling above the source and drain regions, constituting a contact line 6C.

The resulting FinFET device is shown in fig. 13, and includes a plurality of fins 2F extending in a first direction on a substrate 1, a plurality of gate stacks 5G and a plurality of contact lines 6C extending in a second direction on the substrate 1 and crossing the plurality of fins 2F, source and

drain regions

2S and 2D in the plurality of fins 2F and distributed on both sides of the plurality of gate stacks 5G, one or more contact lines 6C between two adjacent gate stacks 5G, and the contact lines 6C forming source and drain contacts on the source and drain regions. Other specific structures and materials and corresponding forming processes have been listed in the above description with reference to the drawings, and are not described herein again.

While the invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the disclosed device structure and its method of manufacture will include all embodiments falling within the scope of the present invention.

Claims

1. A semiconductor device manufacturing method, comprising:

forming a plurality of fins extending in a first direction on a substrate;

forming a plurality of sacrificial gate stacks and a plurality of sacrificial contact stacks extending in a second direction on the substrate, spanning the plurality of fins, each sacrificial gate stack and each sacrificial contact stack having equal widths in the first direction;

forming source and drain regions in the plurality of fins and on two sides of the plurality of sacrificial gate stacks;

forming an insulating layer between the plurality of sacrificial gate stacks and the plurality of sacrificial contact stacks;

selectively etching to remove the sacrificial gate stacks, leaving a first opening in the insulating layer, and filling the gate stacks in the first opening;

and selectively etching to remove the sacrificial contact stacks, leaving a second opening in the insulating layer, filling the second opening with a plurality of contact lines, and leaving no additional device side wall between the gate stacks and the contact lines.

2. The semiconductor device manufacturing method of claim 1, wherein the step of forming a plurality of sacrificial gate stacks and a plurality of sacrificial contact stacks further comprises:

forming a sacrificial stack on the substrate, wherein the sacrificial stack comprises a liner layer, a sacrificial layer and a cover layer, and spans and covers the fins;

forming a plurality of gate masks extending in a second direction on the sacrificial stack;

etching the sacrificial stack until the sacrificial layer is exposed, and leaving a plurality of cover layer lines extending along the second direction;

forming one or more contact masks between the plurality of cap layer lines;

the sacrificial stack is etched until the plurality of fins are exposed, leaving a plurality of sacrificial gate stacks comprised of a liner layer, a sacrificial layer, and a cap layer that are conformal to the plurality of gate masks, and a plurality of sacrificial contact stacks comprised of a liner layer and a sacrificial layer that are conformal to the contact masks.

3. The manufacturing method of a semiconductor device according to claim 2, wherein the liner layer comprises silicon oxide, the sacrificial layer comprises amorphous silicon, polysilicon, amorphous germanium, amorphous carbon, diamond-like amorphous carbon (DLC), and combinations thereof, and the cap layer comprises silicon nitride, silicon oxynitride, and combinations thereof.

4. The manufacturing method of a semiconductor device according to claim 1, wherein the plurality of sacrificial gate stacks and the plurality of sacrificial contact stacks have the same pitch, and start positions and/or lengths in the second direction are the same.

5. The manufacturing method of a semiconductor device according to claim 1, wherein the ion implantation forms lightly doped source-drain regions and/or heavily doped source-drain regions.

6. A method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer is formed by a conformal deposition process.

7. The manufacturing method of a semiconductor device according to claim 2, wherein the step of leaving the first opening in the insulating layer further comprises: and selectively etching the cover layer, the sacrificial layer and the liner layer of the sacrificial gate stacks in sequence until the fins are exposed, wherein the sacrificial contact stacks are protected from etching by the insulating layer.

8. The manufacturing method of a semiconductor device according to claim 1, wherein each of the plurality of gate stacks comprises a gate insulating layer of a high-k material and a gate conductive layer of a metal material.

9. A method for manufacturing a semiconductor device according to claim 2, wherein the step of leaving the second opening in the insulating layer further comprises: and planarizing the insulating layer by CMP until the sacrificial layers of the sacrificial contact stacks are exposed, and selectively etching the sacrificial layers and the liner layers of the sacrificial contact stacks in sequence until the fins are exposed.

10. The semiconductor device manufacturing method according to claim 1, wherein the filling of the plurality of contact lines in the second opening further comprises: forming metal silicide on the source drain region; forming a barrier layer on the metal silicide; and forming source and drain contacts on the barrier layer.

11. The manufacturing method of a semiconductor device according to claim 7 or 9, wherein the etching process for etching away the cap layer, the sacrificial layer, and the pad layer is selective dry etching or wet etching.