JP4769784B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4769784B2 JP4769784B2 JP2007287203A JP2007287203A JP4769784B2 JP 4769784 B2 JP4769784 B2 JP 4769784B2 JP 2007287203 A JP2007287203 A JP 2007287203A JP 2007287203 A JP2007287203 A JP 2007287203A JP 4769784 B2 JP4769784 B2 JP 4769784B2
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Description
(1)本発明は、ハイサイドスイッチとして用いられる第1のパワートランジスタを有する半導体装置であって、第1のパワートランジスタのソース端子は、第1の外部接続端子と第2の外部接続端子とにそれぞれ接続され、第1の外部接続端子、および第2の外部接続端子は、それぞれ異なる経路で分離して形成されているものである。
(2)本発明は、ハイサイドスイッチとして用いられる第1のパワートランジスタと、ローサイドスイッチとして用いられる第2のパワートランジスタと、第1、および第2のパワートランジスタを駆動するドライバとを備えた半導体装置であり、第1のパワートランジスタのソース端子は、第2のパワートランジスタのドレインと接続される第1の外部接続端子とドライバに備えられたソース側接続端子とにそれぞれ異なる経路で接続されたものである。
(3)また、本発明は、ハイサイドスイッチとして用いられる第1のパワートランジスタと、ローサイドスイッチとして用いられる第2のパワートランジスタと、第1、および第2のパワートランジスタを駆動するドライバ、およびドライバを駆動制御する制御信号を発生する制御部とよりなるドライバコントローラとを備えた半導体装置であり、第1のパワートランジスタのソース端子は、第2のパワートランジスタのドレインと接続される第1の外部接続端子とドライバコントローラに備えられたソース側接続端子とにそれぞれ異なる経路で接続されたものである。
(4)さらに、本発明は、ハイサイドスイッチとして用いられる第1のパワートランジスタと、第1のパワートランジスタを駆動するドライバと、平滑用のコイルと、第1のパワートランジスタ、ドライバ、およびコイルを実装するプリント配線基板とを備えた電源システムであり、第1のパワートランジスタのソース端子は、異なる経路で分離してそれぞれ形成された第1の外部接続端子と第2の外部接続端子とに接続されており、プリント配線基板は、第1のパワートランジスタの第1の外部接続端子がドライバに接続される第1の配線と、第1のパワートランジスタの第2の外部接続端子とコイルの接続部とが接続される第2の配線とを有し、第1の配線と第2の配線とは、異なる経路でそれぞれ形成されているものである。
(5)また、本発明は、ハイサイドスイッチとして用いられる第1のパワートランジスタとローサイドスイッチとして用いられる第2のパワートランジスタとよりなるパワーモジュールと、パワーモジュールを駆動するドライバと、平滑用のコイルと、パワーモジュール、ドライバ、およびコイルを実装するプリント配線基板とを備えた電源システムであり、第1のパワートランジスタのソース端子は、異なる経路で分離してそれぞれ形成された第1の外部接続端子と第2の外部接続端子とに接続されており、プリント配線基板は、第1のパワートランジスタの第1の外部接続端子がドライバに接続される第1の配線と、第1のパワートランジスタの第2の外部接続端子とコイルの接続部とが接続される第2の配線とを有し、第1の配線と第2の配線とは異なる経路でそれぞれ形成されているものである。
(6)さらに、本発明は、電源システムに使われる半導体装置であって、該半導体装置は、制御電極と、外部端子に結合される第1のソース電極と、第2のソース電極とを有し、電源システムのハイサイドスイッチとして使われるパワートランジスタと、制御電極と第2のソース電極とに結合され、制御電極と第2のソース電極との間に、該パワートランジスタを制御する制御電圧を出力するドライバとを具備するものである。
図1は、本発明の実施の形態1によるパワーMOS−FETの構成の一例を示す説明図、図2は、図1のパワーMOS−FETの断面図、図3は、図1のパワーMOS−FETにおけるチップレイアウトの一例を示す説明図、図4は、図1のパワーMOS−FETを用いてDC/DCコンバータを構成したプリント配線基板の実装例を示す説明図、図5は、図4のプリント配線基板に実装されたDC/DCコンバータの等価回路図、図6は、図1のパワーMOS−FETの他の構成例を示す説明図、図7は、図6のパワーMOS−FETの断面図、図8は、図7のパワーMOS−FETの他の構成例を示す説明図、図9は、図8のパワーMOS−FETの断面図、図23は、図5のDC/DCコンバータ回路における損失の寄生インダクタンス依存性を示す説明図である。
図10は、本発明の実施の形態2によるパワーICの構成の一例を示す説明図、図11は、図10のパワーICの断面図、図12は、図10のパワーICを用いてDC/DCコンバータを構成したプリント配線基板の実装例を示す説明図である。
図13は、本発明の実施の形態3によるパワーICの構成の一例を示す説明図、図14は、図13のパワーICの断面図、図15は、図13のパワーICを用いて絶縁型DC/DCコンバータの構成例を示す回路図、図16は、図13のパワーICの他の構成例を示す説明図、図17は、図16のパワーICの断面図である。
図18は、本発明の実施の形態4によるパワーICの構成の一例を示す回路図、図19は、図18のパワーICの構成を示す説明図、図20は、図18のパワーICの他の構成例を示す説明図である。
2 リードフレーム
2a ダイパッド
3 半導体チップ
4 パッケージ
5 パワーMOS−FET(第2のパワートランジスタ)
6 コントロールIC
7 コイル
8〜10 金属板
11 はんだボール
12 金属板
13 パワーIC(パワーモジュール)
14,15 リードフレーム
14a,15a ダイパッド
16,17 半導体チップ
18 パッケージ
19 パワーIC(パワーモジュール)
19a〜19d パワーIC(パワーモジュール)
20,21 リードフレーム
20a,21a ダイパッド
22,23 半導体チップ
24 パッケージ
25,25a コントロールIC
26〜28 コンデンサ
28a コイル
29 電源トランス
30 金属板
31 はんだボール
32 パワーIC(パワーモジュール)
33 パワーMOS−FET
34 パワーMOS−FET
35 ドライバIC
35a ドライバ
35b ドライバ
36〜38 リードフレーム
36a,37a,38a ダイパッド
39〜41 半導体チップ
39a,40a,40b,41a,41b 電極部
50 DC/DCコンバータ
51 ハイサイドスイッチ
52 ローサイドスイッチ
ST ソース端子
GT ゲート端子
DT ドレイン端子
HK 半導体基板
Z 絶縁膜
LS1 アウタリード(第1の外部接続端子)
LS2 アウタリード(第2の外部接続端子)
LS3 アウタリード(第1の外部接続端子)
LS4 アウタリード(第2の外部接続端子)
LS5,LS6 アウタリード
LD1〜LD3 アウタリード
LG アウタリード
G アウタリード
V アウタリード
D アウタリード
SIN アウタリード
W ボンディングワイヤ
H1 パターン配線
H2 パターン配線
H3 パターン配線(第2の配線)
H4 パターン配線(第1の配線)
H5 パターン配線
H6 パターン配線
H7 パターン配線
H8 パターン配線
H9 パターン配線(第2の配線)
H10 パターン配線(第1の配線)
H11 パターン配線
H12 パターン配線
GND1 接地端子
VDD 電源電圧端子
IN 制御信号入力端子
OUT 出力端子
GND ソース側接地端子
BOOT ブート端子
GH,GL 電圧確認用端子
Vint 入力電圧端子
LX 電圧出力端子
Claims (3)
- 第1チップ搭載部、第2チップ搭載部及び第3チップ搭載部と、
前記第1、第2及び第3チップ搭載部の周囲に配置された複数の外部端子と、
前記第1チップ搭載部上に配置され、第1電界効果トランジスタを有する第1半導体チップと、
前記第2チップ搭載部上に配置され、第2電界効果トランジスタを有する第2半導体チップと、
前記第3チップ搭載部上に配置され、前記第1及び第2電界効果トランジスタの動作を制御する制御回路を含む第3半導体チップと、
前記第1、第2及び第3半導体チップと、前記第1、第2及び第3チップ搭載部と、前記複数の外部端子の一部を封止する封止樹脂とを有し、
前記複数の外部端子は、入力用電源電位を供給する第1電源端子と、前記入力用電源電位よりも低い電位を供給する第2電源端子と、前記第3半導体チップの制御回路を制御する信号端子と、出力用電源電位を外部に出力する出力端子とを有し、
前記第1電界効果トランジスタは、そのソース・ドレイン経路が前記第1電源端子と前記出力端子との間に直列接続され、
前記第2電界効果トランジスタは、そのソース・ドレイン経路が前記出力端子と前記第2電源端子との間に直列接続され、
前記第3半導体チップの制御回路は、前記信号端子に入力された制御信号によって、前記第1及び第2電界効果トランジスタのそれぞれのゲートを制御し、
前記制御回路は、前記第1電界効果トランジスタのゲートを駆動する第1ドライバと、前記第2電界効果トランジスタのゲートを駆動する第2ドライバと、を含み、
前記第1電界効果トランジスタのソース端子の電極と前記第1ドライバのソース側接地端子の電極とが、金属配線によって接続されることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1チップ搭載部、前記第2チップ搭載部及び前記第3チップ搭載部は、前記封止樹脂から露出することを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記金属配線は、ワイヤ又は金属板であることを特徴とする半導体装置。
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JP2013026342A (ja) * | 2011-07-19 | 2013-02-04 | Sanken Electric Co Ltd | 窒化物半導体装置 |
JP6520437B2 (ja) * | 2015-06-12 | 2019-05-29 | 富士電機株式会社 | 半導体装置 |
FR3055496B1 (fr) * | 2016-08-26 | 2018-09-28 | Alstom Transport Technologies | Appareil de commutation electrique comportant un dispositif d'interconnexion electrique ameliore |
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