JP7199214B2 - 半導体装置および電力変換装置 - Google Patents
半導体装置および電力変換装置 Download PDFInfo
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- JP7199214B2 JP7199214B2 JP2018235262A JP2018235262A JP7199214B2 JP 7199214 B2 JP7199214 B2 JP 7199214B2 JP 2018235262 A JP2018235262 A JP 2018235262A JP 2018235262 A JP2018235262 A JP 2018235262A JP 7199214 B2 JP7199214 B2 JP 7199214B2
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- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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Description
図9は、半導体装置A10の第1変形例にかかる半導体装置A11を示している。図9は、半導体装置A11を示す平面図であって、封止樹脂30を想像線で示している。半導体装置A11は、半導体装置A10と比較して、リードフレーム50が、さらに第7リード57および第8リード58を備えている点で異なる。
図10および図11は、半導体装置A10の第2変形例にかかる半導体装置A12を示している。図10は、半導体装置A12を示す平面図であって、封止樹脂30を想像線で示している。図11は、半導体装置A12を示す側面図であって、x1方向側からx2方向を見たときの側面(左側面)を示している。半導体装置A12は、半導体装置A10と比較して、第1リード51および第2リード52の構成が異なる。
図12および図13は、半導体装置A10の第3変形例にかかる半導体装置A13を示している。図12は、半導体装置A14を示す斜視図である。図13は、半導体装置A13を示す断面図であって、図5に示す半導体装置A10の断面に相当する。半導体装置A13は、封止樹脂30およびリードフレーム50において、窪んだ部分がある点で異なる。
図15および図16は、第2実施形態にかかる半導体装置A20を示している。図15は、半導体装置A20を示す斜視図である。図16は、半導体装置A20を示す平面図であって、封止樹脂30を想像線で示している。
図18は、第2実施形態の変形例にかかる半導体装置A21を示している。図18は、半導体装置A21を示す平面図であって、封止樹脂30を想像線で示している。半導体装置A21は、半導体装置A20と比較して、第1リード51および第3リード53の構成がそれぞれ異なる。
図19は、第3実施形態にかかる半導体装置A30を示している。図19は、半導体装置A30を示す平面図であって、封止樹脂30を想像線で示している。
[付記1]
第1電極および第2電極を有する第1半導体素子と、
第3電極および第4電極を有する第2半導体素子と、
前記第1半導体素子および前記第2半導体素子を覆う封止樹脂と、
前記第1電極に導通し、前記封止樹脂から露出する第1端子部と、
前記第2電極に導通し、前記封止樹脂から露出する第2端子部と、
前記第3電極に導通し、前記封止樹脂から露出する第3端子部と、
前記第4電極に導通し、前記封止樹脂から露出する第4端子部と、
前記第1半導体素子が搭載された第1アイランド部と、
前記第2半導体素子が搭載された第2アイランド部と、
を備えており、
第1方向に見て、前記第1方向に直交する第2方向に沿う第1仮想線と、前記第1方向および前記第2方向の双方に直交する第3方向に沿う第2仮想線とによって分割される4象限を定義し、
前記第1端子部が配置される領域を第1象限として、前記第1象限の前記第2方向の隣を第2象限、前記第2象限の前記第3方向の隣であって前記第1象限の対角である第3象限、前記第1象限の前記第3方向の隣かつ前記第3象限の前記第2方向の隣を第4象限と定義した場合、
前記第2端子部が前記第2象限に配置され、前記第3端子部が前記第3象限に配置され、前記第4端子部が前記第4象限に配置される、ことを特徴とする半導体装置。
[付記2]
前記封止樹脂は、前記第1方向に見て、各々が前記第2方向に沿って延びる一対の第1端縁と、各々が前記第3方向に沿って延びる一対の第2端縁とを有している、付記1に記載の半導体装置。
[付記3]
前記第1仮想線は、前記第2端縁の中央を通り、
前記第2仮想線は、前記第1端縁の中央を通る、付記2に記載の半導体装置。
[付記4]
前記第1半導体素子と前記第1アイランド部とを接合する第1導電性接合材をさらに備えており、
前記第1半導体素子は、前記第1方向において、互いに反対側を向く第1主面および第1裏面を有しており、
前記第1電極は、前記第1裏面において露出し、
前記第2電極は、前記第1主面において露出しており、
前記第1電極と前記第1アイランド部とが前記第1導電性接合材を介して導通しており、
前記第1端子部と前記第1アイランド部とが繋がっている、付記2または付記3に記載の半導体装置。
[付記5]
前記第2半導体素子と前記第2アイランド部とを接合する第2導電性接合材をさらに備えており、
前記第2半導体素子は、前記第1方向において、互いに反対側を向く第2主面および第2裏面を有しており、
前記第3電極は、前記第2裏面において露出し、
前記第4電極は、前記第2主面において露出しており、
前記第3電極と前記第2アイランド部とが前記第2導電性接合材を介して導通しており、
前記第3端子部と前記第2アイランド部とが繋がっている、付記4に記載の半導体装置。
[付記6]
前記第1アイランド部と前記第2アイランド部とは、前記第3方向に並んでいる、付記5に記載の半導体装置。
[付記7]
前記第1半導体素子は、前記第1方向に見て、前記第1アイランド部のうち、前記第2方向において前記第2端子部が配置されている側に、実装されており、
前記第2半導体素子は、前記第1方向に見て、前記第2アイランド部のうち、前記第2方向において前記第4端子部が配置されている側に、実装されている、付記6に記載の半導体装置。
[付記8]
前記第1端子部と前記第2端子部とは、前記第2方向に見て重なり、
前記第3端子部と前記第4端子部とは、前記第2方向に見て重なる、付記6または付記7に記載の半導体装置。
[付記9]
各々が前記封止樹脂から露出する第5端子部および第6端子部をさらに備えており、
前記第1半導体素子は、第5電極をさらに有しており、
前記第2半導体素子は、第6電極をさらに有しており、
前記第5端子部は、前記第5電極に導通し、
前記第6端子部は、前記第6電極に導通する、付記8に記載の半導体装置。
[付記10]
前記第5電極は、前記第1主面において露出し、
前記第6電極は、前記第2主面において露出する、付記9に記載の半導体装置。
[付記11]
前記第1アイランド部は、前記第3方向に見て、前記第1端子部と前記第2端子部との間に配置されており、
前記第2アイランド部は、前記第3方向に見て、前記第3端子部と前記第2端子部との間に配置されている、付記10に記載の半導体装置。
[付記12]
前記第1端子部と前記第4端子部とは、前記一対の第2端縁の一方において露出しており、
前記第2端子部と前記第3端子部とは、前記一対の第2端縁の他方において露出している、付記11に記載の半導体装置。
[付記13]
前記第1端子部と前記第4端子部とは、前記第3方向に見て重なり、
前記第2端子部と前記第3端子部とは、前記第3方向に見て重なる、付記12に記載の半導体装置。
[付記14]
前記第5端子部は、前記第3方向に見て、前記第2端子部および前記第3端子部に重なり、
前記第6端子部は、前記第3方向に見て、前記第1端子部および前記第4端子部に重なる、付記13に記載の半導体装置。
[付記15]
前記第2端子部は、前記第3端子部と前記第5端子部との間に配置されており、
前記第4端子部は、前記第1端子部と前記第6端子部との間に配置されている、付記14に記載の半導体装置。
[付記16]
前記第1端子部および前記第2端子部はともに、前記第3方向に見て、前記第1アイランド部に重なり、
前記第3端子部および前記第4端子部はともに、前記第3方向に見て、前記第1アイランド部に重なる、付記10に記載の半導体装置。
[付記17]
前記第1端子部と前記第2端子部とは、前記一対の第1端縁の一方において露出しており、
前記第3端子部と前記第4端子部とは、前記一対の第1端縁の他方において露出している、付記16に記載の半導体装置。
[付記18]
前記第1端子部と前記第2端子部とは、前記第2方向に見て重なり、
前記第3端子部と前記第4端子部とは、前記第2方向に見て重なる、付記17に記載の半導体装置。
[付記19]
前記第5端子部は、前記第2方向に見て、前記第1端子部および前記第2端子部に重なり、
前記第6端子部は、前記第2方向に見て、前記第3端子部および前記第4端子部に重なる、付記18に記載の半導体装置。
[付記20]
前記第5端子部は、前記第3方向に見て、前記第1端子部と前記第2端子部との間に配置され、
前記第6端子部は、前記第3方向に見て、前記第3端子部と前記第4端子部との間に配置されている、付記19に記載の半導体装置。
[付記21]
前記第1半導体素子および前記第2半導体素子はともに、スイッチング素子である、付記1ないし付記20のいずれかに記載の半導体装置。
[付記22]
前記スイッチング素子は、MOSFETである、付記21に記載の半導体装置。
[付記23]
前記第1電極および前記第3電極はそれぞれ、ドレイン電極であり、
前記第2電極および前記第4電極はそれぞれ、ソース電極である、付記22に記載の半導体装置。
[付記24]
付記1ないし付記23のいずれかに記載の半導体装置と、
一端が前記第1端子部に接続され、他端が前記第4端子部に接続され、前記第1半導体素子の前記第1電極と前記第2半導体素子の前記第4電極との間に電圧を印加するコンデンサと、
前記第1半導体素子の前記第2電極と前記第2半導体素子の前記第3電極との接続点に接続され、前記半導体装置からの出力電圧を平滑化するインダクタと、
前記第1半導体素子および前記第2半導体素子それぞれのオン状態とオフ状態との切り替えを制御するドライブ回路と、
少なくとも、前記半導体装置、前記コンデンサおよび前記インダクタを実装する回路基板と、を備えることを特徴とする電力変換装置。
10,20:半導体素子
101,201:主面
102,202:裏面
11,21:ソース電極
12,22:ゲート電極
13,23:ドレイン電極
30 :封止樹脂
301a,301b:第1端縁
302a,302b:第2端縁
31 :樹脂主面
32 :樹脂裏面
331 :樹脂側面
332 :樹脂側面
333 :樹脂側面
334 :樹脂側面
309 :凹部
40 :ボンディングワイヤ
41 :第1ワイヤ
42 :第2ワイヤ
43 :第3ワイヤ
44 :第4ワイヤ
50 :リードフレーム
51 :第1リード
511 :アイランド部
512 :端子部
513 :連結部
514 :延出部
52 :第2リード
521 :パッド部
522 :端子部
523 :連結部
53 :第3リード
531 :アイランド部
532 :端子部
533 :連結部
534 :延出部
54 :第4リード
541 :パッド部
542 :端子部
543 :連結部
55 :第5リード
551 :パッド部
552 :端子部
56 :第6リード
561 :パッド部
562 :端子部
57 :第7リード
58 :第8リード
509 :凹部
61 :導電性接合材
62 :導電性接合材
B1,B2:電力変換装置
BC :回路基板
71 :第1配線パターン
72 :第2配線パターン
73 :第3配線パターン
74 :第4配線パターン
75 :第5配線パターン
81,82:電子部品
C1,C2:コンデンサ
Dr :ドライブ回路
L1 :インダクタ
T1~T4,T51~T56:端子
Claims (11)
- 第1電極および第2電極を有する第1半導体素子と、
第3電極および第4電極を有する第2半導体素子と、
前記第1半導体素子および前記第2半導体素子を覆う封止樹脂と、
前記第1電極に導通し、前記封止樹脂から露出する第1端子部と、
前記第2電極に導通し、前記封止樹脂から露出する第2端子部と、
前記第3電極に導通し、前記封止樹脂から露出する第3端子部と、
前記第4電極に導通し、前記封止樹脂から露出する第4端子部と、
前記第1半導体素子が搭載された第1アイランド部と、
前記第2半導体素子が搭載された第2アイランド部と、
前記第1半導体素子と前記第1アイランド部とを接合する第1導電性接合材と、
前記第2半導体素子と前記第2アイランド部とを接合する第2導電性接合材と、
各々が前記封止樹脂から露出する第5端子部および第6端子部と、
を備えており、
第1方向に見て、前記第1方向に直交する第2方向に沿う第1仮想線と、前記第1方向および前記第2方向の双方に直交する第3方向に沿う第2仮想線とによって分割される4象限を定義し、
前記第1端子部が配置される領域を第1象限として、前記第1象限の前記第2方向の隣を第2象限、前記第2象限の前記第3方向の隣であって前記第1象限の対角である第3象限、前記第1象限の前記第3方向の隣かつ前記第3象限の前記第2方向の隣を第4象限と定義した場合、
前記第2端子部が前記第2象限に配置され、前記第3端子部が前記第3象限に配置され、前記第4端子部が前記第4象限に配置される、
前記封止樹脂は、前記第1方向に見て、各々が前記第2方向に沿って延びる一対の第1端縁と、各々が前記第3方向に沿って延びる一対の第2端縁とを有しており、
前記第1半導体素子は、前記第1方向において、互いに反対側を向く第1主面および第1裏面を有しており、
前記第1電極は、前記第1裏面において露出し、
前記第2電極は、前記第1主面において露出しており、
前記第1電極と前記第1アイランド部とが前記第1導電性接合材を介して導通しており、
前記第1端子部と前記第1アイランド部とが繋がっており、
前記第2半導体素子は、前記第1方向において、互いに反対側を向く第2主面および第2裏面を有しており、
前記第3電極は、前記第2裏面において露出し、
前記第4電極は、前記第2主面において露出しており、
前記第3電極と前記第2アイランド部とが前記第2導電性接合材を介して導通しており、
前記第3端子部と前記第2アイランド部とが繋がっており、
前記第1アイランド部と前記第2アイランド部とは、前記第3方向に並んでおり、
前記第1端子部と前記第2端子部とは、前記第2方向に見て重なり、
前記第3端子部と前記第4端子部とは、前記第2方向に見て重なり、
前記第1半導体素子は、第5電極をさらに有しており、
前記第2半導体素子は、第6電極をさらに有しており、
前記第5端子部は、前記第5電極に導通し、
前記第6端子部は、前記第6電極に導通し、
前記第5電極は、前記第1主面において露出し、
前記第6電極は、前記第2主面において露出し、
前記第1端子部および前記第2端子部はともに、前記第3方向に見て、前記第1アイランド部に重なり、
前記第3端子部および前記第4端子部はともに、前記第3方向に見て、前記第1アイランド部に重なる、
ことを特徴とする半導体装置。 - 前記第1仮想線は、前記第2端縁の中央を通り、
前記第2仮想線は、前記第1端縁の中央を通る、
請求項1に記載の半導体装置。 - 前記第1半導体素子は、前記第1方向に見て、前記第1アイランド部のうち、前記第2方向において前記第2端子部が配置されている側に、実装されており、
前記第2半導体素子は、前記第1方向に見て、前記第2アイランド部のうち、前記第2方向において前記第4端子部が配置されている側に、実装されている、
請求項1または請求項2に記載の半導体装置。 - 前記第1端子部と前記第2端子部とは、前記一対の第1端縁の一方において露出しており、
前記第3端子部と前記第4端子部とは、前記一対の第1端縁の他方において露出している、
請求項1ないし請求項3のいずれか一項に記載の半導体装置。 - 前記第1端子部と前記第2端子部とは、前記第2方向に見て重なり、
前記第3端子部と前記第4端子部とは、前記第2方向に見て重なる、
請求項4に記載の半導体装置。 - 前記第5端子部は、前記第2方向に見て、前記第1端子部および前記第2端子部に重なり、
前記第6端子部は、前記第2方向に見て、前記第3端子部および前記第4端子部に重なる、
請求項5に記載の半導体装置。 - 前記第5端子部は、前記第3方向に見て、前記第1端子部と前記第2端子部との間に配置され、
前記第6端子部は、前記第3方向に見て、前記第3端子部と前記第4端子部との間に配置されている、
請求項6に記載の半導体装置。 - 前記第1半導体素子および前記第2半導体素子はともに、スイッチング素子である、
請求項1ないし請求項7のいずれか一項に記載の半導体装置。 - 前記スイッチング素子は、MOSFETである、
請求項8に記載の半導体装置。 - 前記第1電極および前記第3電極はそれぞれ、ドレイン電極であり、
前記第2電極および前記第4電極はそれぞれ、ソース電極である、
請求項9に記載の半導体装置。 - 請求項1ないし請求項10のいずれか一項に記載の半導体装置と、
一端が前記第1端子部に接続され、他端が前記第4端子部に接続され、前記第1半導体素子の前記第1電極と前記第2半導体素子の前記第4電極との間に電圧を印加するコンデンサと、
前記第1半導体素子の前記第2電極と前記第2半導体素子の前記第3電極との接続点に接続され、前記半導体装置からの出力電圧を平滑化するインダクタと、
前記第1半導体素子および前記第2半導体素子それぞれのオン状態とオフ状態との切り替えを制御するドライブ回路と、
少なくとも、前記半導体装置、前記コンデンサおよび前記インダクタを実装する回路基板と、を備える、
ことを特徴とする電力変換装置。
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JP2007073581A (ja) | 2005-09-05 | 2007-03-22 | Renesas Technology Corp | 半導体装置 |
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JP5259978B2 (ja) * | 2006-10-04 | 2013-08-07 | ローム株式会社 | 半導体装置の製造方法 |
US8120161B2 (en) * | 2007-04-10 | 2012-02-21 | Infineon Technologies Ag | Semiconductor module including semiconductor chips coupled to external contact elements |
JP5107839B2 (ja) * | 2008-09-10 | 2012-12-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8168490B2 (en) * | 2008-12-23 | 2012-05-01 | Intersil Americas, Inc. | Co-packaging approach for power converters based on planar devices, structure and method |
US8354303B2 (en) * | 2009-09-29 | 2013-01-15 | Texas Instruments Incorporated | Thermally enhanced low parasitic power semiconductor package |
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JP2013026316A (ja) | 2011-07-19 | 2013-02-04 | Semiconductor Components Industries Llc | 半導体装置およびその製造方法 |
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JP2003124436A (ja) | 2001-10-19 | 2003-04-25 | Hitachi Ltd | 半導体装置 |
US20050121777A1 (en) | 2003-12-03 | 2005-06-09 | Toshiyuki Hata | Semiconductor device |
JP2005167013A (ja) | 2003-12-03 | 2005-06-23 | Renesas Technology Corp | 半導体装置及び電子装置 |
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JP2008104348A (ja) | 2007-11-05 | 2008-05-01 | Renesas Technology Corp | 半導体装置および電源システム |
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JP2020098811A (ja) | 2020-06-25 |
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