JP4691624B2 - ラティラルバイポーラcmos集積回路 - Google Patents
ラティラルバイポーラcmos集積回路 Download PDFInfo
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- JP4691624B2 JP4691624B2 JP2005504146A JP2005504146A JP4691624B2 JP 4691624 B2 JP4691624 B2 JP 4691624B2 JP 2005504146 A JP2005504146 A JP 2005504146A JP 2005504146 A JP2005504146 A JP 2005504146A JP 4691624 B2 JP4691624 B2 JP 4691624B2
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- 239000000758 substrate Substances 0.000 claims description 45
- 238000004088 simulation Methods 0.000 description 23
- 238000010586 diagram Methods 0.000 description 15
- 230000003321 amplification Effects 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 7
- 238000003199 nucleic acid amplification method Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0018—Special modifications or use of the back gate voltage of a FET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Description
図9は、比較例であり、全体が400で表される従来構造のDTCMOS(Dynamic Threshold Voltage CMOS)インバータ回路の等価回路図である。また、図10、11は、DTCMOS400に含まれるnチャネルMOSトランジスタ(以下、「DTMOS」と呼ぶ。)410とpチャネルDTMOS420との等価回路図である。
VT0(n)=0.178V
K1=0.47V1/2
K2=−0.057
φS=0.82V
μ0=550cm2/V/Sec
tOX=7nm
hFE=100
IS=2×10−15A
Area=1
VT0(p)=−0.238V
K1=0.45V1/2
K2=−0.03
φS=0.79V
μ0=220cm2/V/Sec
tOX=7nm
hFE=100
IS=2×10−15A
Area=2
図17は、nチャネルLBMOS(Wn=1.05μm)において、Vbe=0.7Vに固定して、Vgsを変化させた場合の、電流Idsと電圧Vdsとの関係である。また、図18は、Vbe=0.7V、Vds=1.0Vに固定した場合の、電流Idsと電圧Vgsとの関係である。図17、18において、縦軸の電流は対数で表されており、電流が急激に増加していることがわかる。
Claims (3)
- nチャネルMOSトランジスタとpチャネルMOSトランジスタとを含むインバータ回路であって、
該nチャネルMOSトランジスタ及び該pチャネルMOSトランジスタのゲートに接続されたゲート入力端子Vinと、
該nチャネルMOSトランジスタ及び該pチャネルMOSトランジスタのドレインに接続された出力端子Voutと、
該nチャネルMOSトランジスタのp型サブストレートに接続されたp型ベース端子と、
該pチャネルMOSトランジスタのn型サブストレートに接続されたn型ベース端子の4つの端子を含み、
該nチャネルMOSトランジスタが、MOSトランジスタの動作モードと、該nチャネルMOSトランジスタに内在するnpnラティラルバイポーラトランジスタの動作モードとの混合モードで動作し、
該pチャネルMOSトランジスタが、MOSトランジスタの動作モードと、該pチネルMOSトランジスタに内在するpnpラティラルバイポーラトランジスタの動作モードとの混合モードで動作し、
上記インバータ回路が、上記ゲート入力端子Vin、上記p型ベース端子、及び上記n型ベース端子を入力端子とし、上記出力端子Voutを出力端子とし、
該ゲート入力端子Vinに入力された高レベル又は低レベルの電圧を、反転させたレベルの電圧として出力端子Voutから出力し、
該nチャネルMOSトランジスタの該p型ベース端子に接続された電流源Ibpと、該pチャネルMOSトランジスタの該n型ベース端子に接続された電流源Ibnとを含み、
該ゲート入力端子Vinへの入力電圧が一定の状態で、該電流源Ibp及び該電流源Ibnの電流は0に維持され、
該ゲート入力端子Vinへの入力電圧が低レベルから高レベルにスイッチングした場合に、該スイッチングに同期して該電流源Ibpから該p型ベース端子に順方向のパルス電流を流すとともに、
該ゲート入力端子Vinへの入力電圧が高レベルから低レベルへスイッチングした場合に、該スイッチングに同期して該電流源Ibnから該n型ベース端子に順方向のパルス電流を流すことを特徴とするラティラルバイポーラCMOS集積回路。 - 更に、電圧源Vddと接地源Gndとを含み、
上記電流源Ibpが、ソース端子、ドレイン端子及びサブストレート端子を含むプルアップ型pチャネルMOSトランジスタであって、該ドレイン端子が上記p型ベース端子に接続され、該ソース端子と該サブストレート端子が該電圧源Vddに接続されたプルアップ型pチャネルMOSトランジスタからなり、
上記電流源Ibnが、ソース端子、ドレイン端子及びサブストレート端子を含むプルダウン型nチャネルMOSトランジスタであって、該ドレイン端子が上記n型ベース端子に接続され、該ソース端子と該サブストレート端子が該接地源Gndに接続されたプルダウン型nチャネルMOSトランジスタからなることを特徴とする請求項1に記載のラティラルバイポーラCMOS集積回路。 - 上記nチャネルMOSトランジスタと上記pチャネルMOSトランジスタとを含むインバータ回路を、上記MOSトランジスタの動作モードでCMOS標準セルとして使用し、該CMOS標準セルの出力に大きな負荷が接続された場合に、上記混成モードで使用することを特徴とする請求項1または2のいずれかに記載のラティラルバイポーラCMOS集積回路。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005504146A JP4691624B2 (ja) | 2003-03-31 | 2004-03-11 | ラティラルバイポーラcmos集積回路 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003095116 | 2003-03-31 | ||
JP2003095116 | 2003-03-31 | ||
JP2005504146A JP4691624B2 (ja) | 2003-03-31 | 2004-03-11 | ラティラルバイポーラcmos集積回路 |
PCT/JP2004/003208 WO2004088750A1 (ja) | 2003-03-31 | 2004-03-11 | ラティラルバイポーラcmos集積回路 |
Publications (2)
Publication Number | Publication Date |
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JPWO2004088750A1 JPWO2004088750A1 (ja) | 2006-07-06 |
JP4691624B2 true JP4691624B2 (ja) | 2011-06-01 |
Family
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JP2005504146A Expired - Fee Related JP4691624B2 (ja) | 2003-03-31 | 2004-03-11 | ラティラルバイポーラcmos集積回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20070096219A1 (ja) |
EP (1) | EP1617477A4 (ja) |
JP (1) | JP4691624B2 (ja) |
WO (1) | WO2004088750A1 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008072095A (ja) * | 2006-08-18 | 2008-03-27 | Advanced Lcd Technologies Development Center Co Ltd | 電子装置、表示装置、インターフェイス回路、差動増幅装置 |
US8531001B2 (en) * | 2011-06-12 | 2013-09-10 | International Business Machines Corporation | Complementary bipolar inverter |
US20140073106A1 (en) | 2012-09-12 | 2014-03-13 | International Business Machines Corporation | Lateral bipolar transistor and cmos hybrid technology |
US8958187B2 (en) | 2012-11-09 | 2015-02-17 | Analog Devices, Inc. | Active detection and protection of sensitive circuits against transient electrical stress events |
FR3001571B1 (fr) * | 2013-01-30 | 2016-11-25 | Commissariat Energie Atomique | Procede de programmation d'un dispositif memoire a commutation bipolaire |
US9293912B2 (en) | 2013-09-11 | 2016-03-22 | Analog Devices, Inc. | High voltage tolerant supply clamp |
US9634482B2 (en) | 2014-07-18 | 2017-04-25 | Analog Devices, Inc. | Apparatus and methods for transient overstress protection with active feedback |
US9966459B2 (en) * | 2014-09-04 | 2018-05-08 | Globalfoundries Inc. | Symmetrical lateral bipolar junction transistor and use of same in characterizing and protecting transistors |
US10199369B2 (en) | 2016-03-04 | 2019-02-05 | Analog Devices, Inc. | Apparatus and methods for actively-controlled transient overstress protection with false condition shutdown |
US10177566B2 (en) | 2016-06-21 | 2019-01-08 | Analog Devices, Inc. | Apparatus and methods for actively-controlled trigger and latch release thyristor |
US10734806B2 (en) | 2016-07-21 | 2020-08-04 | Analog Devices, Inc. | High voltage clamps with transient activation and activation release control |
US10861845B2 (en) | 2016-12-06 | 2020-12-08 | Analog Devices, Inc. | Active interface resistance modulation switch |
US11387648B2 (en) | 2019-01-10 | 2022-07-12 | Analog Devices International Unlimited Company | Electrical overstress protection with low leakage current for high voltage tolerant high speed interfaces |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61289658A (ja) * | 1985-06-18 | 1986-12-19 | Fujitsu Ltd | 半導体集積回路 |
JPH1027859A (ja) * | 1996-07-09 | 1998-01-27 | Yamaha Corp | 複合半導体素子 |
JPH10189957A (ja) * | 1996-12-26 | 1998-07-21 | Mitsubishi Electric Corp | 半導体集積回路 |
JP2000332132A (ja) * | 1999-04-20 | 2000-11-30 | Internatl Business Mach Corp <Ibm> | 本体スイッチ式soi(絶縁体上シリコン)回路及びその形成方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0564204A3 (en) * | 1992-03-30 | 1994-09-28 | Mitsubishi Electric Corp | Semiconductor device |
KR0169157B1 (ko) * | 1993-11-29 | 1999-02-01 | 기다오까 다까시 | 반도체 회로 및 mos-dram |
US5543650A (en) * | 1995-01-12 | 1996-08-06 | International Business Machines Corporation | Electrostatic discharge protection circuit employing a mosfet device |
JP3175521B2 (ja) * | 1995-01-27 | 2001-06-11 | 日本電気株式会社 | シリコン・オン・インシュレータ半導体装置及びバイアス電圧発生回路 |
JP3682801B2 (ja) * | 1995-06-22 | 2005-08-17 | 株式会社デンソー | スイッチ回路 |
JP2917957B2 (ja) * | 1997-02-14 | 1999-07-12 | 日本電気株式会社 | 発振回路および遅延回路 |
US6249027B1 (en) * | 1998-06-08 | 2001-06-19 | Sun Microsystems, Inc. | Partially depleted SOI device having a dedicated single body bias means |
US6147508A (en) * | 1998-08-20 | 2000-11-14 | International Business Machines Corp. | Power consumption control mechanism and method therefor |
KR100353471B1 (ko) * | 1998-12-23 | 2002-11-18 | 주식회사 하이닉스반도체 | 데이터 센스 앰프 |
US6246027B1 (en) * | 1999-10-28 | 2001-06-12 | Vivette Griffiths | Electrically heated tool for cutting hair |
US6864539B2 (en) * | 2002-07-19 | 2005-03-08 | Semiconductor Technology Academic Research Center | Semiconductor integrated circuit device having body biasing circuit for generating forward well bias voltage of suitable level by using simple circuitry |
-
2004
- 2004-03-11 WO PCT/JP2004/003208 patent/WO2004088750A1/ja active Application Filing
- 2004-03-11 JP JP2005504146A patent/JP4691624B2/ja not_active Expired - Fee Related
- 2004-03-11 US US10/551,266 patent/US20070096219A1/en not_active Abandoned
- 2004-03-11 EP EP04719623A patent/EP1617477A4/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61289658A (ja) * | 1985-06-18 | 1986-12-19 | Fujitsu Ltd | 半導体集積回路 |
JPH1027859A (ja) * | 1996-07-09 | 1998-01-27 | Yamaha Corp | 複合半導体素子 |
JPH10189957A (ja) * | 1996-12-26 | 1998-07-21 | Mitsubishi Electric Corp | 半導体集積回路 |
JP2000332132A (ja) * | 1999-04-20 | 2000-11-30 | Internatl Business Mach Corp <Ibm> | 本体スイッチ式soi(絶縁体上シリコン)回路及びその形成方法 |
Also Published As
Publication number | Publication date |
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EP1617477A1 (en) | 2006-01-18 |
EP1617477A4 (en) | 2008-12-10 |
WO2004088750A1 (ja) | 2004-10-14 |
JPWO2004088750A1 (ja) | 2006-07-06 |
US20070096219A1 (en) | 2007-05-03 |
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