JP4600672B2 - Method of joining substrate and device using Au-Sn alloy solder paste - Google Patents

Method of joining substrate and device using Au-Sn alloy solder paste Download PDF

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JP4600672B2
JP4600672B2 JP2005250798A JP2005250798A JP4600672B2 JP 4600672 B2 JP4600672 B2 JP 4600672B2 JP 2005250798 A JP2005250798 A JP 2005250798A JP 2005250798 A JP2005250798 A JP 2005250798A JP 4600672 B2 JP4600672 B2 JP 4600672B2
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substrate
alloy solder
alloy
solder paste
led element
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JP2007061857A (en
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石川　　雅之
正好 小日向
昭史 三島
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Mitsubishi Materials Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of joining to a substrate, an element for which long-term heating is undesirable, for example, an LED (light emitting diode) element, by using an Au-Sn alloy solder paste in particular. <P>SOLUTION: In the method of joining a substrate and an element by using the Au-Sn alloy solder paste 2, the paste 2 is loaded or applied onto the substrate 1, and then reflow-processed in a non-oxidizing atmosphere. A molten Au-Sn alloy solder layer 4 is formed on the surface of the substrate 1, and a flux residue part 5 in its periphery. The element 3 is loaded on the molten Au-Sn alloy solder layer 4, held with heat, and then cooled; thus, the element is joined to the substrate 1. Thereafter, the flux residue part is washed and removed. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

この発明は、Ａｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法に関するものであり、特に高温で長時間の加熱すると特性が劣化したりまたは破損に繋がる素子、例えば、ＬＥＤ（発光ダイオード）素子をＡｕ−Ｓｎ合金はんだペーストを用いて基板に接合する方法に関するものである。   The present invention relates to a method for bonding a substrate and an element using an Au—Sn alloy solder paste, and particularly an element such as an LED (light emitting diode) whose characteristics deteriorate or damage when heated for a long time at a high temperature. The present invention relates to a method for bonding an element to a substrate using an Au—Sn alloy solder paste.

一般に、ＬＥＤ（発光ダイオード）素子、ＧａＡｓ光素子、ＧａＡｓ高周波素子、熱伝素子などの半導体素子と基板との接合、微細かつ高気密性が要求されるＳＡＷフィルター、水晶発振子などのパッケージ封止などには、Ａｇペースト、Ａｕ−Ｓｎ箔材、Ａｕバンプ、Ａｕ−Ｓｎ合金はんだペーストなどが使用されている。   In general, bonding of semiconductor elements such as LED (light emitting diode) elements, GaAs optical elements, GaAs high frequency elements, and heat transfer elements and substrates, SAW filters that require fine and high airtightness, sealing of packages such as crystal oscillators, etc. For example, Ag paste, Au—Sn foil material, Au bump, Au—Sn alloy solder paste and the like are used.

Ａｇペーストは、Ａｇ材料自身の熱伝導性が悪いだけでなく、基板と素子の間に発生するボイドが多い。つまり、ボイドにより接合領域が減少してしまい、熱抵抗を低下させると共に、接合部の信頼性にも問題があった。そのために、特に熱がこもると破損に繋がるようなＬＥＤ（発光ダイオード）素子は基板との接合部の熱伝導性が非常に重要であることから、ＬＥＤ（発光ダイオード）素子と基板との接合には熱伝導性が良くかつ信頼性が高い接合部を形成するＡｕ−Ｓｎ合金はんだ箔材(リボンなど)、Ａｕバンプ、Ａｕ−Ｓｎ合金はんだペーストが用いられている。   The Ag paste not only has poor thermal conductivity of the Ag material itself, but also has many voids generated between the substrate and the element. In other words, the bonding area is reduced by the void, and the thermal resistance is lowered, and there is a problem in the reliability of the bonded portion. For this reason, in particular, LED (light emitting diode) elements that cause damage when heat is trapped are very important in the thermal conductivity of the junction with the substrate. Au-Sn alloy solder foil materials (ribbons, etc.), Au bumps, and Au-Sn alloy solder pastes that form joints with good thermal conductivity and high reliability are used.

しかし、Ａｕ−Ｓｎはんだ合金箔材(リボンなど)は、材料自身の熱伝導性は高いが接合時の濡れ性が悪いため接合領域を十分に広く取ることができず、また箔材表面には酸化膜が多いため溶融したＡｕ−Ｓｎはんだ合金の流動性が悪い。そのため加熱溶融しながら荷重をかけて接合する工法もあるが、加熱時間を長く取らなければならないところから、熱を長時間かけることのできないＬＥＤ（発光ダイオード）素子に適用することができない。さらに、Ａｕ−Ｓｎはんだ合金箔材の場合、濡れ性が悪いことにより接合面積が小さいという欠点があった。   However, Au-Sn solder alloy foil materials (ribbons, etc.) have high thermal conductivity, but the wettability during bonding is poor, so that the bonding area cannot be made sufficiently wide. Since there are many oxide films, the fluidity of the molten Au—Sn solder alloy is poor. Therefore, there is a method of joining by applying a load while heating and melting, but it cannot be applied to an LED (light emitting diode) element that cannot apply heat for a long time because a long heating time must be taken. Furthermore, in the case of the Au—Sn solder alloy foil material, there is a drawback that the bonding area is small due to poor wettability.

また、Ａｕバンプ法による素子の接合は、素子全体にＡｕ−Ｓｎはんだ合金接合層が接合していないため、Ａｕ−Ｓｎはんだ合金接合層と接合していない部分の熱伝導が悪くなり、また、このＡｕバンプ法では３００℃以上の温度で荷重をかけながら接合を行なうが、３００℃以上高温を長時間かける必要があり、熱影響を受けて劣化しやすいＬＥＤ（発光ダイオード）素子に適用することができなかった。
そのため、近年、熱影響を受けて劣化しやすいＬＥＤ（発光ダイオード）素子の接合には接合信頼性の一層優れたＡｕ−Ｓｎ合金はんだペーストが多く用いられるようになってきた。このＡｕ−Ｓｎ合金はんだペーストは、Ｓｎ：１５〜２５質量％（好ましくはＳｎ：２０質量％）を含有し、残りがＡｕおよび不可避不純物からなる組成を有するＡｕ−Ｓｎ共晶合金ガスアトマイズ粉末とロジン、活性剤、溶剤および増粘剤からなる市販のフラックスとを混合して作られる。
このＡｕ−Ｓｎ合金はんだペーストを使用して素子と基板を接合すると接合部がＡｕ−Ｓｎはんだ合金であるので熱伝導性が良く接合信頼性も高いこと、ペーストであるので複数の接合部に一括供給でき、さらに一括熱処理できること、リフロー時にフラックスがＡｕ−Ｓｎはんだ合金表面を覆っているために酸化膜が少なく、そのため、接合時の溶融Ａｕ−Ｓｎはんだ合金の流動性が大きく、濡れが良くなって接合面積を拡大することができることから素子全面を接合することができること、さらに接合時に過剰な荷重をかける必要がないことなどのメリットがある。
このＡｕ−Ｓｎ合金はんだペーストを用いて基板と素子を接合するには、まず、図３（ａ）に示されるように、基板１にＡｕ−Ｓｎ合金はんだペースト２を搭載または塗布する。次に、このＡｕ−Ｓｎ合金はんだペースト２の上に図３（ｂ）に示されるように素子３を搭載し、この状態で加熱してリフロー処理を施したのち冷却すると、図３（ｃ）に示されるように、Ａｕ−Ｓｎ合金はんだ接合層４０を介してと基板１と素子３が接合し、Ａｕ−Ｓｎ合金はんだ接合層４０の周囲にフラックス残渣層５が形成される。この形成されたフラックス残渣層５は洗浄し除去して、図３（ｄ）に示されるように、接合が完了する（特許文献１または２など参照）。
特開２００３−１０５４６２ 特開２００３−２６０５８８ In addition, since the Au-Sn solder alloy bonding layer is not bonded to the entire element in the bonding of the element by the Au bump method, the heat conduction of the portion not bonded to the Au-Sn solder alloy bonding layer is deteriorated, In this Au bump method, bonding is performed while applying a load at a temperature of 300 ° C. or higher. However, it is necessary to apply a high temperature of 300 ° C. or higher for a long time, and it is applied to an LED (light emitting diode) element that is easily deteriorated due to thermal effects. I could not.
For this reason, in recent years, Au-Sn alloy solder pastes with higher bonding reliability have been frequently used for bonding LED (light-emitting diode) elements that are easily deteriorated under the influence of heat. This Au—Sn alloy solder paste contains Sn: 15 to 25% by mass (preferably Sn: 20% by mass), and the remainder is composed of Au and inevitable impurities. Au—Sn eutectic alloy gas atomized powder and rosin It is made by mixing a commercially available flux consisting of an activator, a solvent and a thickener.
When an element and a substrate are bonded using this Au—Sn alloy solder paste, the bonding portion is an Au—Sn solder alloy, so that the thermal conductivity is good and the bonding reliability is high. It can be supplied and further heat treated at the same time, and the flux covers the surface of the Au-Sn solder alloy during reflow, so there is little oxide film. Therefore, the fluidity of the molten Au-Sn solder alloy at the time of joining is large and the wetting is improved. Therefore, there is an advantage that the entire surface of the element can be bonded since the bonding area can be expanded, and that it is not necessary to apply an excessive load at the time of bonding.
In order to join the substrate and the element using this Au—Sn alloy solder paste, first, as shown in FIG. 3A, the Au—Sn alloy solder paste 2 is mounted or applied to the substrate 1. Next, the element 3 is mounted on the Au—Sn alloy solder paste 2 as shown in FIG. 3B, heated in this state, subjected to reflow treatment, and then cooled. As shown in FIG. 5, the substrate 1 and the element 3 are bonded together through the Au—Sn alloy solder bonding layer 40, and the flux residue layer 5 is formed around the Au—Sn alloy solder bonding layer 40. The formed flux residue layer 5 is washed and removed, and the joining is completed as shown in FIG. 3D (see Patent Document 1 or 2).
JP 2003-105462 A JP 2003-260588 A

前記Ａｕ−Ｓｎ合金はんだペースト２の上に図３（ｂ）に示されるように素子３を搭載し、この状態で加熱してリフロー処理を施すことにより、図３（ｃ）に示されるように、Ａｕ−Ｓｎ合金はんだ接合層４０を介してと基板１と素子３を接合させるためには高温で長時間加熱のリフロー処理を施さなければならず、高温で長時間の加熱に弱いＬＥＤ素子などの素子にはこの接合方法は好ましくない。さらに図３（ｂ）に示されるようにＡｕ−Ｓｎ合金はんだペースト２の上に素子３を搭載し、この状態で加熱してリフロー処理を施すと、Ａｕ−Ｓｎ合金はんだペースト２の上に素子３が被さっているために、Ａｕ−Ｓｎ合金はんだペースト２が溶融するに際してペーストから発生したガスが逃げ場を失ってボイドが発生しやすく、ボイドが発生すると素子３と基板１との接合面積が少なくなり、接合面積が少なくなると素子３に発生した熱の放熱性が悪くなるなどの欠点があった。   As shown in FIG. 3C, the element 3 is mounted on the Au—Sn alloy solder paste 2 as shown in FIG. 3B, and heated in this state to perform a reflow process. In order to join the substrate 1 and the element 3 through the Au—Sn alloy solder joint layer 40, a reflow treatment for a long time at high temperature must be performed, and an LED element that is vulnerable to a long time heating at a high temperature. This joining method is not preferable for the above-mentioned elements. Further, as shown in FIG. 3B, when the element 3 is mounted on the Au—Sn alloy solder paste 2 and heated in this state and subjected to reflow treatment, the element is placed on the Au—Sn alloy solder paste 2. 3, when the Au—Sn alloy solder paste 2 is melted, the gas generated from the paste loses the escape field and is likely to generate voids. When the voids are generated, the bonding area between the element 3 and the substrate 1 is small. Therefore, when the bonding area is reduced, there is a disadvantage that heat dissipation of the heat generated in the element 3 is deteriorated.

そこで、本発明者らは、これら課題を解決すべく研究を行った。その結果、Ａｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布したのち素子を搭載することなくリフロー処理して基板表面に溶融Ａｕ−Ｓｎ合金はんだ層およびその周囲にフラックス残渣部分を形成し、次いで前記溶融Ａｕ−Ｓｎ合金はんだ層の上に素子を搭載し加熱保持したのち冷却することにより素子を基板に接合し、次いでフラックス残渣部分を洗浄して除去すると、素子を基板の上に形成された溶融Ａｕ−Ｓｎ合金はんだ層の上に直接搭載してはんだ付けすることから、フラックスから発生するガスの影響を受けることなくはんだ付けすることができ、したがって、接合部にボイドの発生が少なくなって接合部の熱放出性の低下が少なくなり、さらに素子を短時間の加熱処理で基板に接合することができるために特に熱に弱いＬＥＤ素子の接合に有効であるという知見を得られたのである。   Therefore, the present inventors conducted research to solve these problems. As a result, after the Au—Sn alloy solder paste is mounted on or applied to the substrate, a reflow process is performed without mounting the element to form a molten Au—Sn alloy solder layer on the surface of the substrate and a flux residue portion around it, The device is mounted on the molten Au-Sn alloy solder layer, heated and held, and then cooled to join the device to the substrate, and then the flux residue portion is washed away to remove the element formed on the substrate. Since it is directly mounted on the Au-Sn alloy solder layer and soldered, it can be soldered without being affected by the gas generated from the flux, and therefore, the generation of voids at the joint is reduced. L is particularly vulnerable to heat because the reduction in heat release of the part is reduced and the element can be bonded to the substrate by a short heat treatment. It was obtained a finding that it is effective for bonding D element.

この発明は、かかる知見に基づいて成されたものであって、
（１）Ａｕ−Ｓｎ合金粉末とフラックスとを混合して得られたＡｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布したのち非酸化性雰囲気中でリフロー処理して基板表面に溶融Ａｕ−Ｓｎ合金はんだ層およびその周囲にフラックス残渣部分を形成し、前記溶融Ａｕ−Ｓｎ合金はんだ層の上にＬＥＤ素子を搭載し、非酸化性雰囲気中で加熱保持したのち冷却することにより、前記ＬＥＤ素子を基板に接合し、次いでフラックス残渣部分を洗浄して除去するＡｕ−Ｓｎ合金はんだペーストを用いた基板とＬＥＤ素子の接合方法、に特徴を有するものである。 This invention is made based on such knowledge,
(1) An Au—Sn alloy solder paste obtained by mixing Au—Sn alloy powder and a flux is mounted on or applied to a substrate, and then reflow-treated in a non-oxidizing atmosphere to melt the Au—Sn alloy on the substrate surface. A flux residue portion is formed on the solder layer and the periphery thereof, and the LED element is mounted on the molten Au-Sn alloy solder layer , heated and held in a non-oxidizing atmosphere, and then cooled , whereby the LED element is mounted on the substrate. And then, a method of joining the substrate and the LED element using the Au—Sn alloy solder paste, in which the flux residue portion is washed and removed.

この発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法を図面に基づいて具体的に説明する。図１はこの発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法を説明するための斜視説明図である。   A method of joining a substrate and an element using the Au—Sn alloy solder paste of the present invention will be specifically described with reference to the drawings. FIG. 1 is a perspective explanatory view for explaining a method of joining a substrate and an element using the Au—Sn alloy solder paste of the present invention.

図１（ａ）に示されるように、基板１にＡｕ−Ｓｎ合金はんだペースト２を搭載または塗布し、この状態で非酸化性雰囲気中でリフロー処理を施すと、図１（ｂ）に示されるように、Ａｕ−Ｓｎ合金はんだペースト２が溶融して溶融Ａｕ−Ｓｎ合金はんだ層４とその周囲にフラックス残渣層５が形成される。その後、図１（ｃ）に示されるように、溶融Ａｕ−Ｓｎ合金はんだ層４の上に素子３を搭載し、非酸化性雰囲気中でこの状態に短時間加熱保持したのち冷却することにより、図１（ｄ）に示されるように、素子３を基板１にＡｕ−Ｓｎ合金はんだ接合層４０を介して接合し、フラックス残渣層５を洗浄して終了する。   As shown in FIG. 1A, when an Au—Sn alloy solder paste 2 is mounted or applied to the substrate 1 and reflow treatment is performed in this state in a non-oxidizing atmosphere, the result shown in FIG. As described above, the Au—Sn alloy solder paste 2 is melted to form a molten Au—Sn alloy solder layer 4 and a flux residue layer 5 therearound. Thereafter, as shown in FIG. 1 (c), the element 3 is mounted on the molten Au—Sn alloy solder layer 4, and is heated and held in this state for a short time in a non-oxidizing atmosphere, and then cooled. As shown in FIG. 1D, the element 3 is bonded to the substrate 1 via the Au—Sn alloy solder bonding layer 40, and the flux residue layer 5 is washed to finish.

この場合、図示されてはいないが、基板にＡｕ−Ｓｎ合金はんだペーストを搭載または塗布し、この状態で非酸化性雰囲気中でリフロー処理を施したのち冷却して凝固したＡｕ−Ｓｎ合金はんだ層を形成し、その後、再度リフロー処理を施して図１（ｂ）に示されるようなＡｕ−Ｓｎ合金はんだペースト２が溶融して溶融Ａｕ−Ｓｎ合金はんだ層４とその周囲にフラックス残渣層５を形成してもよい。
さらに、この発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板とＬＥＤ素子の接合方法では、基板１の上の溶融Ａｕ−Ｓｎ合金はんだ層４の上に素子３を搭載し、図２（ｃ）に示されるように、素子３に荷重Ｆをかけながら、非酸化性雰囲気中で短時間その状態に加熱保持して、図２（ｄ）に示されるように、素子３を基板１にＡｕ−Ｓｎ合金はんだ接合層４０を介して接合し、その後洗浄して、図２（ｅ）に示されるように、接合を終了することが一層好ましい。
したがって、この発明は、
（２）Ａｕ−Ｓｎ合金粉末とフラックスとを混合して得られたＡｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布したのち非酸化性雰囲気中でリフロー処理して基板表面に溶融Ａｕ−Ｓｎ合金はんだ層およびその周囲にフラックス残渣部分を形成し、前記溶融Ａｕ−Ｓｎ合金はんだ層の上にＬＥＤ素子を搭載し、該ＬＥＤ素子に荷重をかけながら、非酸化性雰囲気中で加熱保持したのち冷却することにより、前記ＬＥＤ素子を基板に接合し、次いでフラックス残渣部分を洗浄して除去するＡｕ−Ｓｎ合金はんだペーストを用いた基板とＬＥＤ素子の接合方法、に特徴を有するものである。 In this case, although not shown in the figure, an Au—Sn alloy solder layer is mounted or coated with an Au—Sn alloy solder paste on the substrate, reflowed in a non-oxidizing atmosphere, and then cooled and solidified. After that, a reflow process is performed again to melt the Au—Sn alloy solder paste 2 as shown in FIG. 1B, and a molten Au—Sn alloy solder layer 4 and a flux residue layer 5 around it are formed. It may be formed.
Furthermore, in the bonding method of the substrate and the LED element using the Au—Sn alloy solder paste of the present invention, the element 3 is mounted on the molten Au—Sn alloy solder layer 4 on the substrate 1, and FIG. As shown in FIG. 2, while applying a load F to the element 3, the element 3 is heated and held in that state for a short time in a non-oxidizing atmosphere, and as shown in FIG. More preferably, bonding is performed via the Sn alloy solder bonding layer 40, and then the cleaning is performed to finish the bonding as shown in FIG.
Therefore, the present invention
(2) Au-Sn alloy solder paste obtained by mixing Au-Sn alloy powder and flux is mounted on or applied to a substrate, and then reflow-treated in a non-oxidizing atmosphere to melt the Au-Sn alloy on the substrate surface. A flux residue portion is formed on the solder layer and the periphery thereof, an LED element is mounted on the molten Au-Sn alloy solder layer, and the LED element is heated and held in a non-oxidizing atmosphere while being loaded, and then cooled. Thus , the LED element is bonded to the substrate, and then the substrate and the LED element are bonded using the Au—Sn alloy solder paste, in which the flux residue portion is washed and removed.

図２は前記（２）記載のこの発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法を説明するための斜視説明図である。図２に示される基板と素子の接合方法は、図２（ｃ）に示されるように、素子３を溶融Ａｕ−Ｓｎ合金はんだ層４の上に搭載し、素子３に荷重Ｆをかけながらその状態に加熱保持することが一層好ましい。図１と図２とでは、素子３にかける圧力の有無が相違するのみであるから、図２の詳細な説明は省略する。   FIG. 2 is a perspective view for explaining a method of joining a substrate and an element using the Au—Sn alloy solder paste of the present invention described in (2). 2A and 2B, as shown in FIG. 2C, the element 3 is mounted on the molten Au—Sn alloy solder layer 4 and a load F is applied to the element 3 while the element 3 is applied. It is more preferable to heat and maintain the state. FIG. 1 and FIG. 2 are different only in the presence or absence of pressure applied to the element 3, and thus detailed description of FIG. 2 is omitted.

この発明のＡｕ−Ｓｎ合金はんだペーストを用いた接合方法によると、基板１と素子３の間の接合部にボイドの発生が少なくなって素子に発生した熱が放熱し易く、さらに基板１と素子３を接合するに必要な加熱時間を短くすることができるので高温で長時間の加熱に弱いＬＥＤ素子などの素子の接合に適しているなど産業上優れた効果をもたらすものである。   According to the bonding method using the Au—Sn alloy solder paste of the present invention, the generation of voids is reduced at the bonding portion between the substrate 1 and the element 3, and the heat generated in the element is easily radiated. Since the heating time required for bonding 3 can be shortened, the present invention provides industrially superior effects such as being suitable for bonding elements such as LED elements that are vulnerable to heating at high temperatures for a long time.

Ｓｎ：２０質量％を含有し、残部がＡｕからなる成分組成を有し平均粒径：２０μｍを有するＡｕ−Ｓｎ合金はんだ粉末を用意し、このＡｕ−Ｓｎ合金はんだ粉末に市販のロジン系フラックスを、ロジン系フラックス：７質量％、残部がＡｕ−Ｓｎ合金はんだ粉末の配合組成となるように配合し、混合してＡｕ−Ｓｎ合金はんだペーストを作製した。
さらに、ＬＥＤ素子およびＡｕメッキしたアルミナ製の基板を用意した。
実施例１
先に用意した基板の上に先に用意したＡｕ−Ｓｎ合金はんだペーストをピン転写方により搭載し、これを窒素雰囲気中の熱対流型炉に装入して２００℃、６０秒保持したのち、さらに３１０℃に３０秒間保持することによりリフロー処理を施して中央に溶融Ａｕ−Ｓｎ合金はんだ層を有しかつその周囲にフラックス残渣を有するＡｕ−Ｓｎ合金はんだペースト溶融部分が形成された。このＡｕ−Ｓｎ合金はんだペースト溶融部分における溶融Ａｕ−Ｓｎ合金はんだ層の上に素子を搭載し、この状態で基板を窒素雰囲気中、３１０℃、１０秒間加熱したのち冷却することにより基板表面にＡｕ−Ｓｎ合金はんだ接合層を介してＬＥＤ素子を接合した。接合部分を調べたところ、基板とＬＥＤ素子の間の接合面積は９５％に達し、基板とＬＥＤ素子の間のＡｕ−Ｓｎ合金はんだ接合層には５％のボイド面積しか見られなかった。 An Au—Sn alloy solder powder containing Sn: 20% by mass with the balance being composed of Au and having an average particle size of 20 μm was prepared, and a commercially available rosin flux was applied to the Au—Sn alloy solder powder. Rosin-based flux: 7% by mass, and the remainder was blended so as to have a blended composition of Au—Sn alloy solder powder, and mixed to prepare an Au—Sn alloy solder paste.
Furthermore, an LED element and an Au-plated alumina substrate were prepared.
Example 1
After mounting the previously prepared Au—Sn alloy solder paste on the previously prepared substrate by the pin transfer method, this was placed in a thermal convection furnace in a nitrogen atmosphere and held at 200 ° C. for 60 seconds, Furthermore, the reflow process was performed by hold | maintaining at 310 degreeC for 30 second, and the Au-Sn alloy solder paste fusion | melting part which has a fusion | melting Au-Sn alloy solder layer in the center and has a flux residue in the circumference | surroundings was formed. An element is mounted on the molten Au-Sn alloy solder layer in the melted portion of the Au-Sn alloy solder paste, and in this state, the substrate is heated at 310 ° C. for 10 seconds in a nitrogen atmosphere and then cooled to form Au on the substrate surface. The LED element was bonded via the Sn alloy solder bonding layer. When the joint portion was examined, the joint area between the substrate and the LED element reached 95%, and only a void area of 5% was found in the Au—Sn alloy solder joint layer between the substrate and the LED element.

なお、接合面積はＴｏｓｉｂａ ＩＴ＆Ｃｏｎｔｏｒｏｌ Ｓｙｓｔｅｍ‘ｓ Ｔｏｓｍｉｃｒｏｎ−６０９０ＦＤにより測定し、ボイド面積は透過Ｘ線により測定した。
実施例２
実施例１において、３１０℃に加熱された溶融Ａｕ−Ｓｎ合金はんだ層の上に載置したＬＥＤ素子に荷重をかけながら窒素雰囲気中、３１０℃に１０秒間保持することによりＬＥＤ素子を基板に接合した。接合部分を実施例１と同様にして調べたところ、基板とＬＥＤ素子の間の接合面積は９７％に達し、基板とＬＥＤ素子の間のＡｕ−Ｓｎ合金はんだ接合層には３％のボイド面積しか見られなかった。
従来例１
基板にＡｕ−Ｓｎ合金はんだペーストを実施例１と同様にして塗布し、次に、このＡｕ−Ｓｎ合金はんだペーストの上にＬＥＤ素子を搭載し、この状態で温度：２００℃、６０秒間加熱した後、さらに温度：３１０℃、３０秒間加熱してリフロー処理を施し、その後、冷却し、Ａｕ−Ｓｎ合金はんだ接合層を介してと基板とＬＥＤ素子を接合した。Ａｕ−Ｓｎ合金はんだ接合層の周囲にはフラックス残渣層が形成されていたので、実施例１と同様にしてフラックス残渣層を洗浄液で洗浄し除去し、接合部分を実施例１と同様にして調べたところ、基板とＬＥＤ素子の間の接合面積は６５％であり、基板とＬＥＤ素子の間のＡｕ−Ｓｎ合金はんだ接合層には３５％のボイド面積があった。 The junction area was measured by Tosiba IT & Control System's Tosmicron-6090FD, and the void area was measured by transmission X-ray.
Example 2
In Example 1, the LED element was bonded to the substrate by holding the LED element placed on the molten Au—Sn alloy solder layer heated to 310 ° C. for 10 seconds at 310 ° C. in a nitrogen atmosphere while applying a load. did. When the joint portion was examined in the same manner as in Example 1, the joint area between the substrate and the LED element reached 97%, and the Au—Sn alloy solder joint layer between the substrate and the LED element had a void area of 3%. It was only seen.
Conventional Example 1
An Au—Sn alloy solder paste was applied to the substrate in the same manner as in Example 1. Next, an LED element was mounted on the Au—Sn alloy solder paste, and heated at a temperature of 200 ° C. for 60 seconds in this state. Thereafter, the substrate was further reflowed by heating at a temperature of 310 ° C. for 30 seconds, then cooled, and the substrate and the LED element were bonded together via the Au—Sn alloy solder bonding layer. Since a flux residue layer was formed around the Au-Sn alloy solder joint layer, the flux residue layer was washed and removed with a cleaning liquid in the same manner as in Example 1, and the joint portion was examined in the same manner as in Example 1. As a result, the bonding area between the substrate and the LED element was 65%, and the Au—Sn alloy solder bonding layer between the substrate and the LED element had a void area of 35%.

実施例１〜２および従来例１に示される結果から、従来法では３１０℃、３０秒間加熱しても満足な接合ができないが、この発明の方法によると、ＬＥＤ素子を３１０℃、１０秒間加熱保持するだけで基板と素子を良好に接合することができことが分かる。   From the results shown in Examples 1 and 2 and Conventional Example 1, the conventional method cannot be satisfactorily bonded even if heated at 310 ° C. for 30 seconds, but according to the method of the present invention, the LED element is heated at 310 ° C. for 10 seconds. It can be seen that the substrate and the element can be satisfactorily bonded simply by holding.

この発明の方法により基板と素子を接合する工程を説明するための説明図である。It is explanatory drawing for demonstrating the process of joining a board | substrate and an element by the method of this invention. この発明の方法により基板と素子を接合する工程を説明するための説明図である。It is explanatory drawing for demonstrating the process of joining a board | substrate and an element by the method of this invention. 従来の方法により基板と素子を接合する工程を説明するための説明図である。It is explanatory drawing for demonstrating the process of joining a board | substrate and an element with the conventional method.

符号の説明Explanation of symbols

１：基板、
２：Ａｕ−Ｓｎ合金はんだペースト、
３：素子、
４：溶融Ａｕ−Ｓｎ合金はんだ層、
４０：Ａｕ−Ｓｎ合金はんだ接合層、
５：フラックス残渣層５。
1: substrate
2: Au—Sn alloy solder paste,
3: Element,
4: Molten Au—Sn alloy solder layer,
40: Au—Sn alloy solder joint layer,
5: Flux residue layer 5

Claims (3)

Ａｕ−Ｓｎ合金粉末とフラックスとを混合して得られたＡｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布したのち非酸化性雰囲気中でリフロー処理して基板表面に溶融Ａｕ−Ｓｎ合金はんだ層およびその周囲にフラックス残渣部分を形成し、前記溶融Ａｕ−Ｓｎ合金はんだ層の上にＬＥＤ素子を搭載し、非酸化性雰囲気中で加熱保持したのち冷却することにより、前記ＬＥＤ素子を基板に接合し、次いでフラックス残渣部分を洗浄して除去することを特徴とするＡｕ−Ｓｎ合金はんだペーストを用いた基板とＬＥＤ素子の接合方法。 An Au—Sn alloy solder paste obtained by mixing Au—Sn alloy powder and a flux is mounted on or applied to a substrate, and then reflow-treated in a non-oxidizing atmosphere, and a molten Au—Sn alloy solder layer and A flux residue portion is formed around the LED element, and the LED element is mounted on the molten Au-Sn alloy solder layer. The LED element is bonded to the substrate by heating and holding in a non-oxidizing atmosphere and then cooling. Then, the residue of the flux is washed and removed, and a method of joining the substrate and the LED element using the Au—Sn alloy solder paste. Ａｕ−Ｓｎ合金粉末とフラックスとを混合して得られたＡｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布したのち非酸化性雰囲気中でリフロー処理して基板表面に溶融Ａｕ−Ｓｎ合金はんだ層およびその周囲にフラックス残渣部分を形成し、前記溶融Ａｕ−Ｓｎ合金はんだ層の上にＬＥＤ素子を搭載し該ＬＥＤ素子に荷重をかけながら、非酸化性雰囲気中で加熱保持したのち冷却することにより、前記ＬＥＤ素子を基板に接合し、次いでフラックス残渣部分を洗浄して除去することを特徴とするＡｕ−Ｓｎ合金はんだペーストを用いた基板とＬＥＤ素子の接合方法。 An Au—Sn alloy solder paste obtained by mixing Au—Sn alloy powder and a flux is mounted on or applied to a substrate, and then reflow-treated in a non-oxidizing atmosphere, and a molten Au—Sn alloy solder layer and By forming a flux residue portion around it, mounting an LED element on the molten Au-Sn alloy solder layer, applying heat to the LED element , heating and holding in a non-oxidizing atmosphere, and then cooling , A method for bonding a substrate and an LED element using an Au—Sn alloy solder paste, wherein the LED element is bonded to a substrate, and then a flux residue portion is washed and removed. 前記Ａｕ−Ｓｎ合金はんだペーストは、Ｓｎ：１５〜２５質量％を含有し、残りがＡｕおよび不可避不純物からなる組成を有するＡｕ−Ｓｎ合金粉末とフラックスとを混合して得られたＡｕ−Ｓｎ合金はんだペーストであることを特徴とする請求項１または２記載のＡｕ−Ｓｎ合金はんだペーストを用いた基板とＬＥＤ素子の接合方法。 The Au—Sn alloy solder paste contains Sn: 15 to 25% by mass, and the remainder is Au—Sn alloy obtained by mixing an Au—Sn alloy powder having a composition composed of Au and inevitable impurities and a flux. The method for joining a substrate and an LED element using the Au-Sn alloy solder paste according to claim 1 or 2, wherein the solder paste is used.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10156311B2 (en) 2013-07-09 2018-12-18 Nordson Corporation Length-adjustable adapter device for connecting a system part of a plastics processing system to a pipeline

Families Citing this family (4)

* Cited by examiner, † Cited by third party
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JP4947345B2 (en) * 2005-11-24 2012-06-06 三菱マテリアル株式会社 Method of joining substrate and device using Au-Sn alloy solder paste
JP4924920B2 (en) * 2006-06-28 2012-04-25 三菱マテリアル株式会社 Method for bonding the entire bonding surface of an element to a substrate using an Au-Sn alloy solder paste
JP5391584B2 (en) * 2008-06-04 2014-01-15 三菱マテリアル株式会社 Method of joining substrate and device using Au-Sn alloy solder paste with less void generation
EP2290676A4 (en) * 2008-06-12 2012-01-11 Mitsubishi Materials Corp Method for joining substrate and object to be mounted using solder paste

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63130258A (en) * 1986-11-19 1988-06-02 Hitachi Ltd Junction structure
JPH05267825A (en) * 1992-03-18 1993-10-15 Tokuyama Soda Co Ltd Manufacture of pre-coated board
JPH08116170A (en) * 1994-08-22 1996-05-07 Seiko Epson Corp Method and apparatus for soldering and correcting soldering method for mounting using this apparatus, and component-mounted board
JPH08222844A (en) * 1995-02-16 1996-08-30 Pfu Ltd Method and electrode structure for mounting surface mount element
JP2003211282A (en) * 2002-01-22 2003-07-29 Sony Corp Creamy solder and method for producing creamy solder

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63130258A (en) * 1986-11-19 1988-06-02 Hitachi Ltd Junction structure
JPH05267825A (en) * 1992-03-18 1993-10-15 Tokuyama Soda Co Ltd Manufacture of pre-coated board
JPH08116170A (en) * 1994-08-22 1996-05-07 Seiko Epson Corp Method and apparatus for soldering and correcting soldering method for mounting using this apparatus, and component-mounted board
JPH08222844A (en) * 1995-02-16 1996-08-30 Pfu Ltd Method and electrode structure for mounting surface mount element
JP2003211282A (en) * 2002-01-22 2003-07-29 Sony Corp Creamy solder and method for producing creamy solder

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10156311B2 (en) 2013-07-09 2018-12-18 Nordson Corporation Length-adjustable adapter device for connecting a system part of a plastics processing system to a pipeline

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